JP4762663B2 - 半導体装置 - Google Patents
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- JP4762663B2 JP4762663B2 JP2005299574A JP2005299574A JP4762663B2 JP 4762663 B2 JP4762663 B2 JP 4762663B2 JP 2005299574 A JP2005299574 A JP 2005299574A JP 2005299574 A JP2005299574 A JP 2005299574A JP 4762663 B2 JP4762663 B2 JP 4762663B2
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- 239000004065 semiconductor Substances 0.000 title claims description 37
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0828—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in composite switches
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- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/18—Modifications for indicating state of switch
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
図1は、全体が100で表される、本実施の形態1にかかる絶縁ゲートバイポーラトランジスタ(以後、「IGBT」とよぶ。)の下面図であり、図2は、図1に示すIGBT100の、紙面に平行な方向(図1に示すA方向)の断面図である。図2のうち、(a)は図1に符号10で表されたコレクタ電極の領域(領域(a))における断面図であり、(b)は図1に符号13で表されたコレクタ電極10を囲む環状のセンスコレクタ電極の領域(領域(b))における断面図である。
図3においては、抵抗層14の厚さをセンスコレクタ電極13より厚くすることで、コレクタ電極10とセンスコレクタ電極13との間に段差を形成し、更には、電極間に隙間を設けるようなパターン形成を行うことで、互いの接触が起こらない構造としている。
なお、抵抗層14についてはニッケルを用いる例を示したが、シリコン基板1のp+コレクタ層8中にp−層を形成し抵抗層とすることでも同様の働きを実現できる。
ここで、抵抗層14の抵抗値Rsは、抵抗層14の材料や膜厚を調整することにより、所定の設計値にすることができる。また、コレクタ電極10とセンスコレクタ電極13との間の電位差Vsは、抵抗層14における電圧降下に略相当する。
従って、電位差Vsを測定することにより、電位差Vsと抵抗値Rsから、コレクタ電極10を流れる電流Iを求めることができる。
なお、抵抗層14をニッケル層の代わりにp−層によって形成する場合は、p+コレクタ層のうち、コレクタ電極を形成する領域において、n型不純物を注入/拡散すること等によりp−層を形成する。
以下の実施の形態で述べる縦型MOSFETやダイオードについても同様に、このような一般的な製造技術を用いて作製できる。
本実施の形態1にかかるIGBT100では、外周部にセンスコレクタ電極13を形成することにより、電流密度の小さい外周部を有効に活用することができ、センスコレクタ電極13を設けても素子面積は大きくならない。また、エミッタ電極側のレイアウト変更も不要である。
なお、図1は、コレクタ電極10の周囲全体をセンスコレクタ電極13で囲む構造となっているが、部分的にセンスコレクタ電極13で囲む構造としても良い。一例としては、図4に示すような、コレクタ電極10の2辺にセンスコレクタ電極を配置する構造が考えられる。以下の実施の形態においても同様である。
図10は、全体が110で表される、本実施の形態2にかかる縦型MOSFETの下面図であり、図11は、図10に示すMOSFET110の、紙面に平行な方向の断面図である。図11において、(a)は図10に符号30で表されたドレイン電極の領域(領域(a))における断面図であり、(b)は図10に符号33で表されたドレイン電極30を囲む環状のセンスドレイン電極の領域(領域(b))における断面図である。
図10、11中、図1、2と同一符号は、同一又は相当箇所を示す。また、図1、2におけるエミッタ電極2、n−エミッタ層7、コレクタ層8の構成が、IGBTとMOSFETとの違いから、図10、11ではそれぞれソース電極22、ソース層27、ドレイン層28となることは、当業者にはよく知られた内容と言えるので詳細についての説明は省略する。
なお、抵抗層14については、シリコン基板1のn+ドレイン層28中にn−層を形成し抵抗層とすることでも、同様の働きを実現できる。
図12は、全体が120で表される、本実施の形態3にかかる縦型ダイオードの下面図であり、図13は、図12に示すダイオード120の、紙面に平行な方向の断面図である。図13において、(a)は図12に符号40で表されたカソード電極の領域における断面図であり、(b)は図12に符号43で表されたカソード電極40を囲む環状のセンスカソード電極の領域(領域(b))における断面図である。
図12、13中、図1、2と同一符号は、同一又は相当箇所を示す。
なお、抵抗層14については、シリコン基板1のn+カソード層48中にn−層を形成し抵抗層とすることでも、同様の働きを実現できる。
従って、実施の形態1の場合と同様に、電位差Vsを測定することにより、電位差Vsと抵抗層14の抵抗値Rsから電流Iを求めることができる。
Claims (3)
- 半導体基板を挟んで対向配置された電極間に流れる電流を制御する縦型の半導体装置であって、
対向する第1面と第2面とを有する半導体基板と、
該第1面に形成された第1電極と、
該第2面に、抵抗値Rsの高抵抗電極を介して形成された第2電極と、
該第2面の外周縁の少なくとも一部に沿って形成された第3電極とを含み、
該第1電極と該第2電極との間に電流Iを流した状態で、該第2電極と該第3電極との間の電位差Vsが測定され、該抵抗値Rsと該電位差Vsから該電流Iが検出されることを特徴とする半導体装置。 - 上記第3電極が、上記半導体基板の第2面の外周縁に沿って形成された環状電極であることを特徴とする請求項1に記載の半導体装置。
- 上記縦型の半導体装置が、絶縁ゲートバイポーラトランジスタ、縦型MOFFET、および縦型ダイオードからなる群から選択される一の半導体装置であることを特徴とする請求項1又は2に記載の半導体装置。
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JP2005299574A JP4762663B2 (ja) | 2005-10-14 | 2005-10-14 | 半導体装置 |
US11/463,499 US7560773B2 (en) | 2005-10-14 | 2006-08-09 | Semiconductor device |
DE102006044808A DE102006044808B4 (de) | 2005-10-14 | 2006-09-22 | Halbleitervorrichtung |
CNB2006101362306A CN100505299C (zh) | 2005-10-14 | 2006-10-13 | 半导体装置 |
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JP2005299574A JP4762663B2 (ja) | 2005-10-14 | 2005-10-14 | 半導体装置 |
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JP4762663B2 true JP4762663B2 (ja) | 2011-08-31 |
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US7656633B2 (en) * | 2006-12-26 | 2010-02-02 | Hamilton Sundstrand Corporation | Asymmetric fault detection and protection with AC solid state power controllers |
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EP4213386A1 (en) * | 2022-01-13 | 2023-07-19 | Infineon Technologies AG | Semiconductor assembly with semiconductor switching device and current sense unit |
CN117116939B (zh) * | 2023-10-25 | 2024-02-06 | 深圳腾睿微电子科技有限公司 | 绝缘栅双极晶体管芯片及其栅极电阻调整方法 |
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CH670334A5 (ja) * | 1986-09-16 | 1989-05-31 | Bbc Brown Boveri & Cie | |
US5061863A (en) * | 1989-05-16 | 1991-10-29 | Kabushiki Kaisha Toyoda Jidoshokki Seisakusho | Transistor provided with a current detecting function |
US5153696A (en) * | 1989-12-29 | 1992-10-06 | Nec Corporation | MOS FET with current sensing terminal |
JPH0493033A (ja) | 1990-08-08 | 1992-03-25 | Nec Corp | 電力用トランジスタ |
JPH05275704A (ja) | 1992-03-27 | 1993-10-22 | Masaya Maruo | 半導体装置 |
US5753938A (en) * | 1996-08-08 | 1998-05-19 | North Carolina State University | Static-induction transistors having heterojunction gates and methods of forming same |
JP3545590B2 (ja) * | 1997-03-14 | 2004-07-21 | 株式会社東芝 | 半導体装置 |
JP4024990B2 (ja) * | 2000-04-28 | 2007-12-19 | 株式会社ルネサステクノロジ | 半導体装置 |
EP1372197A1 (de) * | 2002-06-10 | 2003-12-17 | ABB Schweiz AG | Leistungshalbleiter mit variierbaren Parametern |
US6787885B2 (en) * | 2002-11-04 | 2004-09-07 | The United States Of America As Represented By The Secretary Of The Navy | Low temperature hydrophobic direct wafer bonding |
JP4073876B2 (ja) * | 2004-01-14 | 2008-04-09 | 三菱電機株式会社 | 半導体装置 |
US7669313B2 (en) * | 2005-07-11 | 2010-03-02 | Texas Instruments Incorporated | Method for fabricating a thin film resistor semiconductor structure |
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- 2006-09-22 DE DE102006044808A patent/DE102006044808B4/de active Active
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CN100505299C (zh) | 2009-06-24 |
DE102006044808B4 (de) | 2011-04-07 |
US20070085135A1 (en) | 2007-04-19 |
CN1949533A (zh) | 2007-04-18 |
US7560773B2 (en) | 2009-07-14 |
DE102006044808A1 (de) | 2007-04-26 |
JP2007109907A (ja) | 2007-04-26 |
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