CN1568534A - 铜制金属－绝缘体－金属电容器 - Google Patents

铜制金属－绝缘体－金属电容器 Download PDF

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CN1568534A
CN1568534A CNA028037634A CN02803763A CN1568534A CN 1568534 A CN1568534 A CN 1568534A CN A028037634 A CNA028037634 A CN A028037634A CN 02803763 A CN02803763 A CN 02803763A CN 1568534 A CN1568534 A CN 1568534A
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迈克尔·D.·阿马克思特
安德列斯·K.·奥古斯丁
杰拉尔德·R.·弗瑞斯
约翰·E.·海登瑞奇三世
加里·R.·许克尔
肯尼思·J.·斯坦
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Infineon Technologies North America Corp
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Abstract

采用铜制技术的平行板电容器形成在下方(在0.3μm之内)无铜的区域中，具有底部阻蚀层(104)，具有TiN层之下的铝层的复合底板(110)，氧化物电容器电介质(120)，和TiN的顶板(130)。制程涉及蚀刻顶板以留下电容器区域，蚀刻底板到在所有侧面具有余量的较大底部区域；在电容器顶板的顶表面之下沉积具有较高材料品质的层间电介质；开凿到顶板和底板，以及到下部互连的触孔，直到两步骤制程，同时穿透该底板之上的氮化物覆盖层，接着切通电容器电介质，并结束氮化物覆盖层的穿透。

Description

铜制金属-绝缘体-金属电容器
技术领域
本发明的领域为具有铜互连的集成电路。
背景技术
在形成集成电路的金属化的过程中，有时必须构建平行板电容器。在铝互连领域，这种制程已经开发成熟。
然而，在铜互连领域已经证明，开发适宜方法的困难超出预期。
铜金属表面中潜在的小丘和沟槽可在活性绝缘体或电容器板中造成薄化及不连续，导致过早磨损和潜在破裂。
发明内容
本发明涉及具有下部板的平行板电容器，所述下部板不包含铜层，并且不在电容器本身的区域中的下部铜互连上方延伸。
本发明的一个可选特征在于，具有较高电阻率的材料的顶衬垫覆盖具有较低电阻率的材料，例如铝的复合下部板。
本发明另一个特征在于，提供不包含铜并且在所有侧边小于底板的电容器顶板。
本发明另一个特征在于，沉积环绕电容器的层间电介质，其中至少在与电容器同层的电介质部份中具有高材料品质。
本发明另一个特征在于，电容器堆被一种材料覆盖，所述材料在蚀刻层间电介质以形成触点的期间提供较低的蚀刻率。此材料的厚度对于顶板及底板可不相同。
本发明另一个特征在于，将触孔开到电容器板的多步骤制程，其中第一步骤仅部份蚀刻穿过顶板和下部互连上的覆盖层，同时蚀刻一直穿过底板上的覆盖层，之后蚀刻穿过覆盖层的剩余部份。
另一个特征在于，位于下层铜金属化的顶部的硬电介质覆盖与电容器的底板之间的电介质(即ILD材料)层。此层在形成该底板期间保护硬电介质覆盖以及下层的铜。
附图说明
图1示出了将包含本发明电容器的集成电路的区域的横截面。
图2-8示出了制程中较晚阶段的相同区域。
具体实施方式
现在参考图1，所示为一部分集成电路的横截面。在该图的底部，以括号5表示的区域示意性代表硅基底，晶体管及下层互连。术语“下层互连”用来表示多晶互连(poly interconnects)，以及所有直到电容器底部的其他层。在此图中，它包含金属(铜)构件20。
初始电容器堆包含第一(氮化物Si3N4)覆盖层102(有利为正常金属化的部份)，牺牲(氧化物SiO2)层104，底板层110，电容器电介质层120，顶板层130以及第二覆盖层132。说明性地，在0.28μm接地规则(ground rule)(称为该线层级的最小尺寸)制程中，第一覆盖层102为50nm的氮化物，氧化物104为50nm的高品质氧化物，底板110包括35nm的铝，5nm的钛以及50nm的TiN，电介质120为50nm的高品质氧化物，顶板130为50nm的TiN，而第二覆盖层132为40nm的氮化物。电容器堆也能由不同材料及/或不同厚度的层构建。
电容器将在下层互连构件20之间的区域中形成。在本领域中，铜难于抛光已广为人知，但其出人意料地，已经发现，甚至当铜表面中的不规则性与那些铝顶表面中(50-75nm)的不规则性相同时，这些不规则性也可造成早期的可靠性失效。
因此，电容器本身没有任何部份(在图2中箭头152所示)能放置在电容器底板下方少于约0.3μm的铜下层互连上。图1中的括号7代表此最小容许垂直距离。本领域的技术人员通常会想到，至少将底板的接触部分直接放在下部构件之上，并且最好制作铜板。
说明性地，本发明使用由铜互连的衬垫材料制成的板。说明性地，衬垫材料为TiN，但任何其它相容的衬垫材料也可用来满足整体的制程热预算，金属污染规格等。
图2示出了第一蚀刻步骤和沉积的结果。第一蚀刻(Cl2/BCl3化学成分)后留下箭头152表示的区域，第一蚀刻定义了电容器顶板，并中止在该电容器电介质120上。此区域将被称为电容器区域(它可为长方形而非正方形)，并且是实际定义电容器的区域。已经执行40nm氮化物的第二沉积，留下电容器区域外的覆盖层134，以及电容器顶板152之上的层132’。增加132’的厚度的意义将在以下说明。
图3示出了底板蚀刻的结果，其中在BCl3/Cl2化学成分中蚀刻所有的层104，110，120及134。蚀刻被设计为中止在层104中，层104的蚀刻大体上比氮化物层102的蚀刻要慢。
箭头154指示的距离代表底板的垂直边缘和导体(下部互连构件20)之间的可允许最近水平距离，其中电容器具有其到上方层级的电气连接。将此距离称为电容器最近逼近距离。可能存在由来自顶板蚀刻的电介质120的电浆损伤造成的从顶板152下到底板110的潜在泄漏路径。
箭头155所指示的距离代表顶板的垂直边缘与底板的对应边缘之间的最近容许距离。将此距离称为泄漏最近逼近距离。此距离为控制板间泄漏所需，并在优选实施例中为1.0μm。为了容纳到底板的触点的区域，底板的范围可在一侧或多侧增加(大于泄漏最近逼近距离)。
图4示出了在电容器板组件周围沉积层间电介质140(氧化物)的结果。以消除可能形成泄漏路径的空洞的方式沉积(说明性地，以较低速率沉积)层间电介质140的下部(如标注146所示，图中为300nm)。术语“空洞”被用来表示20nm或更大的开口，以将其区别于氧化物的正常多孔性。为了能够再进行铜双重镶嵌制程，应用诸如CMP的平坦化制程以除去所产生的地形(topography)。
图5示出了蚀刻一组金属线141进入氧化物140中的结果。在说明性范例中，互连被用于双重镶嵌方案中。此并非必要，并可使用其它方案。
图6示出了蚀刻以下通孔的结果：右侧中止于氧化物120的通孔142，和以部分进入氮化物层的方式中止于氮化物层的通孔144与146。132’和102两层必须足够厚，以给出合理的余量，避免蚀刻穿透到下层。此部分蚀刻的目的是保护铜20免受用于下一步骤的氧化物蚀刻剂和后续阻蚀剂剥离制程的影响。
标记为156的距离代表顶板和最近电极之间的最近容许逼近距离，说明性地，为0.56μm。由电浆蚀刻损坏造成的有关泄漏路径从顶板130的右下角穿过电介质120。
图7示出了剥除孔144和146中剩余氮化物，从而露出孔146中的铜和孔144与142中的TiN的结果。通孔蚀刻制程必须使得不可能清除通孔底部的所有TiN。
可选地，可结合图6及7所示的步骤，其中使用CHF3/O2化学成分的单一蚀刻步骤蚀刻一直穿过氮化物层132’及102，并中止于顶板及底板。必须注意到，在此制程中，铜未被暴露，直到剥除氮化物覆盖层134-132’的剩余部分。
图8示出了沉积传统TiN衬垫162和铜电容器互连构件160和165的结果。
在图左侧，下层互连构件20及上层(和电容器)互连构件165之间的连接是铜制程技术中常规的。
结果，针对电容器板的触点是来自上方，而非来自下方，并且在两种状况中，触点位于TiN及TaN/Ta的层之间。穿透进入TiN的量值取决于制造公差。只要构成良好的触点，便不要求特定的数值。
电容器底板为复合结构，以便降低充电及放电的阻抗。顶部TiN具有约55ohm/square的电阻率，它将提供对于某些目的而言过大的RC时间常数。铝具有约2ohm/square的电阻率，所以使用铝层提供导电并且使用TiN层作屏蔽是有吸引力的。可选地，可使用具有约40ohm/square的阻抗并且较厚的TiN底板(没有铝)。芯片设计人员将必须做出判断，以确定特定电路是否需要额外的费用。
可选地，如果结构太高，造成保持平坦性的困难，可以在层间电介质中蚀刻凹陷，并且在凹陷中形成下部板。
此外，电容器可位于互连的最高层，使得不需要平坦化绝缘体140。而且，可使用不同的材料，例如铝，来制造与电容器的触点。铝通常被用作制造与外部芯片端子的触点的材料。
已列出的尺寸仅用于说明目的，本领域的技术人员可根据其需求调整所给的范例。举例而言，控制泄漏的最小距离将取决于沿相关路径的材料的电阻，以及在特定电路中可容忍的泄漏量。
虽然已经根据单一优选实施例说明了本发明，然而本领域的技术人员将可了解到，本发明在以下的权利要求的宗旨及范围之内可实施成不同的版本。

Claims (5)

1.一种使用铜互连在集成电路中制作平行板电容器的方法，包含以下步骤：
形成该集成电路的器件和下层互连，所述器件和下层互连至少部份由铜形成，其中包含一组顶部下层互连；
形成初始电容器堆，电容器堆包含具有第一覆盖厚度的第一覆盖层，置于所述第一覆盖层之上的导电底板层，置于所述导电底板层之上的电容器电介质层，置于所述电容器电介质层之上的导电顶板层，以及置于所述导电顶板层之上、具有第二覆盖厚度的第二覆盖层；
蚀刻所述第二覆盖层及所述顶板层，蚀刻中止在所述电容器电介质层上，以形成为所述第二覆盖层所覆盖的电容器顶板，所述电容器顶板包含在一电容器区域内，所述电容器区域从所述一组顶部下层互连中最靠近的一个偏移至少最小偏移距离；
形成具有第三覆盖厚度的第三覆盖层，由此，所述第三覆盖层覆盖所述电容器电介质层的暴露部份，所述导电顶板被顶板覆盖层覆盖，所述顶板覆盖层的顶板覆盖厚度基本等于所述第二及第三覆盖厚度的总和；
蚀刻所述第三覆盖层，所述电容器电介质层和所述底板层，从而形成覆盖所述电容器区域并在所有侧边延伸通过所述电容器顶板的电容器底板，由此，所述电容器底板的所有边缘从所述电容器顶板的对应边缘横向偏移至少顶板偏移距离；
沉积一层间电介质层；
在所述层间电介质中形成一组通孔，中止于所述第一和第三覆盖层；
清除所述底板上方以及所述顶板之外的底板接触区域中的所有所述第三覆盖层，并只清除顶板接触区域中所述顶板之上部分的所述第三覆盖层，从而在所述顶板接触区域中留下剩余厚度的所述第三覆盖层；
清除所述底板接触区域中的所述电容器电介质；
清除所述顶板触点区域中所有所述剩余厚度的所述第三覆盖层；及
在所述顶板接触区域及所述底板接触区域中形成由一组上层互连构成的电容器互连构件。
2.如权利要求1所述的方法，其中所述底板层为复合层，包含下部高导电性层和上部导电屏蔽层，并且清除所述底板接触区域中所述电容器电介质的所述步骤仅穿透所述上部导电屏蔽层。
3.如权利要求1所述的方法，其中衬垫材料沉积在所述顶板接触区域和所述底板接触区域；并且
铜层沉积在所述衬垫材料之上，并被光刻以形成所述上层互连组。
4.如权利要求1所述的方法，其中：
在所述层间电介质中形成一组通孔的所述步骤包含同时为所述上层互连组形成通孔；
仅清除所述顶板之上的部分所述第三覆盖层的所述步骤包含同时仅清除所述上层互连组的所述通孔中的部分所述第三覆盖层；
仅清除所述顶板接触区域中所有所述剩余厚度的所述第三覆盖层的所述步骤包含同时仅清除所述上层互连组的所述通孔中的、所有所述剩余厚度的所述第三覆盖层；
在所述顶板接触区域和所述底板接触区域中形成一组上层互连的电容器互连构件的所述步骤包含同时形成所述上层互连组的电容器互连构件。
5.如权利要求1所述的方法，其中所述电容器互连构件为铝。
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