CN1471802A - 一种集成电路载体的制作方法 - Google Patents

一种集成电路载体的制作方法 Download PDF

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CN1471802A
CN1471802A CNA018177603A CN01817760A CN1471802A CN 1471802 A CN1471802 A CN 1471802A CN A018177603 A CNA018177603 A CN A018177603A CN 01817760 A CN01817760 A CN 01817760A CN 1471802 A CN1471802 A CN 1471802A
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CN1235452C (zh
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卡·西尔弗布鲁克
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Abstract

一种制作集成电路载体的方法，该方法包括提供一个基板。划分至少一个容纳区，用以容纳基板上的集成电路。在至少一个容纳区周围设置多个岛屿界定部分。通过从基板去除材料在相邻的岛屿界定部分之间设置刚性降低装置。

Description

一种集成电路载体的制作方法
技术领域
本发明与集成电路封装有关。特别地，本发明与用于集成电路封装的集成电路载体有关。
技术背景
由于集成电路连接(引脚数目)的不断增加，采用球栅阵列封装将集成电路连接到印刷电路板的技术正在不断增加。这样使得集成电路倒装芯片凸点阵列由非常微小的间距重新分布到更大间距的球栅阵列，以连接到印刷电路板(PCB)上。
集成电路载体通常是指一个内插板(interposer)并且可以利用不同的材料例如陶瓷，或者塑性材料，例如BT(bismaleimide triazine)进行制造。
通过热传导而去除集成电路的热量，集成电路载体也可以起到散热片的作用。因此集成电路载体容易受到热应变的影响。
另外，包括集成电路、集成电路载体和PCB的电子封装组件具有多种采用不同机械性能的不同材料。在使用过程当中由于温度分布不均、几何尺寸、材料结构和热膨胀不一致而在元件内部产生复杂的热应变。
通常情况下，当前的集成电路是通过金或焊接凸点的球栅阵列连接到集成电路载体。同样，集成电路载体进一步通过更大的焊球的球栅阵列与集成电路板PCB相连。通常在PCB和集成电路载体之间与焊球接界处的热机械应变是非常严重的。这会导致焊球连接的剪切应变(shearing)。该问题被由PCB和集成电路载体之间热应变差的增加而引起的集成电路载体边缘长度的增加而扩大。通常集成电路载体边缘长度会随集成电路连接和焊球数目的增加而增加。
目前球栅阵列设计的可靠性受到集成电路引脚数目的限制。
通常焊球的最大弹性剪切应变大约为0.08％。申请人采用厚度为500微米固态硅载体，间距为1毫米、直径为500微米的焊球，厚度为700微米的PCB和边长16毫米的硅芯片进行实验计算，结果显示在封装最外部焊球的最大剪切应变为1.476％，该数值远大于焊球的塑变值。
该结果意味集成电路封装的最外部边缘的焊球产生最大的平移剪切应变。
正如《International Technology Road Map for Semiconductors》1999年版装配及封装一节第217页表59a所述，该版本是提出本申请时的最新版本，高性能集成电路引脚数目可达到1800个引脚的水平。在近期内，也就是说直到2005年，此技术要求说明对于引脚的数目超过3,000的高性能集成电路，如表所示，至今还没有解决方案。同样，如该出版物第219页表59b所述，在更长期的时间内，直到大约2014年，高性能集成电路封装引脚数目将达到9,000个的层次。同样，在表当中也显示没有针对该类型集成电路封装的解决方案。
以上几个方面的问题是本发明关注的焦点。
发明内容
本发明提供一种制作集成电路载体的方法，该方法包括以下步骤：
提供一个基板；
划分出至少一个容纳区，用以容纳基板上的集成电路，在上述至少一个容纳区周围设置多个岛屿界定部分；以及
通过从基板去除材料在相邻的岛屿界定部分之间设置刚性降低装置。
该方法包括在上述至少一个容纳区制作多个电触点，以及每个岛屿界定部分制作一个电端子，每个电端子通过电路层的走线轨迹电连接到一个电触点。
因此，该方法包括通过在基板上沉积金属层从而在基板表面形成电路层。然后，该方法可以包括对金属层进行蚀刻从而形成走线轨迹。
该方法可以包括通过在基板表面应用掩膜技术而划分出至少一个容纳区和岛屿界定部分。
然后通过蚀刻贯通基板，在曝露出基板之后进行光罩处理去除基板材料，而产生刚性降低装置。
优选地，该方法包括通过重入蚀刻的方法制作刚性降低装置从而提高载体的散热能力。
该方法能够在与上述至少一个容纳区和上述至少一个岛屿界定部分相邻的每个岛屿界定部分之间产生辅助刚性降低装置。同样，该方法可以通过在基板上进行贯通蚀刻的方法产生辅助刚性降低装置。
该方法可以包括采用具有绝缘层的末掺杂硅晶片而制作基板。该绝缘层可以作为蚀刻用的硬掩模。
该方法还能够通过在基板内制作凹槽来划分至少一个容纳区。该凹槽可以通过对基板蚀刻的方法而制作。
另外，该方法还包括通过在基板上制作通孔的方法划分至少一个容纳区，在基板上环绕通孔周围的区域设置多个电触点。同样，该通孔可以通过蚀刻基板的方法进行制作。
附图说明
下面结合附图和实例对本发明给予说明：
图1所示为概念性集成电路载体的部件平面示意图；
图2所示为本发明的集成电路载体的部分平面图；
图3所示为集成电路载体的一个具体实施例的局部透视图；
图4所示为集成电路载体第二具体实施例的局部透视图；
图5所示为集成电路载体第三具体实施例的局部透视图；
图6所示为集成电路载体第四具体实施例的局部透视图；
图7所示为使用中的集成电路载体的一个具体实施例的局部侧视图；
图8所示为使用中的集成电路载体的另一个具体实施例的局部侧视图；
图9所示为图8中圆圈A部分的放大示意图；
图10所示为集成电路载体以更大比例放大的局部侧视图；
图11所示为集成电路载体的另外一个具体实施例的侧视图；
图12也所示为集成电路载体的另外一个具体实施例的侧视图；
图13所示为安装多芯片模块的集成电路载体；
图14所示为安装多芯片模块的集成电路载体的侧视图。
具体实施方式
参考附图，本发明的集成电路载体通常用参考数字10来表示。附图的图2对集成电路载体给予更加具体的说明。
集成电路载体10具有一个容纳区12，用以安装一个集成电路或者芯片14(图7)。
多个岛屿界定部分或者岛屿16围绕着容纳区12。每个岛屿界定部分16其上具有一个电端子18，该电端子18与焊球20附着或者回流(reflow)。
每个岛屿界定部分16通过一个制作成蛇形件22形式的刚性降低装置连接到与其相邻的岛屿界定部分或者岛屿16。图1对此给予了详细的概念性说明。如图1所示，每个蛇形件22起到类似弹簧的作用，这样每个岛屿界定部分16相对于其相邻的岛屿界定部分16都具有一定的移动自由度。因此，印刷电路板24(图7至图9)和集成电路载体10之间的膨胀差可以通过相关蛇形件22的伸缩而得到补偿。由此，岛屿界定部分16上焊球20的剪切应变被显著降低，同时对焊球20产生的疲劳失效(fatigue fatilure)也相应下降。
下面结合图3到附图6对集成电路载体10的各种具体实施例给予具体说明。如图3所示，集成电路载体10通过采用单个曲线臂26的蛇形件22将每个岛屿界定部分16连接到其相邻的岛屿界定部分16。
在如图4所示的本发明的具体实施例中，每个蛇形件22通过由矩形连接件30而相互连接的一对并行臂28，将一个岛屿界定部分16连接到其相邻的岛屿界定部分16。
在图5所示的具体实施例中，每个蛇形件22通过具有三个彼此并行延伸的臂34的结构，将一个岛屿界定部分16连接到其相邻的岛屿界定部分16，相邻臂34通过矩形连接件32连接在一起。
在图6所显示的具体实施例中，每个具有五个并行臂36的蛇形件22将一个岛屿界定部分16连接到其相邻的岛屿界定部分16，并且，相邻的平等臂36通过一个矩形连接件38而连接。
为便于说明，在附图的图3到图6中所示的具体实施例可以在以下内容中分别称为：单臂26蛇形件22，两臂28蛇形件22，三臂34蛇形件22，以及五臂36蛇形件22。
如附图的图7到附图9所示，围绕容纳区12周围的岛屿界定部分16由之字形元件40所构成的第二刚性降低装置而连接到接收区，该之字形元件40可进一步降低作用在焊球20上的应变。
同样，如图7到图9所示，集成电路14通过焊接凸点44连接到容纳区12内的电触点42(图2)上。
集成电路载体10由与集成电路14相同的材料制成。因此，集成电路载体10是由具有一层二氧化硅绝缘层的硅而制成的。该绝缘层也可以作为蛇形件22的蚀刻掩膜，这一点将在以下内容给予更加细致的讨论。
在集成电路载体10的制作过程当中，首先提供一个硅晶片46。该晶片46可以为单晶硅或者多晶硅。
需要指明的是，附图的图10中所示的载体10的版本是接收区12与图7中所示的衬垫18相同一侧的载体10。如图8所示，当容纳区12位于与集成电路载体10的相对表面上时，电路层可应用在晶片46的两侧。这一点在图9中以较大比例进行了显示。在该具体实施例内，每条走线轨迹52都通过延伸到晶片46的电镀通孔58而电连接到其相关衬垫18上。
现在参照图11和12，对集成电路载体10的另外两个具体实施例给予说明。参照前面的附图，除非特别指定，相同部件采用相同的数字编号标注。
在图示的实例当中，容纳区12不是被限定在集成电路载体10的表面上，而是一个制作在集成电路载体10内的通道60。集成电路14贴附在由金属盖所构成的安装装置或者固定装置上，该装置连接在集成电路载体10的一个表面上。集成电路14的相反表面上具有可将集成电路连接到集成电路载体10上的多个连接衬垫。需要注意的是，在本实施例中，在集成电路载体10围绕通道60的部分设置以电触点。在如图11所述的具体实施例中，通过采取引线键合64而实现相互连接。也可采用球压焊或者楔焊的形式。在图12所示的具体实施例中，相互连接是通过采取是卷带自动接合(TAB)薄层66或者其他诸如梁式引线等平面连接形式。
结合图13，在以下内容对集成电路载体的进展给予了说明，并且采用参考数字70表示集成电路载体。参照前面的附图，除非特别指定，相同部件采用相同的参考数字。
在本发明的本实施例中，集成电路载体70是一个多芯片模块的基板70，安装有多个集成电路或者芯片，例如图13所示的72，74和76。芯片72，74和76即可以安装在集成电路载体70的表面，或者参照上述图10和图11中的情况，将芯片内嵌入集成电路载体70，如图14所示。
如上所述，蛇形件22具有不同的结构，例如，单臂26结构，两臂28结构，三臂34结构或者五臂36结构组态。通过有限元分析也可以采用例如四臂、六臂或者更多臂结构等其他结构，因此对于具有不同形状的蛇形件22和不同球栅的不同载体装置可产生不同的矩阵结构。下面所列举的矩阵是根据每排采用一到二十四个焊球，分别采用固态硅，固态Al2O3，固态BT制作载体，以及分别采用单臂26蛇形件22，两臂28蛇形件22，三臂34蛇形件22和五臂36蛇形件的结构球栅阵列而得到的结果。
  每排焊球数                              1             4              8              16             24             100
  固态硅内插件 1.08％ 1.48％ 1.61％ 1.01％
  固态Al2O3内插件 0.667％ 0.953％ 1.077％ 0.72％
  固态BT内插件 0.126％ 0.149％ 0.150％ 0.097％
  单臂蛇形件 0.103％ 0.0903％ 0.085％
  二臂蛇形件 0.47％ 0.15％ 0.147％ 0.136％ 0.128％ 0.088％
  三臂蛇形件 0.22％ 0.082％ 0.079％ 0.058％ 0.056％
  五臂蛇形件 0.025％ 0.025％ 0.013％
如上所示，焊料弹性应变极限大约为0.08％。从容纳区12的边缘到集成电路载体10的边缘被定义为一个焊球排。
以上结果显示，由于PCB 24和载体10之间的机械-热应变累积效应，固体载体的焊球应变数值随焊球数目增加而增加，在接近20处达到某一个峰值。焊球应变实际上由于焊接了大量焊球而下降，这可能是由于固态硅载体发生变形而造成的。虽然集成电路载体和PCB之间的不同膨胀效果已经得到最大限度的降低，但是在最外侧的焊球仍然出现最大应变。而且，除了BT载体，固态载体的最大应变值仍然远远超过焊料的弹性应变极限。
采用不同的蛇形件22表明随着焊球数目的增加最大焊球应变降低。这是由于热应变不匹配分布到了大量焊球20，从而导致较轻程度的形变。球栅阵列越小，即每行的焊球越少，就会显示出越严重的形变，从而在焊球20的最内侧和最外侧都会造成一个集中负荷现象。
因此，本发明的一个优点在于，由于应变的峰值随焊球20数目的增加而减少，所以对于集成电路引脚的数目不存在热机械性的限制。在容纳区12各边设置每行100个焊球的结构相当于一个大于40,000个焊球的球栅阵列，远远超过到2014年9,000个焊球的要求。对于具有三个或更多臂的蛇形件，设置以8行或者更多排焊球的载体，有限元计算表明最大焊球应变低于焊料的弹性应变极限。当容纳区材料为硅时，即与硅集成电路具有相同的热膨胀系数，则最大限度地降低了从集成电路14至集成电路载体10的焊接凸点上的应变。这一点表明本文所述的带有蚀刻纵折区域的硅BGA，对于当前采用球栅阵列作为芯片和PCB之间的引脚时，由于热循环对其所制作的引脚数目的限制问题，可以提供一个确切的解决方案。同样，如上所述，通过设置蛇形件22，可以提供更大的表面积并且该表面积通过重入式蚀刻50进一步增加从而增强了集成电路载体10的散热能力。这一点也增加了构成阵列的焊球20的数目。
本领域的技术人员应该明确：在不违背本发明所广泛说明的精神和范围的情况下，可以对本发明进行各种变化和/或改进。因此，应当将本发明的实施例作为说明而不是限制。

Claims (11)

1.一种制作集成电路载体的方法，该方法包括步骤如下：
提供一个基板；
划分出至少一个容纳区，用以容纳基板上的集成电路，并且在上述至少一个容纳区周围设置多个岛屿界定部分；以及
通过从基板去除材料在相邻的岛屿界定部分之间设置刚性降低装置。
2.如权利要求1所述的方法，其特征在于，该方法包括在上述至少一个容纳区制作多个电触点，以及每个岛屿界定部分制作一个电端子，每个电端子通过电路层的走线轨迹电连接到一个电触点。
3.如权利要求2所述的方法，其特征在于，该方法包括通过在基板上沉积金属层从而在基板表面形成电路层。
4.如权利要求1所述的方法，其特征在于，该方法包括通过对基板表面应用掩膜技术而划分出至少一个容纳区和岛屿界定部分。
5.如权利要求1所述的方法，其特征在于，该方法包括通过蚀刻贯通基板，在曝露出基板之后进行光罩处理去除基板材料，而产生刚性降低装置。
6.如权利要求1所述的方法，其特征在于，该方法包括通过蚀刻贯通基板的方法制作辅助刚性降低装置。
7.如权利要求1所述的方法，其特征在于，该方法包括采用具有绝缘层的末掺杂硅晶片而制作基板。
8.如权利要求1所述的方法，其特征在于，该方法包括通过在基板内制作凹槽来划分至少一个容纳区。
9.如权利要求8所述的方法，其特征在于，该凹槽可以通过对基板蚀刻的方法制作。
10.如权利要求2所述的方法，其特征在于，该方法通过在基板上制作通孔的方法划分至少一个容纳区，在基板上环绕通孔周围的区域设置多个电触点。
11.如权利要求10所述的方法，其特征在于，该通孔可以通过蚀刻基板的方法进行制作。
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