CN1467819A - 在硅基板中插塞通孔的方法 - Google Patents
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Abstract
本发明公开了一种在硅基板中插塞通孔的方法。借助电解电镀用金属11插塞硅基板1中的通孔2。抛光和平坦化硅基板的两面之后，在硅基板上进行高压退火以除去在插塞金属中产生的小空隙，因此，增强了插塞金属的精度和密度。
Description
技术领域
本发明涉及在通孔中填充或插塞(plugging)金属的方法，所述通孔形成在用于硅半导体器件、插入物(interposer)等的单晶硅基板中。
当在硅基板上三维地安装部件时，最困难的事情是将形成在上表面上的电路布线与形成在硅基板下表面上的电路布线电连接。
背景技术
通常，如下实现硅基板的上和下表面之间的电连接。在硅基板中形成通孔之后，穿透上和下表面将金属插塞到通孔内，硅基板的上和下表面上的电路图形通过通孔中插塞的金属导体相互连接。
例如，日本待审专利公开No.1-258457公开了一种半导体集成电路的制造方法，其中在单晶硅制成的硅安装基板中形成通孔并且借助热氧化用绝缘膜涂覆单晶硅基板，以及用金属插塞通孔。在专利公开的官方公报中，公开了将用于镀覆的电极固定到硅安装基板的主表面，通过镀覆用金属插塞通孔的技术。
根据硅基板中插塞通孔的以上常规方法，存在通过镀覆在插塞到通孔内的金属中产生小空隙的问题。因此，不可能精确并致密地用金属插塞通孔。为了防止产生以上的小空隙，现已研究了一种方法，其中通过镀覆用金属插塞通孔之后，硅基板的背面接地以露出插塞的金属。然而，即使采用以上的对策，也不可能防止在插塞金属中产生小空隙。因此，现已发现不可能得到由相当精确和致密的金属组成的栓塞。因此，在现有技术的方法中，半导体晶片上的通路布线的可靠性很低，并且成品率降低。
发明内容
因此，本发明的一个目的是提供一种用金属在硅基板中插塞通孔的方法，其中在硅基板上形成通孔之后通过镀覆用金属插塞这些通孔，该方法的特征在于防止在插塞的金属中产生小空隙以便可以用精确和致密的金属插塞通孔。
根据本发明，提供一种在硅基板中插塞通孔的方法，包括以下步骤：提供具有第一和第二表面的硅基板，通孔从第一表面穿透到第二表面；用绝缘膜形成包括通孔内壁表面的硅基板的第一和第二表面；通过粘合剂将导体面粘结到硅基板的第二表面；从硅基板的第一表面处借助通孔蚀刻粘结剂将粘结剂钻孔，以便在通孔的内部露出导体面；使用导体面作为来自硅基板第一表面的电极，通过镀覆金属用金属填充通孔；剥离掉导体面并平坦化包括填充金属的硅基板的第一和第二表面；以及对硅基板进行高压退火。
有利的是形成在包括通孔内壁表面的硅基板的第一和第二表面上的绝缘膜是通过化学汽相淀积(CVD)或热处理形成的氧化膜(SiO2膜)。
有利之处还在于通过等离子体蚀刻进行粘结剂膜的蚀刻步骤。通过化学机械抛光(CMP)进行硅基板的第一和第二表面的平坦化步骤。
在150MPa的压力下在350℃的温度下在氩气氛中进行对硅基板的高压退火步骤。此外，粘结剂优选是粘结剂膜。金属面优选是铜箔。
附图简介
图1示出了形成在单晶的硅基板上的通孔；
图2示出了在包括通孔内壁表面的硅基板的正面和背面上整个形成绝缘膜的步骤；
图3示出了通过粘结剂膜将金属箔或金属板粘附到硅基板背面的步骤；
图4示出了在粘结剂膜上进行钻孔的状态；
图5示出了通过电解电镀将金属插塞到通孔内的步骤；
图6示出了硅基板的各面平坦化的步骤；以及
图7示出了在硅基板上进行高压退火的步骤。
优选实施例的详细说明
参考附图，下面详细介绍本发明的一个实施例。
图1示出了在单晶硅基板1中形成通孔2的步骤。此时，硅基板1可以是用做如半导体元件的电子器件的晶片的硅基板，或者是用做用于插入物的晶片的硅基板。硅基板1可以是厚度为几百μm的厚硅基板或是厚度为几十μm的薄硅基板。可以借助如机械钻孔或激光束加工的公知方法或是通过如蚀刻的化学方法形成通孔2。
图2示出了在包括通孔2内壁表面的硅基板1的正面和背面(第一和第二表面)的整个表面上形成绝缘膜3的步骤。该绝缘膜3可以形成为通过化学汽相淀积(CVD)形成的热氧化膜(SiO2膜)或是在气氛中通过热处理氧化硅基板的表面时形成的热氧化膜(SiO2膜)。
图3示出了通过粘结树脂膜4将金属箔片或金属片5粘附到硅基板1背面的步骤。金属箔片5由如铜箔的金属材料制成，当在以后步骤中进行电解电镀时用做阴极。硅基板1、粘结剂膜4以及金属箔5通过夹具6相互固定。
图4示出了当硅基板1、粘结剂膜4以及金属箔5通过夹具6相互固定时，从硅基板1的上表面对通孔2进行蚀刻以便在对应于通孔2的部分对粘结剂膜4进行钻孔的状态。此时，优选通过将等离子体照射到通孔2内的等离子体蚀刻进行蚀刻。当以此方式在粘结剂膜4上形成孔10时，对应于通孔2的一部分金属箔片5暴露到通孔2内。因此，当在下一步骤中进行电解电镀时，该金属箔片5可以用做阴极。
图5示出了夹具6浸泡在镀液中并且进行电解电镀，同时金属箔片5用做以上提到的阴极，金属11沉积在通孔中由此由该金属插塞这些通孔的步骤。此时，优选镀覆金属11为铜，铜的导电性较高。如上所述，当金属箔片或金属片5粘附到硅基板1背面以使金属箔片或金属片5用做阴极时并且当阴极在对应于硅基板1上的通孔2的部分中露出时，可以仅在对应于通孔2的部分中沉积金属11。
图6示出了已被粘附到硅基板1背面的金属箔片5被剥离并且平坦化包括插塞在通孔2中金属11的硅基板的两个表面的步骤。由于以上，硅基板变成具有条形的形状9。在平坦化硅基板1的两个表面的步骤中，优选采用化学机械抛光(CMP)。
图7示出了在硅基板1上进行高压退火的步骤。在硅基板1上进行高压退火的步骤中，在高压氩气氛中进行热处理。在退火的工艺中，加热温度适当设置为约350℃，并且压力适当设置为约150Mpa。加热温度必须是充分低于铜和铝熔点的值，当然硅基板1上的栓塞金属(例如，铜)和铝布线(未示出)不能熔化。处理时间必须是栓塞铜可以制得精确和致密的时间周期。
如上所述，根据本发明，通过电解电镀通孔2已插塞有金属(铜)之后，进行高压退火。由于以上，可以解决在栓塞金属中形成小空隙的问题。因此，栓塞可以由精确和致密的金属组成。例如，在退火之前图6所示的状态中，由小空隙造成的小缝隙20存在于镀覆金属1和通孔2的内壁上氧化的绝缘膜3之间，然而，完成高压退火之后，如图7所示该缝隙被金属22填充。由于以上，通路孔布线的可靠性增强，并且可以有效地防止成品率的降低。
当进行高压退火时，通过高压气体的作用和高温作用的共同合作可以由已填充在通孔中的栓塞金属除去留在栓塞中的小空隙。因此，可以认为金属可以致密并且紧固地填充在通孔中。
参考附图，已介绍了本发明的实施例。然而，应该注意本发明不限于以上提到的具体实施例。本领域中的技术人员可以不脱离本发明的精神和范围做出变化、修改和修正。
如上所述，根据本发明，借助电解电镀用金属(铜)插塞通孔之后，进行高压退火。由于以上，可以解决在栓塞金属中形成的小空隙的问题。因此，栓塞可以由精确和致密的金属组成。
由于以上，可以增强通路孔布线的可靠性，可以有效地防止成品率的降低。因此，在用做芯片级三维安装的硅基板上，可以通过镀覆铜插塞通孔。当实现芯片级三维安装时，可以制造高性能的半导体芯片。此外，可以高速进行操作，并且可以进行紧密的安装。
Claims (7)
1.一种在硅基板中插塞通孔的方法，包括以下步骤：
提供具有第一和第二表面的硅基板，通孔从第一表面穿透到第二表面；
在包括通孔内壁表面的硅基板的第一和第二表面上形成绝缘膜；
通过粘合剂将导体面粘结到硅基板的第二表面；
从硅基板的第一表面处借助通孔蚀刻粘结剂将粘结剂钻孔，以便在通孔的内部露出导体面；
使用导体面作为来自硅基板第一表面的电极，通过镀覆金属用金属填充通孔；
剥离掉导体面并平坦化包括填充金属的硅基板的第一和第二表面；以及
对硅基板进行高压退火。
2.根据权利要求1中的插塞方法，其中形成在包括通孔内壁表面的硅基板的第一和第二表面上的绝缘膜是通过化学汽相淀积(CVD)或热处理形成的氧化膜。
3.根据权利要求1中的插塞方法，其中通过等离子体蚀刻进行粘结剂膜的蚀刻步骤。
4.根据权利要求1中的插塞方法，其中通过化学机械抛光(CMP)进行硅基板的第一和第二表面的平坦化步骤。
5.根据权利要求1中的插塞方法，其中在150MPa的压力下在350℃的温度下氩气氛中进行对硅基板的高压退火步骤。
6.根据权利要求1中的插塞方法，其中粘结剂是粘结剂膜。
7.根据权利要求1中的插塞方法，其中金属面是铜箔。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002178902A JP3904484B2 (ja) | 2002-06-19 | 2002-06-19 | シリコン基板のスルーホールプラギング方法 |
| JP178902/2002 | 2002-06-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1467819A true CN1467819A (zh) | 2004-01-14 |
| CN1310309C CN1310309C (zh) | 2007-04-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB031376754A Expired - Fee Related CN1310309C (zh) | 2002-06-19 | 2003-06-18 | 在硅基板中插塞通孔的方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6815348B2 (zh) |
| EP (1) | EP1376686B1 (zh) |
| JP (1) | JP3904484B2 (zh) |
| KR (1) | KR100999907B1 (zh) |
| CN (1) | CN1310309C (zh) |
| TW (1) | TWI294160B (zh) |
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| CN110634792A (zh) * | 2019-09-26 | 2019-12-31 | 上海航天电子通讯设备研究所 | 一种电气互连基板制造方法 |
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| JP5367616B2 (ja) | 2009-02-23 | 2013-12-11 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
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| TWI527174B (zh) | 2010-11-19 | 2016-03-21 | 日月光半導體製造股份有限公司 | 具有半導體元件之封裝結構 |
| TWI445155B (zh) | 2011-01-06 | 2014-07-11 | Advanced Semiconductor Eng | 堆疊式封裝結構及其製造方法 |
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| WO2018097265A1 (ja) * | 2016-11-28 | 2018-05-31 | 三井金属鉱業株式会社 | 多層配線板の製造方法 |
| CN109770438B (zh) * | 2019-03-25 | 2023-07-25 | 云南中烟工业有限责任公司 | 一种镀膜硅基电子烟雾化芯片及其制备方法 |
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| US4348253A (en) * | 1981-11-12 | 1982-09-07 | Rca Corporation | Method for fabricating via holes in a semiconductor wafer |
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| JP2773366B2 (ja) * | 1990-03-19 | 1998-07-09 | 富士通株式会社 | 多層配線基板の形成方法 |
| JPH11288973A (ja) | 1998-04-01 | 1999-10-19 | Canon Inc | 半導体の接続構造と半導体の接続方法及び半導体デバイス |
| US6114098A (en) * | 1998-09-17 | 2000-09-05 | International Business Machines Corporation | Method of filling an aperture in a substrate |
| JP2000353703A (ja) * | 1999-06-11 | 2000-12-19 | Sony Corp | 半導体装置の製造方法 |
| JP2001060621A (ja) * | 1999-08-20 | 2001-03-06 | Kobe Steel Ltd | 半導体装置の製造方法 |
| US6399486B1 (en) * | 1999-11-22 | 2002-06-04 | Taiwan Semiconductor Manufacturing Company | Method of improved copper gap fill |
-
2002
- 2002-06-19 JP JP2002178902A patent/JP3904484B2/ja not_active Expired - Fee Related
-
2003
- 2003-06-12 EP EP03291402A patent/EP1376686B1/en not_active Expired - Fee Related
- 2003-06-12 US US10/459,609 patent/US6815348B2/en not_active Expired - Lifetime
- 2003-06-18 CN CNB031376754A patent/CN1310309C/zh not_active Expired - Fee Related
- 2003-06-18 TW TW092116567A patent/TWI294160B/zh not_active IP Right Cessation
- 2003-06-18 KR KR1020030039466A patent/KR100999907B1/ko not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100449799C (zh) * | 2004-09-29 | 2009-01-07 | 晶元光电股份有限公司 | 发光二极管的封装基板的形成方法 |
| CN110634792A (zh) * | 2019-09-26 | 2019-12-31 | 上海航天电子通讯设备研究所 | 一种电气互连基板制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20030235982A1 (en) | 2003-12-25 |
| CN1310309C (zh) | 2007-04-11 |
| TWI294160B (en) | 2008-03-01 |
| EP1376686A3 (en) | 2004-04-21 |
| US6815348B2 (en) | 2004-11-09 |
| JP3904484B2 (ja) | 2007-04-11 |
| KR100999907B1 (ko) | 2010-12-13 |
| EP1376686B1 (en) | 2005-08-31 |
| JP2004022990A (ja) | 2004-01-22 |
| TW200402836A (en) | 2004-02-16 |
| EP1376686A2 (en) | 2004-01-02 |
| KR20030097673A (ko) | 2003-12-31 |
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