CN1381847B - 半导体存储器装置 - Google Patents
半导体存储器装置 Download PDFInfo
- Publication number
- CN1381847B CN1381847B CN021035644A CN02103564A CN1381847B CN 1381847 B CN1381847 B CN 1381847B CN 021035644 A CN021035644 A CN 021035644A CN 02103564 A CN02103564 A CN 02103564A CN 1381847 B CN1381847 B CN 1381847B
- Authority
- CN
- China
- Prior art keywords
- data
- circuit
- parity
- input
- reading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 93
- 230000015654 memory Effects 0.000 claims abstract description 23
- 238000003860 storage Methods 0.000 claims description 17
- 230000006870 function Effects 0.000 abstract description 7
- 230000005540 biological transmission Effects 0.000 description 50
- 238000001514 detection method Methods 0.000 description 20
- 238000000034 method Methods 0.000 description 20
- 230000008569 process Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 6
- 238000011084 recovery Methods 0.000 description 6
- 230000002159 abnormal effect Effects 0.000 description 4
- 238000007689 inspection Methods 0.000 description 4
- 241001269238 Data Species 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000000306 recurrent effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Tests Of Electronic Circuits (AREA)
- Memory System (AREA)
Abstract
Description
Claims (9)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP119439/2001 | 2001-04-18 | ||
JP2001119439A JP4782302B2 (ja) | 2001-04-18 | 2001-04-18 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1381847A CN1381847A (zh) | 2002-11-27 |
CN1381847B true CN1381847B (zh) | 2010-05-12 |
Family
ID=18969658
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN021035644A Expired - Fee Related CN1381847B (zh) | 2001-04-18 | 2002-02-07 | 半导体存储器装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6922750B2 (zh) |
EP (1) | EP1251522A3 (zh) |
JP (1) | JP4782302B2 (zh) |
KR (1) | KR100823013B1 (zh) |
CN (1) | CN1381847B (zh) |
TW (1) | TW546657B (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4664208B2 (ja) * | 2003-08-18 | 2011-04-06 | 富士通セミコンダクター株式会社 | 半導体メモリおよび半導体メモリの動作方法 |
KR100511047B1 (ko) | 2003-12-08 | 2005-08-30 | 삼성전자주식회사 | 반도체 메모리 테스트 방법 및 이를 수행하기 위한 장치,테스트용 반도체 메모리 |
JP4569182B2 (ja) * | 2004-03-19 | 2010-10-27 | ソニー株式会社 | 半導体装置 |
US7833575B2 (en) * | 2005-11-08 | 2010-11-16 | Gupta Laxmi C | Methods for applying fire retardant systems, compositions and uses |
KR100852191B1 (ko) * | 2007-02-16 | 2008-08-13 | 삼성전자주식회사 | 에러 정정 기능을 가지는 반도체 메모리 장치 및 에러 정정방법 |
KR101094402B1 (ko) | 2009-12-29 | 2011-12-15 | 주식회사 하이닉스반도체 | 반도체 장치 및 반도체 장치를 포함하는 반도체 시스템 |
CN102420017A (zh) * | 2011-09-28 | 2012-04-18 | 上海宏力半导体制造有限公司 | 检测存储器记忆能力的方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62120699A (ja) * | 1985-11-20 | 1987-06-01 | Fujitsu Ltd | 半導体記憶装置 |
JPH0612613B2 (ja) | 1986-03-18 | 1994-02-16 | 富士通株式会社 | 半導体記憶装置 |
JPH01200455A (ja) * | 1988-02-05 | 1989-08-11 | Sharp Corp | パリティ機能を有する半導体記憶装置に於けるパリティ機能テスト方法 |
JPH0440697A (ja) * | 1990-06-06 | 1992-02-12 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
JPH04132093A (ja) * | 1990-09-21 | 1992-05-06 | Toshiba Corp | 半導体記憶装置 |
JP2968134B2 (ja) | 1991-11-27 | 1999-10-25 | 三菱電機株式会社 | 半導体記憶装置 |
JP2830730B2 (ja) * | 1994-02-28 | 1998-12-02 | 日本電気株式会社 | ダイナミックメモリ |
US6108229A (en) | 1996-05-24 | 2000-08-22 | Shau; Jeng-Jye | High performance embedded semiconductor memory device with multiple dimension first-level bit-lines |
CN1137491C (zh) * | 1998-03-30 | 2004-02-04 | 西门子公司 | 动态随机存取存储器中的译码自动刷新模式 |
JP3938842B2 (ja) * | 2000-12-04 | 2007-06-27 | 富士通株式会社 | 半導体記憶装置 |
JP4001724B2 (ja) * | 2001-03-29 | 2007-10-31 | 富士通株式会社 | 半導体記憶装置 |
-
2001
- 2001-04-18 JP JP2001119439A patent/JP4782302B2/ja not_active Expired - Fee Related
-
2002
- 2002-01-17 US US10/046,754 patent/US6922750B2/en not_active Expired - Fee Related
- 2002-01-17 TW TW091100657A patent/TW546657B/zh not_active IP Right Cessation
- 2002-01-23 EP EP02250447A patent/EP1251522A3/en not_active Withdrawn
- 2002-02-07 CN CN021035644A patent/CN1381847B/zh not_active Expired - Fee Related
- 2002-02-07 KR KR1020020007134A patent/KR100823013B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JP4782302B2 (ja) | 2011-09-28 |
KR100823013B1 (ko) | 2008-04-17 |
EP1251522A2 (en) | 2002-10-23 |
KR20030010465A (ko) | 2003-02-05 |
US20020156967A1 (en) | 2002-10-24 |
US6922750B2 (en) | 2005-07-26 |
TW546657B (en) | 2003-08-11 |
JP2002313077A (ja) | 2002-10-25 |
EP1251522A3 (en) | 2004-03-17 |
CN1381847A (zh) | 2002-11-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6756856B2 (en) | Clock generation circuits and integrated circuit memory devices for controlling a clock period based on temperature and methods for using the same | |
CN101432818B (zh) | 具有完全独立的部分阵列刷新功能的动态随机存取存储器 | |
CN101013602B (zh) | 半导体存储装置 | |
JP3924539B2 (ja) | データストアをテストするテスト方法 | |
GB2248706A (en) | A semiconductor memory device comprising a test circuit and a method of operation thereof | |
CN100421175C (zh) | 用于对缺陷单元地址编程的缺陷单元地址编程电路和方法 | |
JPH05298895A (ja) | 誤り訂正回路を備えた不揮発性メモリ装置 | |
CN1381847B (zh) | 半导体存储器装置 | |
JPH05249196A (ja) | 半導体記憶装置 | |
KR20190086936A (ko) | 메모리 장치 | |
US7464309B2 (en) | Method and apparatus for testing semiconductor memory device and related testing methods | |
WO1981001208A1 (en) | Data processor having common monitoring and memory loading and checking means | |
KR950006215B1 (ko) | 반도체 기억장치를 위한 테스트장치 | |
JP4724722B2 (ja) | 集積回路半導体ランダムアクセス・メモリ装置 | |
US7461306B2 (en) | Output data compression scheme using tri-state | |
CN101174404B (zh) | 用于显示控制器的半导体集成电路装置 | |
JP2006275810A (ja) | 半導体装置の試験方法及び半導体装置 | |
CN1637939B (zh) | 半导体存储装置 | |
US6611929B1 (en) | Test circuit for memory | |
JPS6366798A (ja) | 半導体記憶装置 | |
JP3655658B2 (ja) | 数値制御装置 | |
KR970005648B1 (ko) | 에러정정수단을 갖는 반도체메모리 | |
JP3088140B2 (ja) | 半導体記憶装置 | |
KR100262129B1 (ko) | 칩상에 기하학적 연결 논리 구동기를 갖는 메모리 집적회로 및동 메모리 집적회로를 검사하고제조하는 방법 | |
JPH02122500A (ja) | 半導体メモリ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20081212 Address after: Tokyo, Japan Applicant after: Fujitsu Microelectronics Ltd. Address before: Kanagawa, Japan Applicant before: Fujitsu Ltd. |
|
ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081212 |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C56 | Change in the name or address of the patentee |
Owner name: FUJITSU SEMICONDUCTOR CO., LTD. Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD. |
|
CP03 | Change of name, title or address |
Address after: Kanagawa Patentee after: Fujitsu Semiconductor Co., Ltd. Address before: Tokyo, Japan Patentee before: Fujitsu Microelectronics Ltd. |
|
ASS | Succession or assignment of patent right |
Owner name: SUOSI FUTURE CO., LTD. Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20150525 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20150525 Address after: Kanagawa Patentee after: Co., Ltd. Suo Si future Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100512 Termination date: 20160207 |
|
CF01 | Termination of patent right due to non-payment of annual fee |