CN1315176C - 形成沟槽隔离结构的方法 - Google Patents
形成沟槽隔离结构的方法 Download PDFInfo
- Publication number
- CN1315176C CN1315176C CNB2004800057038A CN200480005703A CN1315176C CN 1315176 C CN1315176 C CN 1315176C CN B2004800057038 A CNB2004800057038 A CN B2004800057038A CN 200480005703 A CN200480005703 A CN 200480005703A CN 1315176 C CN1315176 C CN 1315176C
- Authority
- CN
- China
- Prior art keywords
- temperature
- prebake
- polysilazane
- coating
- silicon dioxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
从宽度1μm沟槽顶端的相对高度 | 空隙 | ||||
沟槽宽度 | 0.5μm | 0.2μm | 0.1μm | 0.05μm | 0.05μm |
实施例1 | 0.00μm | -0.03μm | -0.05μm | -0.08μm | 无 |
实施例2 | 0.00μm | 0.00μm | -0.02μm | -0.04μm | 无 |
实施例3 | -0.01μm | -0.02μm | -0.02μm | -0.04μm | 无 |
实施例4 | -0.01μm | -0.01μm | -0.01μm | -0.02μm | 无 |
实施例5 | -0.01μm | -0.01μm | -0.03μm | -0.04μm | 无 |
实施例6 | 0.00μm | -0.01μm | -0.01μm | -0.01μm | 无 |
实施例7 | -0.01μm | -0.01μm | -0.03μm | -0.05μm | 无 |
对比例1 | -0.03μm | -0.09μm | -0.24μm | -0.41μm | 在下端有 |
对比例2 | -0.05μm | -0.08μm | -0.18μm | -0.22μm | 无 |
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP058365/2003 | 2003-03-05 | ||
JP2003058365A JP2004273519A (ja) | 2003-03-05 | 2003-03-05 | トレンチ・アイソレーション構造の形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1757105A CN1757105A (zh) | 2006-04-05 |
CN1315176C true CN1315176C (zh) | 2007-05-09 |
Family
ID=32958792
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004800057038A Expired - Fee Related CN1315176C (zh) | 2003-03-05 | 2004-03-03 | 形成沟槽隔离结构的方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US20060160321A1 (zh) |
EP (1) | EP1608012A1 (zh) |
JP (1) | JP2004273519A (zh) |
KR (1) | KR20060002786A (zh) |
CN (1) | CN1315176C (zh) |
TW (1) | TW200503101A (zh) |
WO (1) | WO2004079819A1 (zh) |
Families Citing this family (22)
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JP4342895B2 (ja) | 2003-10-06 | 2009-10-14 | 東京エレクトロン株式会社 | 熱処理方法及び熱処理装置 |
JP4594648B2 (ja) * | 2004-05-26 | 2010-12-08 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP2005347636A (ja) * | 2004-06-04 | 2005-12-15 | Az Electronic Materials Kk | トレンチ・アイソレーション構造の形成方法 |
JP5091428B2 (ja) * | 2005-06-14 | 2012-12-05 | 株式会社東芝 | 半導体装置の製造方法 |
US7892942B2 (en) * | 2007-07-09 | 2011-02-22 | Micron Technology Inc. | Methods of forming semiconductor constructions, and methods of forming isolation regions |
JP5329825B2 (ja) | 2008-02-25 | 2013-10-30 | 株式会社東芝 | 半導体装置の製造方法 |
JP5306669B2 (ja) * | 2008-02-29 | 2013-10-02 | AzエレクトロニックマテリアルズIp株式会社 | シリカ質膜の形成方法およびそれにより形成されたシリカ質膜 |
JP5405031B2 (ja) * | 2008-03-06 | 2014-02-05 | AzエレクトロニックマテリアルズIp株式会社 | シリカ質膜の製造に用いる浸漬用溶液およびそれを用いたシリカ質膜の製造法 |
US7999355B2 (en) | 2008-07-11 | 2011-08-16 | Air Products And Chemicals, Inc. | Aminosilanes for shallow trench isolation films |
JP5535583B2 (ja) * | 2009-05-25 | 2014-07-02 | AzエレクトロニックマテリアルズIp株式会社 | トレンチ・アイソレーション構造の形成方法 |
JP5490753B2 (ja) * | 2010-07-29 | 2014-05-14 | 東京エレクトロン株式会社 | トレンチの埋め込み方法および成膜システム |
US9082612B2 (en) * | 2010-12-22 | 2015-07-14 | Cheil Industries, Inc. | Composition for forming a silica layer, method of manufacturing the composition, silica layer prepared using the composition, and method of manufacturing the silica layer |
JP5675331B2 (ja) * | 2010-12-27 | 2015-02-25 | 東京エレクトロン株式会社 | トレンチの埋め込み方法 |
JP5634366B2 (ja) * | 2011-09-26 | 2014-12-03 | 株式会社東芝 | 成膜装置及び半導体装置の製造方法 |
CN103257523B (zh) * | 2012-02-17 | 2016-01-06 | 中国科学院微电子研究所 | 曝光电子束正性抗蚀剂的方法 |
US8796105B2 (en) * | 2012-07-25 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for preparing polysilazane on a semiconductor wafer |
KR101361454B1 (ko) * | 2012-08-23 | 2014-02-21 | 이근수 | 반도체 소자의 실리콘 산화막 형성 방법 |
CN103871951B (zh) * | 2012-12-18 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | 沟槽填充方法 |
CN103910885A (zh) | 2012-12-31 | 2014-07-09 | 第一毛织株式会社 | 制备间隙填充剂的方法、用其制备的间隙填充剂和使用间隙填充剂制造半导体电容器的方法 |
US11450526B2 (en) * | 2018-05-30 | 2022-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cyclic spin-on coating process for forming dielectric material |
CN110890314A (zh) * | 2018-09-11 | 2020-03-17 | 长鑫存储技术有限公司 | 一种半导体器件的绝缘层的制备方法 |
CN110517984A (zh) * | 2019-08-29 | 2019-11-29 | 上海华力微电子有限公司 | 浅沟槽隔离结构的制备方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020068413A1 (en) * | 2000-12-01 | 2002-06-06 | Akito Konishi | Process of manufacturing semiconductor device |
EP1278238A1 (en) * | 2000-04-25 | 2003-01-22 | Tonen General Sekiyu K.K. | Method for sealing fine groove with siliceous material and substrate having siliceous coating formed thereon |
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JPS60145903A (ja) * | 1983-12-29 | 1985-08-01 | Toa Nenryo Kogyo Kk | 無機ポリシラザン及びその合成方法 |
JPH07120700B2 (ja) * | 1985-09-18 | 1995-12-20 | ソニー株式会社 | 半導体装置の製造方法 |
JP2918573B2 (ja) * | 1989-09-13 | 1999-07-12 | 三菱電機株式会社 | 半導体装置の製造方法 |
JPH0497542A (ja) * | 1990-08-15 | 1992-03-30 | Nec Corp | 半導体装置の製造方法 |
US5821160A (en) * | 1996-06-06 | 1998-10-13 | Motorola, Inc. | Method for forming a laser alterable fuse area of a memory cell using an etch stop layer |
JP3638778B2 (ja) * | 1997-03-31 | 2005-04-13 | 株式会社ルネサステクノロジ | 半導体集積回路装置およびその製造方法 |
JP3178412B2 (ja) * | 1998-04-27 | 2001-06-18 | 日本電気株式会社 | トレンチ・アイソレーション構造の形成方法 |
JP2000114362A (ja) * | 1998-10-02 | 2000-04-21 | Nec Corp | 半導体装置の製造方法 |
US6319796B1 (en) * | 1999-08-18 | 2001-11-20 | Vlsi Technology, Inc. | Manufacture of an integrated circuit isolation structure |
JP3344397B2 (ja) * | 2000-01-21 | 2002-11-11 | 日本電気株式会社 | 半導体装置の製造方法 |
KR100362834B1 (ko) * | 2000-05-02 | 2002-11-29 | 삼성전자 주식회사 | 반도체 장치의 산화막 형성 방법 및 이에 의하여 제조된 반도체 장치 |
KR100354442B1 (ko) * | 2000-12-11 | 2002-09-28 | 삼성전자 주식회사 | 반도체 장치의 스핀 온 글래스 절연막 형성 방법 |
KR100568100B1 (ko) * | 2001-03-05 | 2006-04-05 | 삼성전자주식회사 | 트렌치형 소자 분리막 형성 방법 |
KR100512167B1 (ko) * | 2001-03-12 | 2005-09-02 | 삼성전자주식회사 | 트렌치 소자 분리형 반도체 장치 및 트렌치형 소자 분리막형성방법 |
US6699799B2 (en) * | 2001-05-09 | 2004-03-02 | Samsung Electronics Co., Ltd. | Method of forming a semiconductor device |
KR20030003906A (ko) * | 2001-07-04 | 2003-01-14 | 삼성전자 주식회사 | 반도체 소자의 콘택 형성방법 및 그에 따라 제조된 반도체메모리 소자 |
JP2003031650A (ja) * | 2001-07-13 | 2003-01-31 | Toshiba Corp | 半導体装置の製造方法 |
US6869860B2 (en) * | 2003-06-03 | 2005-03-22 | International Business Machines Corporation | Filling high aspect ratio isolation structures with polysilazane based material |
-
2003
- 2003-03-05 JP JP2003058365A patent/JP2004273519A/ja not_active Withdrawn
-
2004
- 2004-03-03 CN CNB2004800057038A patent/CN1315176C/zh not_active Expired - Fee Related
- 2004-03-03 US US10/548,222 patent/US20060160321A1/en not_active Abandoned
- 2004-03-03 KR KR1020057016283A patent/KR20060002786A/ko not_active Application Discontinuation
- 2004-03-03 WO PCT/JP2004/002638 patent/WO2004079819A1/ja not_active Application Discontinuation
- 2004-03-03 EP EP04716765A patent/EP1608012A1/en not_active Withdrawn
- 2004-03-04 TW TW093105645A patent/TW200503101A/zh unknown
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1278238A1 (en) * | 2000-04-25 | 2003-01-22 | Tonen General Sekiyu K.K. | Method for sealing fine groove with siliceous material and substrate having siliceous coating formed thereon |
US20020068413A1 (en) * | 2000-12-01 | 2002-06-06 | Akito Konishi | Process of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
CN1757105A (zh) | 2006-04-05 |
JP2004273519A (ja) | 2004-09-30 |
US20060160321A1 (en) | 2006-07-20 |
WO2004079819A1 (ja) | 2004-09-16 |
KR20060002786A (ko) | 2006-01-09 |
TW200503101A (en) | 2005-01-16 |
EP1608012A1 (en) | 2005-12-21 |
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Address after: Tokyo, Japan Patentee after: AZ electronic material IP (Japan) Co.,Ltd. Address before: Tokyo, Japan Patentee before: AZ ELECTRONIC MATERIALS (JAPAN) Kabushiki Kaisha |
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