CN1309418A - 在基片上成膜的方法和装置 - Google Patents

在基片上成膜的方法和装置 Download PDF

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CN1309418A
CN1309418A CN01101669A CN01101669A CN1309418A CN 1309418 A CN1309418 A CN 1309418A CN 01101669 A CN01101669 A CN 01101669A CN 01101669 A CN01101669 A CN 01101669A CN 1309418 A CN1309418 A CN 1309418A
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layer
etching
etch stop
etch
stop layer
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CN1185693C (zh
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约汉·迈克内尔
罗伯特·约汉·维尔比
努特·比克曼
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Aviza Europe Ltd
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Aviza Europe Ltd
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Abstract

本发明涉及一种在两层介质层中间含有一层居中的蚀刻阻挡层的半导体器件,其中每层的介质常数k≤3.5而且蚀刻阻挡层相对于上层的选择性至少是2.5∶1。还描述了可形成如作为蚀刻阻挡层用的掺氮碳化硅膜的方法和器件。

Description

在基片上成膜的方法和装置
本发明涉及在基片上形成膜的方法和装置，尤其但不唯一地涉及低k蚀刻阻挡膜的形成以及内含这类膜的器件。为了说明起见，这里的低k专指等于或小于3.5的介电常数。
镶嵌和双镶嵌工艺正日益在半导体晶片制造中流行，尤其是在把铜作为内连金属的工艺中。这是因为铜的等离子蚀刻相对比较困难，所以优选为在介质层上蚀刻出构形，然后再把铜沉积在已蚀刻出的构形上并把它填充。任何多余的铜能通过诸如化学机械抛光的方法从表面移走以便把镶嵌的铜留在已蚀刻的器件中。
在作双镶嵌工艺时要把两个分立且互连的特性蚀刻在各自介质层中，一层排在另一层之上。于是在上层蚀刻出一条沟槽而在下层可形成通孔以便把沟槽和位于下层的许多触点相连接。这种结构的许多例子已由Peter Singer发表在1999.8的Semiconductor International的名称为Damascene Challenges,Dielectric Etch的论文所讨论。
通常形成双镶嵌特性的途径是在两介质层之间沉积一层蚀刻阻挡层，当自动蚀刻设备穿透第一层时该蚀刻阻挡层便会给它发出一个有效的“终点”信号。这种闭环控制是较佳的，因为它与开环定时蚀刻控制相比，可以对受蚀刻的特性作出更精确的控制。
所以，蚀刻阻挡层势必需要对蚀刻过程相对于上层有较高选择性以便蚀刻得非常慢，留下时间使控制过程发生。
最近，人们通常希望整个介质结构要有一个低的k值，从而导致人们希望蚀刻阻挡层也有一个低的k值。
另外，一种硅烷基的等离子成形氮化硅已经用作与二氧化硅型层相联系的蚀刻阻挡层，但是这种氮化硅比起标准二氧化硅的4.1的k值来和人们认可的小于3.5的低k值要求来它的k值常常达到7.5。碳化硅也曾建议作为一个可供选择的蚀刻阻挡材料但其k值是9-10，而且会使介质堆叠层的k值明显升高。氮化硅层也发现有问题，即它们会产生一种良好的防水层而许多低k处理还取决于在处理时迫使介质层脱水的能力。
进一步说，现在的氮化硅技术还未必能与用来形成低k层的化学机理相容。
这些问题已在WO-A-99/41423中讨论过，但这份专利申请的结论是一种好的与此相适应的蚀刻阻挡层应具有明显的氧化物含量。许多推荐方法也已提出但是它们看来似乎需要许多其k值明显地各不相同的堆叠层。
从一个方面看本发明的特征在于它是一种在介质堆叠层上形成双镶嵌结构的半导体器件，这个堆叠层包括内含第一蚀刻构形的上层，居中的蚀刻阻挡层和内含第二蚀刻构形的下层，第一、二构形是相连的，每层有一个小于等于3.5的介电常数，k更好的是在3.0以下，相对于上层来说，蚀刻阻挡层至少有2.5∶1的选择性。
较佳地该蚀刻阻挡层是和下层相集成的，尤其较佳地该蚀刻阻挡层是由掺氮的碳化硅形成的。
在一个特别优选的方案中蚀刻阻挡层的k值大体上是可以使之与堆叠层中其他各层的k值相等的。意想不到的是还发现掺氮碳化硅的k值竟可随着掺氮发生时氮的含量来调整的。所以，这一蚀刻阻挡层的k值至少在某种程度上是可以随着其他介质层的k值而予以匹配的。
如上所述，蚀刻阻挡层是可以和下层集成的，这是因为掺氮碳化硅的k值是足够低的以至于它自身可被视为是一种低k值的介质材料。
从第二方面看本发明的特征在于它含有一种用掺氮碳化硅形成的低k值介质层。
再进一步看，本发明的特征还在于：它含有一种在基片上形成一层低k值膜的方法，包括以下步骤：
(a)把基片放置在反应室内的支撑物上；
(b)往室里加入气态或汽化物形式的含硅有机化合物和氮以等离子形式存在以在基片上沉积一层掺氮的碳化硅膜。
含有硅的有机物可以是烷基硅烷，其中尤其是四烷基甲硅烷。特别优选为含硅有机物是四甲基硅烷。
这种膜可以在等于或低于室温下沉淀在已定位的一片基片上，在沉积这种膜时可提供RF能源。
虽然本发明已定义如上，但可以理解的是它还包含了以上已提出或在下面所描述的涉及本发明特征的任何其他发明组合。
本发明可用各种方法实现，将通过带有下述附图的具体实施例予以描述：
图1是一个使用本发明的装置的剖视图；
图2～图4是用于说明按照本发明形成且配置在介质堆叠层内时蚀刻阻挡层的可检测性的附图；
图5(a)～(e)是说明布线沟道及其连接通道的形成的剖视图。
参阅图1，如图所示总体用1表示装置，它含有一个带簇射头3和晶片支撑物或台板4的真空室2。簇射头3与一个射频源(未示)RF相连构成一个电极而支撑物4接地形成另一个电极。或者，射频源RF也可与支撑物4相连而簇射头3接地。簇射头3经管状物(未示)与相应的四甲基硅烷和一种或多种气体的气源相连。这种装置一般结构已包含在参考文献EP-A-0731982，在此作为参考。但是，一个标准(非二重)的簇射头则是常用的。
在使用时，实际上该装置设置成根据所供应的其他气体的性质去沉积许多层。如果其他气体是氧或含氧气体，则可以形成一层低k值的掺碳的二氧化硅层。反之如其他气体是氮气，则根据氮气流速的不同，从纯碳化硅层(实际上不存在氮)到掺碳的氮化硅层(高速氮气流)的任何膜都能形成。申请人发现：对氮气流速进行适当的调整就可形成其k值近似于或等于上述掺碳二氧化硅层的掺氮碳化硅膜。这样就能在单一的室内形成一个同时含有掺碳二氧化硅层，掺氮碳化硅层和掺碳二氧化硅层的介质堆叠层。这个堆叠层不仅从低k的角度来看是所特别希望的而且也是一种既简单又生产率高的形成方法。
因而，根据实验，开发出一种特别有效的介质阻挡层，它是通过引入一种可视为掺甲基的碳化硅/氮化物来形成的，其k值接近2.6。实验发现，如果碳对氮的比率下降至更多形成的是掺碳的氮化硅，则k值就会升高至4.6左右。在两种材料之间是没有严格的转换点的。把更多的氮加到工作气体中去便会提高氮对碳的比值以至于一个极限材料(无氮)可以认为是碳化硅，还有另外一种极限情况是含碳氮化硅。所有的膜都含氢。
在这实验中其工艺条件如下：压力        TMS流      氧气流    氮气流    RF功率     温度低k值掺碳的二氧化硅               k=2.6    SiO2(C)掺甲基二氧化硅3000mT    ～80sccm     100sccm    500sccm  100W       0～25℃低k值掺氮的碳化硅                 k=2.6    SiC(N)掺甲基碳化硅/氮化物1500mT    ～80sccm     无         50sccm   200w        0～25℃低k值掺碳氮化硅                   k=4.6    SiN(C)掺甲基氮化硅500mT     ～20sccm     无         500sccm  1000W       0～25℃
由此可见，在特别选定的氮气流下，低k值掺氮碳化硅其k值精确地等于如上所述形成的低k值的掺碳二氧化硅。
射频功率经380kHz的信号发生器加到簇射头电极上，台板则维持在等于或低于室温状况。零下的温度对工艺是有用的，但在一般情况下，这种工艺是在室温或室温和0℃之间运行的。
进一步的实验是在13.56mHz RF功率时进行的。实验发现SiO2(C)和SiC(N)两者的结果是显著不同的。在SiO2(C)的情况下，沉淀速度提高了而且厚度均匀性也得到了改进，而对SiC(N)材料而言，速度下降而且均匀性变坏。由此可进一步设定：本发明所述的低k值蚀刻阻挡层可以由在高频下(在4mHz以上)沉积的SiO2(C)和在低频(4mHz以下)下沉积的SiC(N)形成。
晶片与簇射头和电极的间距将影响成膜的均匀度，应通过实验来使膜的均匀性达到极大。四甲基硅烷(TMS)的流速是估计的，因为根据共同未决的申请号为No.9922691.2的英国专利申请文件中给出的理由它是难以确定的。
实验最初是在没有涂抗蚀剂的硅晶片上进行的，在蚀刻工艺相同时，其蚀刻速度如下：
膜的类型  母体 蚀刻速度
 SiO2(C)  TMS/O2  9,377/min
 SiC(N)  TMS/N2  3,222/min
 SiN(C)  TMS/N2  4,787/min
从这些蚀刻速度可以计算出：蚀刻选择率是2.9∶1(SiO2∶SiC)，它比起k值更高的标准蚀刻阻挡层来还是要好得多。
因而出乎意外的是：掺氮SiC(N)相对于掺碳的氮化硅而言它更适于作低k值的蚀刻阻挡材料。
于是，堆叠式结构基本上采用上述的沉积工艺而构成，但还包含一项氢等离子处理工艺，用已经在作为参考文献的申请号为9922801.7的我们共同未决英国专利申请中公开的方法。这项氢等离子气处理工艺改进了低k值膜的性能即把BOE湿处理蚀刻速度从10,000/min以上降到和热氧化处理同一等级的水平(约550/min)，降低了氢和碳的含量，明显地提高了密度并降低了膜的吸水性从而减少了裂化的可能性。
这种组合的堆叠层含有中间被一层厚度为500的SiC(N)隔开的两层厚度为7000的SiO2(C)层。其中每层二氧化硅层都用氢等离子体处理过。
蚀刻实验是在不同时间下进行的且终点检测器的输出被记录。用终点检测器来监控440nm发射谱线上的光强度。终点检测器的输出已示于图2和图3中。(图3至4的纵轴表示在任选单位下增加的信号强度)。
进一步的实验是对SiC(N)层在SiO2(C)层上进行的，该实验的终点信号输出见图4。
接着，再在已构图的晶片上进一步作实验。使用两种不同的图形，相应地，一个其敞口区是小的(常用的接点/通孔)，另一个其敞口区是大的(可与内连的相比较的)。使用按以上描述的SiO2(C),SiC(N)和SiN(C)。
其结果可概述如下：
膜的类型 蚀刻速度/min 非均匀性+/-％ 选择性对TMS/O2 SiO2
                          内连掩膜
TMS/O2 SiO2(C)TMS/N2 SiC型TMS/N2 SiN型  10,6113,5244,224  8.35.36.6 3.01
                     接点/通孔掩膜
TMS/O2 SiO2(C)TMS/N2 SiC型TMS/N2 SiN型  11,3283,8753,932  4.45.99.0 2.92
由此可见，除了k值更高以外，SiN的蚀刻特性是在低k值SiC材料之下。不论制作布线图案与否，在低k值SiO2(C)对SiC(N)的选择性上没有明显的区别。在没有光致抗蚀刻的情况下选择性是2.9∶1，从这两个实验值3.01∶1和2.92∶1可大致得出3∶1的值。把蚀刻选择性和十分令人满意的均匀度结合在一起可以看出：SiC(N)是一种实用的蚀刻阻挡材料，从图可看出：实用清晰的终点信号产生在440nm线处。
如上所述，SiC(N)材料作为低k值介质自身具备了令人满意的性能，同时有可能形成两层堆叠层而不存在明确分离的“蚀刻阻挡”层。真正的堆叠层是由k值相似但蚀刻特性明显相异的材料层构成，其层间转换可以检测并实现自动化处理。
一个具体的应用实例，受益于使用两种低k值材料而不使用蚀刻阻挡层的，是一种可在双镶嵌应用中形成低k值双层构造。在这里一层是用作形成通孔而另一层是用作形成上面的沟槽。作为一个例子，一种“沟槽优先”方案可用于对上面覆盖的SiO2(C)层作较快的蚀刻，而对形成通孔的那一层作较慢的蚀刻。沟槽图案可用光刻技术在其表面形成并蚀刻沟槽图案。一个终点信号会在蚀刻到下层材料时产生并实施定时过蚀刻。然后再把蚀刻掩膜(如光致抗蚀剂)去掉并对晶片构图下面的通孔。然后再在下面低k值层上蚀刻通孔。
一项可供选择的程序展示在图5中。可以看出：图5(a)～(e)说明了一种布线沟道和通孔组合的成形方法，该方法在利用上述材料良好的低k值特性的同时也利用了其所能达到的不同蚀刻速度。特别有利的是所述方法对于布线沟道底部的通孔而言，它不需要光刻和形成掩膜。当布线越来越窄的时候，沟道底部的掩蔽就会越益困难。
在图5(a)中，第一层是低k值绝缘材料层10，它是沉积在基片11上的，局部通孔蚀刻在该材料的表面上，标以12。此时在蚀刻通孔构形12时是相当直接的，因为层10的整个表面是完全暴露在外的。图5(b)中，在沉积第二共形层13时要填满构形12但其结构造形如14所示能反映在层13的表面上。然后在层13的上表面掩蔽所希望的布线图案并如图5(c)所示局部蚀刻出布线沟道15。与此同步而且不可避免的是也要对构造14的底部进行蚀刻而且要如图5(c)和(d)所示一直向下蚀刻到构造12。在图5(d)所示的点上，层13中留下距离X未蚀刻，而层11中留下距离Y未蚀刻。虽然在示意图上并不清楚但Y常常比X大而且比率Y/X将决定层13和11的材料各自所选用的蚀刻速度。在如图所示的布置下，事实上Y大约为X的二倍，相应地材料11的蚀刻速度也约为材料13的两倍。
材料11可按上述方式方便地提供蚀刻阻挡信号。因而看一下上述的蚀刻速度可以看出：掺碳氮化硅和掺碳二氧化硅提供蚀刻速度比或选择性大约为2∶1，而如前所述，二氧化硅对掺氮碳化硅的选择性大约为3∶1。调整掺杂即可获得其他一些选择性。

Claims (16)

1．一种半导体器件，含有在介质堆叠层内形成的双镶嵌结构，该堆叠层包括内含第一蚀刻构造的上层，中间蚀刻阻挡层以及内含第二蚀刻构造的下层，第二构造经蚀刻阻挡层与第一构造相连，每层具有介电常数k≤3.5，蚀刻阻挡层相对于上层的选择性至少为2.5∶1。
2．根据权利要求1所述的半导体器件，其中，所述的蚀刻阻挡层是与下层相集成的。
3．根据权利要求1或2所述的器件，其中，所述的蚀刻阻挡层是由掺氮的碳化硅形成的。
4．一种在基片上形成低k值膜的方法，包括：
(a)把基片放置在室内的一个支撑物上；
(b)往室里加入气态或蒸汽形式的含硅有机化合物和氮在有等离子体存在的条件下向基片上沉积一层掺氮碳化硅膜。
5．根据权利要求5所述的方法，其中，掺氮的碳化硅是在低于4MHz频率驱动下由等离子体沉积的。
6．根据权利要求4或5中所述的方法，其中，所述的含硅有机化合物是烷基硅烷。
7．根据权利要求4～6中任一项的方法，其中，所述的含硅有机化合物是四烷基甲硅烷。
8．根据权利要求4～6中任一项的方法，其中，所述的含硅有机化合物是四甲基硅烷。
9．一种蚀刻阻挡层含有掺氮的碳化硅。
10．一种电介质堆叠层，其中每层由不同的材料形成，各层材料可检测到不同的蚀刻特性但具有基本相等的介电常数。
11．根据权利要求10所述的介质堆叠层，其中，邻接层之间的选择性至少为2.5∶1。
12．一种形成双镶嵌结构的方法，包括：把具有第一蚀刻速度的第一绝缘材料层沉积在半导体晶片上，在第一层中部分地蚀刻出一或多个通孔，接着把第二绝缘材料层沉积在第一层上，使得第二材料填满部分地蚀刻出的通孔并在第二层的表面显现出相应的构造，在第二层上蚀刻出容纳布线线路的沟道使得该沟道包含相应的构造，各类材料相对蚀刻速度是这样的：当把沟道蚀刻到第一层的表面时，通孔被充分地蚀刻通过第一层。
13．根据权利要求10或11所述的堆叠层，其中，邻接层的材料其介电常数的相异性在小于10％内变化。
14．根据权利要求13所述的方法，其中，所述第一层的蚀刻速度大约为第二层的二倍。
15．根据权利要求12所述的方法，其中，所述的第一层是掺碳的SiO2而第二层是掺氮的SiC或掺碳的氮化硅。
16．一种形成低k值蚀刻阻挡层的方法，包括：在大于4MHz频率下通过基于等离子体的反应沉积掺碳的SiO2以及在小于4MHz频率下通过基于等离子体的反应把掺氮的SiC沉积到SiO2材料上。
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