CN1716546B - 介电层及集成电路 - Google Patents

介电层及集成电路 Download PDF

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CN1716546B
CN1716546B CN2005100801462A CN200510080146A CN1716546B CN 1716546 B CN1716546 B CN 1716546B CN 2005100801462 A CN2005100801462 A CN 2005100801462A CN 200510080146 A CN200510080146 A CN 200510080146A CN 1716546 B CN1716546 B CN 1716546B
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dielectric layer
metal layers
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CN1716546A (zh
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黎丽萍
章勋明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种介电层及集成电路，所述介电层包括：一顶部部分；以及一底部部分，其中上述介电层具有由顶部部分往底部部分大体均匀地变化的密度。本发明所述介电层、其形成方法与具有此介电层的集成电路，可允许调整金属层间介电层的密度特性以改善其步阶覆盖表现，并同时允许调整残余的金属层间介电层以改善其电性/介电常数特性。

Description

介电层及集成电路
技术领域
本发明是有关于低介电常数介电材料的形成方法，且特别是有关于一种有介电常数沿其厚度方向上梯度变化的低介电常数介电层的形成方法以及应用此低介电常数介电层的集成电路结构。 
背景技术
随着半导体元件积集度的提升，半导体装置的尺寸也随之缩减。缩小化的半导体装置尺寸于其制作时需要更薄膜层，如薄化的介电层。当半导体装置密度变大以及介电层变薄时，膜层间的寄生电容便成为一显在问题而会影响半导体装置的表现。 
现有用以减少寄生电容的方法中包括采用具有低介电常数的介电材料的方法。通常，具有低于二氧化硅的介电常数(约3.9)的材料，始可称之为低介电常数介电材料。通过应用如此的低介电常数介电材料以替代传统介电材料可有效减少如金属内连线结构内的寄生电容。 
然而，低介电常数介电材料仍具有某些缺点。其中之一为低介电常数介电材料具有如附着力不佳以及较差的机械强度等低机械特性。此些缺点降低了半导体装置的良率、可靠度以及其整体表现。 
如此，便需要一种低介电常数介电材料以克服前述的现有低介电常数介电材料的机械特性上缺点。 
发明内容
有鉴于此，本发明提供了一种介电层，包括： 
一顶部部分；以及一底部部分，其中介电层具有由顶部部分往底部部分大体线性地或正弦地变化的密度。 
本发明所述的介电层，该密度由该顶部部分的1.5克/立方公分变化至该底部部分的1.2克/立方公分。 
本发明所述的介电层，由该顶部部分至该底部部分，该密度至少变化10％。 
本发明所述的介电层，该介电层包含氧，且该介电层的氧含量自该顶部部分至该底部部分至少变化3％。 
本发明另提供了一种介电层的形成方法，包括下列步骤： 
提供一基底；通过导入至少两种的气体至该基底，以起始一介电层的化学气相沉积；以及于沉积该介电层时改变该些气体的流率比例，以于形成的一介电层内大体均匀地变化该些气体之一的浓度。 
本发明所述的介电层的形成方法，通过变化该些气体流量比例以使得该介电层具有至少一密区以及至少一疏区。 
本发明还提供了一种介电层的形成方法，包括下列步骤： 
形成一介电层于一基底上；暴露该介电层的顶面于一等离子下；以及继续暴露该介电层于该等离子下直到该介电层具有一期望的密度曲线。 
本发明还提供一种集成电路，所述集成电路包括： 
至少一晶体管，该晶体管包括一源极区、一漏极区以及一栅电极；一层间介电层，设置于该源极区、漏极区以与门电极之上；一接触结构，形成于该层间介电层内且至少电性接触该源极区、该漏极区与该栅电极其中之一；一内连结构，接触该接触结构； 以及一金属层间介电层，通过一大体连续的制程步骤形成，设置于至少一部分的该内连结构上，该金属层间介电层包括：一第一部分，具有一第一介电常数；一第二部分，具有一第二介电常数，其中该金属层间介电层的介电常数由该第一部分至该第二部分大体连续地变化且该金属层间介电层的孔隙度自该第一部分的10％变化至该第二部分的5％。 
本发明所述的集成电路，该金属层间介电层包括为主要材质为有机硅基材料。 
本发明所述的集成电路，该金属层间介电层的介电常数由其顶部的2.2变化至其底部的3.5。 
本发明所述的集成电路，该金属层间介电层的介电常数由其顶部部分至其底部部分线性地变化。 
本发明又提供一种介电层，所述介电层包括： 
一顶部部分；一底部部分；以及至少一中间部部分，位于该顶部部分与该底部部分之间，其中该介电层具有由该顶部部分往该底部部分大体均匀且连续地变化的密度，且该顶部部分与该底部部分为一缜密区，该至少一中间部部分为一疏区，其中该密度是由该顶部部分通过该至少一中间部部分而往该底部部分而线性地或正弦地变化。 
本发明所述介电层、其形成方法与具有此介电层的集成电路，可允许调整金属层间介电层的密度特性以改善其步阶覆盖表现，并同时允许调整残余的金属层间介电层以改善其电性/介电常数特性。 
附图说明
图1是一种本发明的半导体装置； 
图2是本发明的半导体结构； 
图3是依据本发明一实施例的介电层中的密度曲线； 
图4a与图4b是依据本发明另一实施例的介电层中的密度曲线； 
图5是依据本发明另一实施例中的具有良好步阶覆盖的介电层。 
具体实施方式
为了让本发明的上述和其它目的、特征和优点能更明显易懂，下文特举一较佳实施例，并配合所附图示，作详细说明如下： 
图1图标了一集成电路结构2，其包括形成于基底4上的一金属氧化物半导体场效应晶体管(MOSFET)装置6。基底4可为一传统的块状基底，例如为一单晶硅晶圆，或为形成于一埋入氧化层上(未图示)如硅层、硅锗层或其相似物的一半导体层，上述埋入氧化层与半导体层是依序形成于如硅、石英、玻璃或其相似物(即绝缘层上有硅的基底)的一支撑基底上。金属氧化物半导体场效应晶体管装置6包括形成于基底4内的一源极区8以及一漏极区10，以定义出其间的沟道区。金属氧化物半导体场效应晶体管装置6更包括位于信道区上的一栅电极14且通过栅介电层12与的隔离。通常，间隔物16形成于邻近栅电极14处且分别用以形成源极区8与漏极区10。 
图1亦分别显示了源极区8与漏极区10的电性连接情形，其分别以接触物18、20以电性连接于源极区8与漏极区10与金属内连物22、24。介电层26则位于金属氧化物半导体场效应晶体管元件6上且用以电性绝缘此装置与后续形成元件，包括金属内 连物22、24(除了于如接触结构18与20处等需电性连接于此装置的位置)。介电层26通常亦称之为层间介电层(ILD)。于某些实施例中，特别是当金属内连物22、24是通过镶嵌或双镶嵌制成形成时，介电层26亦作为支撑内连线之用。于传统半导体装置中，介电层26通常由二氧化硅或相似物所形成。无论其使用材料为何，其膜层通常大体同质且沿其厚度方向上具有大体一致的材料特性。 
介电层26亦可能包含如蚀刻停止层28的一蚀刻停止层，其有助于于后续形成的介电层内形成介层洞与沟槽，于下文中将更解释其作用。举例来说，介电层26可更包括两或两个以上的分离次膜层。 
于图1中亦显示了一金属层间介电层(IMD)30。金属层间介电层30是作为金属内连物22、24与后续形成的内连结构(未图标)的电性绝缘之用，除了于经由如介层洞32以电性连接形成于内连线结构24上之后续内连结构(未图标)之处外。金属层间介电层30可包括两或两个以上的分离次膜层。金属层间介电层30则通常通过与层间介电层的相同类型的材料所形成，但由于两者表现、制程以及相关需求不同，通常层间介电层与金属层间介电层间的材质不为相同。如同层间介电层，传统的金属层间介电层沿其厚度方向的机械与材料特性亦为一致的。 
图2是图示本发明的一实施例，其中所形成的金属层间介电层40沿其厚度方向上具有大体连续变化的介电常数。图3则图示了自金属层间介电层40内最底部区(即邻近内连线结构22与24以及蚀刻停止层28处)至介电层40内最顶部区“即邻近于后续形成的内连线结构(未图标)以及/或蚀刻停止层(亦未图示)”的介电常数变化。如图3所示，自介电层40的底部至顶部，其密度逐渐地自1.2克/立方公分增加至约1.5克/立方公分。而密度是正比于介 电常数(当薄膜密度减少时介电常数亦减少)。故最终的低介电常数介电层40具有低介电常数的优点，且同时较传统低介电常数层提供了较佳的机械强度与表现。低介电常数介电层36亦可通过相似技术以获得大体连续变化的介电常数，如下所述。 
于另一实施例中，金属层间介电层40是通过有机硅基材料(organo silica based material)所形成，其例如由氧与四甲基硅烷(tetramethylsilane；简称为4MS)、三甲基硅烷(trimethylsilane；简称为3MS)以及八甲基环四硅氧烷(octamethylcyclotetrasiloxane)等的硅烷(silane)类化合物所沉积形成的材料。于本发明中，金属层间介电层40的厚度与最小的特征尺寸以及其特定用途有关。于单镶嵌金属层应用，金属层间介电层40的厚度约介于1800～3000埃。而于双镶嵌金属层中，金属层间介电层40的厚度则约介于4000～8000埃。于膜层中，介电常数是沿膜层的厚度方向而变化。于一实施例中，介电常数沿其厚度的变化自其底部区的3.0于改变至其中间区的2.0最后至其顶部区的3.0。如此的介电常数梯度变化可通过精密控制沉积参数而达成。于第一实施例中的膜层是通过化学气相沉积法所形成。介电常数的控制较佳地可通过等离子处理一沉积薄膜或通过调整沉积时硅甲烷与氧气比例而达成。 
于一范例中，例如四甲基硅烷(4MS)所制备的有机硅基材料可通过化学气相沉积法于约2～6托(Torr)下，较佳地约3～5托(Torr)下，以及于30-450℃下，较佳地于30-250℃下所沉积而成，以形成一介电层。通过于化学气相沉积反应室中通入氧气与硅烷类化合物的一混合物以形成薄膜。于薄膜沉积的开始时，硅烷类化合物的流量较佳地约为200～1500sccm，而采用四甲基硅烷(4MS)时的较佳流量约为250sccm，而氧气流量约为400～1500sccm，而于使用四甲基硅烷(4MS)时，氧气的较佳流量 约为600sccm。接着逐渐地调整其相对流量比例以达到预定梯度的密度与介电常数。举例来说，于使用四甲基硅烷以沉积薄膜的范例中，四甲基硅烷的流速与氧气的流速比例可自薄膜底部部分的约0.4(以提供约2.8的介电常数)变化至薄膜顶部部分的约0.8(以提供约2.5的介电常数)。 
于另一范例中，当相对流量比例保持大体一致时，则于薄膜沉积程序开始后通过改变沉积反应室内的压力以改变介电常数。举例来说，当四甲基硅烷与氧气流量比例约为0.4时，逐渐将压力从3托增加至5托。于如此的循环下，所得到薄膜具有沿厚度方向自2.8变化至2.6的介电常数。 
于另一实施例中，薄膜的介电常数可通过沉积后的等离子处理所调整。等离子处理可造成沉积薄膜的缜密化，因而增加其介电常数。上述缜密化现象于薄膜上部表面最为明显，而等离子处理的冲击将逐渐地且大体连续地沿其厚度方向往下方部分递减。 
于一范例中，金属层间介电层40是通过通入四甲基硅烷与氧气后形成，其并经由氢气等离子的处理。此等离子较佳地于约250～400℃温度下以及约4托的压力下形成。对于厚度约为6000埃的膜层，等离子处理需30秒～5分钟以有效形成大体穿过整个薄膜厚度的足够介电常数梯度。于一范例中，材料的介电常数通常自顶部的2.2变化至底部的3.5。 
如前所述，当化学气相沉积程序与等离子处理程序是为分开施行时，本领域技术人员可了解上述实施例中，于薄膜沉积时可调整于上述程序内的气体流速比例，或可更于薄膜沉积后通过后续等离子的处理而达到所要的介电常数梯度。 
上述沉积技术允许于所形成的介电层内的密度控制。如现有技艺中，较缜密的膜层具有较高介电常数(此为低介电常数介电材料所不期望的情形)，但其具有较佳的机械特性。反之，当膜层较 为疏散时，其介电常数特性变为的改善，但有损其机械强度、附着能力或相似特性。薄膜密度是与薄膜的孔隙度与/或薄膜中成分的一的浓度(如上述实施例内的氧气)有关。于某些较佳实施例中，可通过将薄膜的缜密区至其较不缜密区的薄膜孔隙度变化至少5％而改变介电常数的梯度。缜密区的孔隙度较佳地低于10％而缜密区较佳地占薄膜整体厚度的5％。薄膜孔隙度的梯度变化则可通过如前所述的等离子处理而得到。 
于其它较佳实施例中，薄膜密度可通过控制组成成份之一的浓度而达成，例如薄膜中的氧气含量。于较佳实施例中，氧气所占百分比的改变量至少约为3％，较佳地为10％。其浓度梯度可通过调整硅甲烷/氧气流量比例而得到。而于其它较佳实施例中，介电常数梯度可通过改变孔隙度与组成成份之一的浓度而得到。于如此的实施例中，孔隙度的改变量至少为5％而其组成成份之一的浓度改变量至少约为3％。 
如图3所示，介电薄膜可自其顶部的缜密区至其底部较不缜密区(或称之为疏区)逐渐地改变，而具有线性的介电常数曲线。图4a则图示了另一实施例，其中介电薄膜的密度(或介电常数)是通过于位置于顶部与底部缜密区之间的中间部形成一较不缜密区(或称之为疏部)而控制。如此的实施例可提供具有良好机械特性与附着特性的顶部与底部部分，而主要部分的中间部则可提供主要的低介电常数特性。图4b则图示了另一实施例，其中薄膜密度沿其薄膜厚度方向上大体正弦地或疏或密地变化。如此的方法可改变薄膜密度且提供薄膜如提供相对于下层或上层膜层的较佳附着力的优点，当且于疏区的低介电常数特性亦提供用以降低寄生电容的功效。如此正弦模式适用于当蚀刻停止层存在于整个内层介电层的中间区时(因其需要缜密薄膜区以达到良好附着)。本领域技术人员应可了解密度/孔隙度曲线的变化可通过改变等离子处理与 气体比例而达成。亦可采用其它制程以改变薄膜孔隙度与组成成份浓度，例如通过热治疗、电子束治疗，紫外光治疗或相似方法以处理沉积而成的介电层。 
图5则图示了本发明的另一实施例，是以一放大图标显示，一装置50包含形成有一步阶高度54的基底52(其可为前述形成的介电层、内连结构、蚀刻停止层，或类似膜层)。步阶高度54是起因于如内连线结构的结构56的出现。于其它实施例中，当结构56形成于基底52内时，结构56是于基底52形成前形成，因而于基底52上形成一不平坦的顶面。于一实施例中，步阶高度54约为200埃左右。由于步阶覆盖程度是为如图5所示的形成于基板52上且包括一步阶高度的金属层间介电层60的介电层的重要特性。本发明优点之一在于，可允许调整金属层间介电层的密度特性以改善其步阶覆盖表现，并同时允许调整残余的金属层间介电层以改善其电性/介电常数特性。 
前述实施例中所描述的介电层是关于通过四甲基硅烷所形成的一介电层。本领域技术人员可以了解，上述教导亦可应用于包括为有机或无机的硅基材料、有机聚合物、有机-无机混合材料或其组合等其它材料。 
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。 
附图中符号的简单说明如下： 
2：集成电路 
4：基底 
6：金属氧化物半导体场效应晶体管装置 
8：源极区 
10：漏极区 
12：栅介电层 
14：栅电极 
16：间隔物 
18、20：接触物 
22、24：金属内连物 
26：介电层 
28：蚀刻停止层 
30、40：金属层间介电层 
32：介层洞 
36：低介电常数介电层 
50：装置 
52：基底 
54：步阶高度 
56：结构 
60：金属层间介电层 

Claims (9)

1.一种介电层，其特征在于所述介电层包括：一顶部部分；以及
一底部部分，其中该介电层具有由该顶部部分往该底部部分线性地或正弦地变化的密度。
2.根据权利要求1所述的介电层，其特征在于：该密度由该顶部部分的1.5克/立方公分变化至该底部部分的1.2克/立方公分。
3.根据权利要求1所述的介电层，其特征在于：由该顶部部分至该底部部分，该密度至少变化10％。
4.根据权利要求1所述的介电层，其特征在于：该介电层包含氧，且该介电层的氧含量自该顶部部分至该底部部分至少变化3％。
5.一种集成电路，其特征在于所述集成电路包括：
至少一晶体管，该晶体管包括一源极区、一漏极区以及一栅电极；
一层间介电层，设置于该源极区、漏极区以与门电极之上；
一接触结构，形成于该层间介电层内且至少电性接触该源极区、该漏极区与该栅电极其中之一；
一内连结构，接触该接触结构；以及
一金属层间介电层，通过一连续的制程步骤形成，设置于至少一部分的该内连结构上，该金属层间介电层包括：
一第一部分，具有一第一介电常数；
一第二部分，具有一第二介电常数，其中该金属层间介电层的介电常数由该第一部分至该第二部分连续地变化且该金属层间介电层的孔隙度自该第一部分的10％变化至该第二部分的5％。
6.根据权利要求5所述的集成电路，其特征在于：该金属层间介电层包括为主要材质为有机硅基材料。
7.根据权利要求5所述的集成电路，其特征在于：该金属层间介电层的介电常数由其顶部的2.2变化至其底部的3.5。
8.根据权利要求5所述的集成电路，其特征在于：该金属层间介电层的介电常数由其顶部部分至其底部部分线性地变化。
9.一种介电层，其特征在于所述介电层包括：
一顶部部分；
一底部部分；以及
至少一中间部部分，位于该顶部部分与该底部部分之间，其中该介电层具有由该顶部部分往该底部部分均匀且连续地变化的密度，且该顶部部分与该底部部分为一缜密区，该至少一中间部部分为一疏区，其中该密度是由该顶部部分通过该至少一中间部部分而往该底部部分而线性地或正弦地变化。
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