CN1245744C - 半导体元件的制造方法以及半导体元件 - Google Patents
半导体元件的制造方法以及半导体元件 Download PDFInfo
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- CN1245744C CN1245744C CNB031553346A CN03155334A CN1245744C CN 1245744 C CN1245744 C CN 1245744C CN B031553346 A CNB031553346 A CN B031553346A CN 03155334 A CN03155334 A CN 03155334A CN 1245744 C CN1245744 C CN 1245744C
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- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Y | X | Z | |
芯片 | 5600 | 3000 | 470 |
间隙 | 504 | 270 | 42 |
Claims (39)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10239866.6 | 2002-08-29 | ||
DE10239866A DE10239866B3 (de) | 2002-08-29 | 2002-08-29 | Verfahren zur Herstellung eines Halbleiterbauelements |
Publications (2)
Publication Number | Publication Date |
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CN1489193A CN1489193A (zh) | 2004-04-14 |
CN1245744C true CN1245744C (zh) | 2006-03-15 |
Family
ID=31983885
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CNB031553346A Expired - Fee Related CN1245744C (zh) | 2002-08-29 | 2003-08-27 | 半导体元件的制造方法以及半导体元件 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6953708B2 (zh) |
CN (1) | CN1245744C (zh) |
DE (1) | DE10239866B3 (zh) |
SG (1) | SG106156A1 (zh) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4624131B2 (ja) * | 2005-02-22 | 2011-02-02 | 三洋電機株式会社 | 窒化物系半導体素子の製造方法 |
SG135074A1 (en) | 2006-02-28 | 2007-09-28 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
US8283756B2 (en) * | 2007-08-20 | 2012-10-09 | Infineon Technologies Ag | Electronic component with buffer layer |
TWI360207B (en) | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
FR2934082B1 (fr) * | 2008-07-21 | 2011-05-27 | Commissariat Energie Atomique | Dispositif multi composants integres dans une matrice |
US7776649B1 (en) * | 2009-05-01 | 2010-08-17 | Powertech Technology Inc. | Method for fabricating wafer level chip scale packages |
TWI456715B (zh) * | 2009-06-19 | 2014-10-11 | Advanced Semiconductor Eng | 晶片封裝結構及其製造方法 |
TWI466259B (zh) * | 2009-07-21 | 2014-12-21 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法 |
TWI405306B (zh) | 2009-07-23 | 2013-08-11 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體 |
US20110084372A1 (en) | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
US8378466B2 (en) | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
US10057333B2 (en) | 2009-12-10 | 2018-08-21 | Royal Bank Of Canada | Coordinated processing of data by networked computing resources |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US8372689B2 (en) | 2010-01-21 | 2013-02-12 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof |
US8320134B2 (en) | 2010-02-05 | 2012-11-27 | Advanced Semiconductor Engineering, Inc. | Embedded component substrate and manufacturing methods thereof |
US20110198762A1 (en) * | 2010-02-16 | 2011-08-18 | Deca Technologies Inc. | Panelized packaging with transferred dielectric |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
DE102014111106A1 (de) | 2014-08-05 | 2016-02-11 | Osram Opto Semiconductors Gmbh | Elektronisches Bauelement, optoelektronisches Bauelement, Bauelementeanordnung und Verfahren zur Herstellung eines elektronisches Bauelements |
IT201700055942A1 (it) | 2017-05-23 | 2018-11-23 | St Microelectronics Srl | Procedimento per fabbricare dispositivi a semiconduttore, dispositivo e circuito corrispondenti |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2189343B (en) | 1986-04-02 | 1990-11-14 | Int Rectifier Co Ltd | Semi-conductor modules |
US5172215A (en) | 1990-03-06 | 1992-12-15 | Fuji Electric Co., Ltd. | Overcurrent-limiting type semiconductor device |
JP3258764B2 (ja) * | 1993-06-01 | 2002-02-18 | 三菱電機株式会社 | 樹脂封止型半導体装置の製造方法ならびに外部引出用電極およびその製造方法 |
JPH0878574A (ja) * | 1994-09-08 | 1996-03-22 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JPH09321168A (ja) | 1996-03-22 | 1997-12-12 | Shinko Electric Ind Co Ltd | 半導体パッケージ及び半導体装置 |
JPH1174403A (ja) | 1997-08-28 | 1999-03-16 | Mitsubishi Electric Corp | 半導体装置 |
KR100266693B1 (ko) * | 1998-05-30 | 2000-09-15 | 김영환 | 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법 |
JP2001230348A (ja) | 2000-02-18 | 2001-08-24 | Hitachi Ltd | 半導体装置 |
US6709898B1 (en) * | 2000-10-04 | 2004-03-23 | Intel Corporation | Die-in-heat spreader microelectronic package |
DE10233641B4 (de) * | 2002-07-24 | 2007-08-23 | Infineon Technologies Ag | Verfahren zur Verbindung einer integrierten Schaltung mit einem Substrat und entsprechende Schaltungsanordnung |
-
2002
- 2002-08-29 DE DE10239866A patent/DE10239866B3/de not_active Expired - Fee Related
-
2003
- 2003-08-15 US US10/642,063 patent/US6953708B2/en not_active Expired - Fee Related
- 2003-08-26 SG SG200305360A patent/SG106156A1/en unknown
- 2003-08-27 CN CNB031553346A patent/CN1245744C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6953708B2 (en) | 2005-10-11 |
DE10239866B3 (de) | 2004-04-08 |
CN1489193A (zh) | 2004-04-14 |
SG106156A1 (en) | 2004-09-30 |
US20040113270A1 (en) | 2004-06-17 |
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