CN1238856A - 芯片模块及制造芯片模块的方法 - Google Patents

芯片模块及制造芯片模块的方法 Download PDF

Info

Publication number
CN1238856A
CN1238856A CN97180008A CN97180008A CN1238856A CN 1238856 A CN1238856 A CN 1238856A CN 97180008 A CN97180008 A CN 97180008A CN 97180008 A CN97180008 A CN 97180008A CN 1238856 A CN1238856 A CN 1238856A
Authority
CN
China
Prior art keywords
chip
chip module
lead
circuit board
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN97180008A
Other languages
English (en)
Inventor
J·菲舍尔
J·黑策尔
M·胡伯尔
F·皮施纳
P·斯坦普卡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of CN1238856A publication Critical patent/CN1238856A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • G06K19/07747Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743External electrical contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • H05K3/3426Leaded components characterised by the leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/1016Shape being a cuboid
    • H01L2924/10161Shape being a cuboid with a rectangular active surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10977Encapsulated connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305Moulding and encapsulation
    • H05K2203/1316Moulded encapsulation of mounted components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49169Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171Assembling electrical component directly to terminal or elongated conductor with encapsulating
    • Y10T29/49172Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Credit Cards Or The Like (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明涉及一种芯片模块,该模块含有一接触区(3)以及含有至少一个半导体芯片(6),接触区布置在其外侧(2)上,有许多基本上扁平的,相互绝缘的,导电材料组成的接触元件(4),半导体芯片含有一个或多个半导体集成电路,这些电路通过引线(8)与接触区(3)的接触元件(4)电学上连接。芯片模块(1)的接触元件(4)由一预制的引线框架(20)(Leadframe)形成,用于支撑至少一个半导体芯片(6),并且形成在芯片模块(1)的至少两对边上,通过相互邻近排列布置的向外适配的引线(8)用于芯片模块(1)在外部印刷电路板或外部电路板基片(10)的安装表面(9)上的表面安装。

Description

芯片模块及制造芯片模块的方法
本发明涉及一种含有一接触区以及含有至少一个半导体芯片的芯片模块,接触区布置在其外侧上,有许多基本上扁平的,相互绝缘的,导电材料组成的接触元件,半导体芯片含有一个或多个半导体集成电路,这些电路通过引线与接触区的接触元件电学上连接。本发明同样涉及制造这样一种芯片模块的方法,和涉及这种芯片模块在芯片卡或类似数据载体中的使用,以及涉及在印刷电路板上或中,或在电路板基片上或中的使用。
在芯片卡的制造中,芯片模块是作为技术上完成的中间产品制造的,并被进一步单独处理进入最终产品。在此芯片模块被理解为意味着根据权利要求1的前序部分所述的装置,其中一个或多个集成半导体电路以芯片的形式被布置在基片上或中,芯片通过引线与提供在基片至少一侧上的导线系统连接。对于一种已知的芯片模块,基片主要由环氧树脂或类似的塑料材料制成的一载体形成,载体上安装有真正半导体芯片,并且在载体上,在具有ID-1,ID-00或ID-000规格触点的通常芯片卡的外侧,布置有常常是镀金的,通常6个或8个接触元件,以此实现与外部卡片阅读/写入站的电学连接用于电源供电和与集成在芯片卡中的微控制器电路的数据传输。接触元件相对于芯片卡体的位置以及它们的尺寸按照国际标准ISO 7810或ISO 7816-2设计。有关芯片模块和芯片卡的结构和制造的进一步细节和特点,主要涉及Wolfgang Rankl,Wolfgang Effing,芯片卡手册,CarlHanser Verlag,1995,ISBN 3-446-17993-3及其全部内容。
由于增加涉及芯片卡领域安全性方面的应用,对于满足最高安全性要求的微控制器的需求正在增长。通过使用所谓的密码控制器,可能达到非常高的安全水平,该密码控制器借助协同处理器实现相对于不对称片上安全算法的高速执行的特别的计算性能。由于密码控制器在芯片卡中和电路板上两者中的双重使用,例如在所谓的PCMCIA插入式卡片,银行和财务机构中用于密码控制器电信的阅读系统以及类似阅读装置的情况下,不同的可靠性要求意味着密码控制器电路使用不同的外壳形状,但是由于不同的制造工艺和不同的材料,这在成本和后勤费用方面带来相当多的缺点。
有SMT功能的芯片外壳具有一些特殊形状的引线,它们容许自动安装以及同样自动焊接操作。在对应于表面安装技术的一种优选的半导体芯片和电路板间的连接技术的情况下,采用丝网印刷将焊剂覆在电路板上,并且随后半导体芯片封装后作为被表面安装的装置,被定位于其上。为了建立电路板和半导体芯片间的连接,电路板被放入炉中以熔化焊料。在这种情况下,必须确保焊接连接是可靠的,并且在确定的点上制造,不存在导致将会产生的短路或形成不良接触的焊料流失。
与此相反,目前芯片卡使用的芯片模块含有有着相当大面积的触点,这主要是用作与外部阅读器的读出探头建立可靠的接触。
由此有必要为不同的应用提供不同的外壳或芯片载体,由于不同的制造工艺,后勤(Logistik),材料等等问题,这导致生产成本的增加。
本发明的目的在于提供一些构造方法,由此,一种最初为芯片卡应用而制造的模块同样可以被进一步处理用于外部电路板中或上。
借助根据权利要求1所述的芯片模块和根据权利要求15所述的制造芯片模块的方法,本目的得以实现。采用这样一种芯片模块用于制造芯片卡或类似的数据载体的方法在权利要求27中提出,芯片模块在印刷电路板上或中,或在电路板基片上或中的使用被在权利要求29中提出。
根据本发明,规定芯片模块的接触元件由一预制的引线框架(Leadframe)形成,用以支撑至少一个半导体芯片,并且形成在芯片模块的至少两对边上,通过相互邻近排列布置的向外适配的引线用于芯片模块在外部印刷电路板或外部电路板基片安装表面上的表面安装。这种预制引线框架不仅以一种有利的方式实现单纯的电气功能,并且同时满足了安装的技术要求;为半导体芯片提供了一个用于电气接合的可靠支点;同时支承了对应于芯片引线并且含有一容许实现良好接触表面的引线焊盘;用作一个机械上确定的可靠支承,用于输送操作以及用于进一步处理;并且同样用于热耗散或热分布。依据按照本发明的解决方法,用在芯片卡模块中的半导体集成电路,特别是微控制器或密码控制器电路,可以被成功地用作只是一种外壳形状的电子元件,同时用作可以被表面安装在电路板,插入式卡片或类似基片的安装表面上的装置。本发明提供了下列胜过现有工艺的基本优点:
-芯片模块可被选择性地用于安装在芯片卡中或用作一可表面安装的装置,这种选择建立在在芯片模块制造工艺的结尾时一个相对简单的附加机械加工步骤,但也还能够在所谓的前端制造过程中完成;
-通过采用唯一的一种外壳形状,后勤,存货,运输等等费用可被显著地降低;
-由于唯一的一种标准制造工艺被用于一个标准元件,而该元件可以用于两种完全不同的应用领域,生产费用大大低于依据先前已知两种不同的外壳形状以及因而两种不同的制造技术的生产费用;
-在制造芯片模块的工艺工序中,同样在其作为一可表面安装的装置的应用中,基本上不需要改变,而且更进一步,先前在模块组装中执行的生产步骤可基本上没有改变地采用;
-按照本发明的芯片模块,在其作为一可表面安装装置的应用中,整体高度大大小于先前单独制造的具有SMT功能的元件;
-对于用作可表面安装的装置,芯片模块适用于所有常用的焊接方法,例如烙铁焊,波焊和回流焊等;这样,用于芯片模块表面安装的引线可以按照SMT安装所需要的质量,根据所保留的容隙,焊接点的可靠性,焊接方法等等被提供以结构上不同的焊接附件(Loetansatz);
-紧接着最后,包括芯片模块接触元件的成形,即使是被设计为一可表面安装的装置,芯片模块可以采用相同的进一步制造步骤被进一步处理(芯片焊接,引线键合,覆盖或压制,电测试,外表检查以及类似的功能测试),以此较容易地同时进行对不合格芯片模块的处理和报废;
-存在将现有植入技术用于在芯片卡中安装芯片模块的可能性;因此,先前已知的用于芯片卡制造的技术可以不加限制地继续使用。
接触元件的几何布置和尺寸由ISO标准细则决定,特别是用于芯片卡的ISO 7810,但同时要在足够的引线的焊接阻挡层,元件的耐热性等方面满足加在SMT模块上的要求。一种特别优选的设计的要点在于,用来形成可表面安装引线的引线框架的接触元件是这样形成的,它们相互平行设置,并且相互有一预定的距离,它们中心线间的该距离对应于形成在外部印刷电路板或外部电路板基片的安装表面上的接线点连接间隔(Anschlussraster),该连接间隔特别地为1.27mm或其倍数。这样,按照本发明的芯片模块同样适合于用自动装配机处理,该装配机用于具有典型外壳设计TSOP,SOT,SO,VSO,以及同样具有给定间隔1.27mm的向外弯的焊接附件的小型化元件的机械组装的表面安装技术(SMT)中。
为了使芯片模块在印刷电路板的连接间隔上较容易地定位,在此可以有利地规定,用来形成可表面安装引线的接触元件配有一焊接附件,用于芯片模块在外部印刷电路板或外部电路板基片的安装表面上的牢固连接。
在用焊接方法实现芯片模块在印刷电路板的连接间隔上表面安装的情况下,为了减小由于使用焊剂导致电气短路的风险,可以有利地规定,可表面安装引线的焊接附件由一相对于接触元件平面横向设置的间距保持器(Abstandhalter)形成。
对于一种可以以低成本制造的结构上特别简单的芯片模块,在本发明一项特别优选的设计的情况下可规定,基本上长方形设计的可表面安装引线的宽度稍小于连接间隔。
为了保护半导体芯片以防外部机械和化学影响,可规定有电学上绝缘材料的,整个盖住半导体芯片的芯片封装。为了将被优选加在接触元件自由端的焊接附件能够接近在此使用的工具,可以有利地规定,引线框架的向外适配的可表面安装引线沿安装平面方向延伸至芯片封装外。
将被加在接触元件自由端的焊接附件的结构设计,可以按照表面安装对装配所要求的质量,根据所保留的容隙,焊接点的可靠性,焊接方法等等进行不同的设计。最简单的情况是,焊接附件可由一凹陷或开孔形成,该凹陷或开孔提供在向外适配的接触元件的面向电路板安装表面的一侧上,并优选采用冲压或化学刻蚀方法制成。此外,可以规定,焊接附件以提供有相应切口的向外适配的接触元件的多角形状形成,优选采用冲孔和/或弯曲方法制成。
由于芯片模块在印刷电路板上组装的特殊要求,模块的引线或接触元件被拉至模块覆层外也是可能的。在这种情况下规定,焊接附件由高出芯片封装整个高度的一适配物形成。
在本发明一更为优选设计的情况下,可以规定,预制引线框架在其面向半导体芯片的表面上有一绝缘膜,该膜在焊接附件附近和/或在连接引线附近配有一些开孔。绝缘膜,优选用塑料材料制成,这样其厚度有利地为约25μm~约200μm;合适的材料为,例如,环氧树脂,聚酰亚胺,聚酯,聚醚砜(PES),聚乙二酰脲(PPA),聚氯乙烯(PVC),聚碳酸酯,聚酰亚胺薄膜(Kapton)和/或丙烯腈-丁二烯-苯乙烯共聚物(ABS)或类似的高冲击韧性的热塑材料。
下面参照附图对本发明实施例的说明体现本发明的进一步的特点,优点和实用性,其中:
图1A为根据本发明第一实施例,有一已冲孔引线框架的可表面安装芯片模块的剖面图示,含有一塑料支撑载体和一覆有球形顶覆层的增强框架;
图1B为根据图1A的芯片模块的平面图示;
图1C为第一实施例的一种变型,含有一已冲孔的引线框架和球形顶设计支撑载体;
图1D为根据图1C的芯片模块的平面图示;
图2A为一可表面安装芯片模块的剖面图示,根据本发明的第二实施例含有一模压引线框架;
图2B为根据图2A的芯片模块的平面图示;
图2C为第二实施例的另一种设计的剖面图示,含有一引线框架,一塑料支撑载体和一球形顶覆层;
图3A为根据本发明第三实施例的一芯片模块的剖面图示;
图3B为根据图3A的芯片模块的平面图示;
图4A为根据本发明第四实施例的一芯片模块的剖面图示;
图4B为根据图4A的芯片模块的平面图示;
图5A为根据本发明第五实施例的一芯片模块的剖面图示;
图5B为根据图5A的芯片模块的平面图示;
图6A为根据本发明第六实施例的一芯片模块的剖面图示;
图6B为根据图6A的芯片模块的平面图示;
图7A为根据本发明第七实施例的一芯片模块的剖面图示;
图7B为根据图7A的芯片模块的平面图示;
图8A为根据本发明第八实施例的一芯片模块的剖面图示;
图8B为根据图8A的芯片模块的平面图示;
图9A为根据本发明第九实施例的一芯片模块的剖面图示;
图9B为根据图9A的芯片模块的平面图示。
在图1A至9B所示的所有本发明的实施例中,都包括有一芯片模块1,它含有一接触区3,接触区域布置在其外侧2上,有许多相互绝缘的,基本上扁平的,导电材料组成的接触元件4,并含有至少一片具有一个或多个半导体集成电路(图中未更详细示出)的半导体芯片6,这个或这些电路通过形式为键合线7的连接引线与接触区3的接触元件4电学上连接。芯片模块1的接触元件4通过相互邻近排列布置的向外适配的引线8形成在芯片模块1的两对边上,用于芯片模块1在外部印刷电路板10或外部电路板基片10的安装表面9上的表面安装。在印刷电路板10的安装表面9上,在此布置有具有给定间隔的焊接区域11,通常在表面安装技术中间隔为1.27mm,采用常用的焊接方法,这些焊接区作为接线点用于接触元件4的电气和机械连接。芯片模块1的接触元件4,用来形成可表面安装引线8,在这种情况下是这样形成的,它们相互平行设置,并且它们的中心线5相互有一预定距离a,该距离又对应于形成在印刷电路板10的安装表面9上的接线点11的连接间隔,即a=1.27mm。接触元件4,用来形成可表面安装引线8,在这种情况下配有一焊接附件12用于芯片模块1在印刷电路板10的安装表面9上的牢固连接。为了保护半导体芯片6以防外部机械和化学影响,被提供有电学上绝缘材料的,整个盖住半导体芯片的芯片封装13。各图中所示所有实施例共享该通用特征,即向外适配的可表面安装引线8沿安装平面14的方向延伸至芯片封装13以外。
所示的这些实施例首先在加在接触元件的自由端15上的焊接附件12的结构设计方面有所不同,按照可表面安装的装配所要求的质量,根据所保留的容隙,焊接点的可靠性,焊接方法等进行不同的设计。
实施例同样在保护半导体芯片6的芯片封装13的结构和布置上有所不同。在本发明的范围内,所示的任何所希望的芯片封装布置的设计可能性,包括用于设计焊接附件的所示的可能性在内,都是可以想象的;其结果是,这里明确示出的实施例仅仅代表可以想象的可能的设计中的一种选择。
在这种意义上,在根据图1A,1B,1C,1D,3A,3B,4A,4B,5A,5B,6A,6B,8A,8B所示实施例的情况下,焊接附件12由配有相应切口16a的向外适配的接触元件4的多角形16形成,优选采用冲孔和/或弯曲方法制成。另一方面,在根据图7A和7B所示实施例的情况下,焊接附件12由凹陷17形成,它提供在向外适配的接触元件4的面向电路板10安装表面9一侧上,相应地,在根据图9A和9B所示实施例的情况下,焊接附件12由开孔18形成,优选采用冲压或化学刻蚀方法制成。在根据图2A,2B和2C所示实施例的情况下,焊接附件12由高出芯片封装13整个高度的适配件19形成,其结果是对于该实施例,芯片模块1可以被向下面对半导体芯片6表面安装在电路板10的安装表面9上。
对于图中所示的所有实施例,根据本发明,接触元件4或引线8由一导电材料的预制引线框架20(Leadframe)形成,同时用作用于支撑半导体芯片6的抗弯基片并且支承含有一表面的引线焊盘21,该表面容许实现的良好的接触,焊盘借助键合线7用于电气连接。在根据图1A,1B,1C,1D,2C,3A,3B,4A,4B,6A,6B,7A,7B,9A,9B所示实施例的情况下,引线框架20被分配一中间载体,优选由塑料,或一薄绝缘膜22制成,在焊接附件12的范围内和/或引线焊点21的范围内,配有优选冲压开孔22a和22b。
对于芯片封装13的制造,根据本发明任务的结构设计的范围内,同样存在几种可能性。例如,芯片封装13可以使用一种经适当设计的铸模,采用铸塑化合物模制而成,或者采用配制一种可以热学上或UV光照射后可被固化的化合物制造而成。相应的实施例在图2A,2B,4A,4B,5A,5B,以及8A,8B中示出。另一方面,为了生产芯片封装13,为半导体芯片6配有一适当的塑料预制增强框架23同样是可以想象的,该增强框架被永久地固定在引线框架20上,优选采用粘着的方法,并随后用一所谓的球形顶覆层24,优选环氧树脂,一种可UV固化聚合物化合物等材料,封闭。这些设计变型在图1A,1B,3A,3B,6A,6B,7A和7B中更为详细地示出。此外,省略增强框架23并直接用一球形顶覆层25将半导体芯片6和键合线7包裹起来同样是可以的。这些实施例在图1C,1D,2C,9A,9B中更为详细地示出。
在根据图9A和9B所示实施例的情况下,中间引线8a和8b的端部15具有与外部引线8c和8d相比稍小的宽度;此外,接触元件4a至4d在其边缘区域基本上被设计为L形并且彼此啮合。该设计的优点在于,在对于可表面安装引线8a至8d间距保留即使较小的给定间隔a时,接触元件可以保持与ISO标准ISO 7810相一致的适当大的面积。

Claims (29)

1.芯片模块,含有一接触区(3)以及含有至少一个半导体芯片(6),接触区布置在其外侧(2)上,有许多基本上扁平的,相互绝缘的,导电材料组成的接触元件(4),半导体芯片含有一个或多个半导体集成电路,这些电路通过引线(8)与接触区(3)的接触元件(4)电学连接,其特征在于,芯片模块(1)的接触元件(4)由一预制的引线框架(20)(“Leadframe”)形成,用于支撑至少一个半导体芯片(6),并且形成在芯片模块(1)的至少两对边上,通过相互邻近排列布置的向外适配的引线(8)用于芯片模块(1)在外部印刷电路板或外部电路板基片(10)的安装表面(9)上的表面安装。
2.根据权利要求1所述的芯片模块,其特征在于,引线框架(20)的接触元件(4),用来形成可表面安装引线(8),是这样形成的,它们相互平行设置,并且相互间有一预定的距离,它们中心线间的该距离(a)对应于在外部印刷电路板或外部电路板基片(10)的安装表面(9)上形成的接线点的连接间隔(Anschlussraster),该连接间隔特别地为1.27mm。
3.根据权利要求1或2所述的芯片模块,其特征在于,用来形成可表面安装引线(8)的接触元件(4)配有一焊接附件(12),用于芯片模块(1)在外部印刷电路板或外部电路板基片(10)的安装表面(9)上的牢固连接。
4.根据权利要求3所述的芯片模块,其特征在于,可表面安装引线(8)的焊接附件(Loetansatz)(12)由一相对于接触元件(4)的平面横向设置的一间距保持器形成。
5.根据权利要求2至4之一所述的芯片模块,其特征在于,基本上长方形设计的可表面安装引线(8)的宽度稍小于连接间隔。
6.根据权利要求1至5之一所述的芯片模块,其特征在于,规定有一电学上绝缘材料的,至少盖住半导体芯片(6)的芯片封装(13)。
7.根据权利要求6所述的芯片模块,其特征在于,引线框架(20)的向外适配的可表面安装引线(8)沿安装平面(14)的方向延伸至芯片封装(13)外。
8.根据权利要求1至7之一所述的芯片模块,其特征在于,接触区(3)的接触元件(4),用于电信号或数据至一外部阅读/写入站的有触点的传输,在布置和尺寸上符合为具有触点的芯片卡设置的ISO标准细则,特别是根据ISO 7810的细则。
9.根据权利要求3至8之一所述的芯片模块,其特征在于,焊接附件(12)由一凹陷(17)或一开孔(18)形成,提供在向外适配的接触元件(4)的面向电路板安装表面(9)的一侧。
10.根据权利要求3至8之一所述的芯片模块,其特征在于,焊接附件(12)形成配有相应切口(16a)的向外适配的接触元件(4)的多角形状(16)。
11.根据权利要求1至10之一所述的芯片模块,其特征在于,焊接附件由一高出芯片封装(13)整个高度的适配物(19)形成。
12.根据权利要求1至11之一所述的芯片模块,其特征在于,预制引线框架(20)在其面向半导体芯片(6)的表面有一绝缘膜,该绝缘膜在焊接附件(12)的范围内和/或在连接引线(8)的范围内,配有开孔(22a,22b)。
13.根据权利要求3至12之一所述的芯片模块,其特征在于,芯片封装(13)有一增强框架(23),它包围半导体芯片(6)并被覆盖半导体芯片(6)的电学上绝缘覆层化合物封闭。
14.根据权利要求3至12之一所述的芯片模块,其特征在于,芯片封装(13)由整个盖住半导体芯片(6)和/或连接引线的覆层化合物形成。
15.制造一种芯片模块的方法,芯片模块含有一接触区(3)以及含有至少一个半导体芯片(6),接触区布置在其外侧(2)上,有许多基本上扁平的,相互绝缘的,导电材料组成的接触元件(4),半导体芯片含有一个或多个半导体集成电路,这些电路通过引线(8)与接触区(3)的接触元件(4)电学上连接,其特征在于,芯片模块(1)的接触元件(4)由一预制的引线框架(20)形成,用于支撑至少一个半导体芯片(6),并且形成在芯片模块(1)的至少两对边上,通过相互邻近排列布置的向外适配的引线(8)用于芯片模块(1)在外部印刷电路板或外部电路板基片(10)的安装表面(9)上的表面安装。
16.根据权利要求15所述的方法,其特征在于,引线框架(20)的接触元件(4),用来形成可表面安装引线(8),是这样形成的,它们相互平行设置,并且相互间有一预定的距离,它们中心线间的该距离(a)对应于形成在外部印刷电路板或外部电路板基片(10)的安装表面(9)上的接线点的连接间隔,该连接间隔特别地为1.27mm。
17.根据权利要求15或16所述的方法,其特征在于,用来形成可表面安装引线(8)的接触元件(4)配有一焊接附件(12),用于芯片模块(1)在外部印刷电路板或外部电路板基片(10)的安装表面(9)上的牢固连接。
18.根据权利要求17所述的方法,其特征在于,可表面安装引线(8)的焊接附件(12)由一相对于接触元件(4)的平面横向设置的一间距保持器形成。
19.根据权利要求15至18之一所述的方法,其特征在于,基本上长方形设计的可表面安装引线(8)的宽度稍小于连接间隔。
20.根据权利要求15至18之一所述的方法,其特征在于,规定有一电学上绝缘材料的,盖住至少半导体芯片(6)的芯片封装(13)。
21.根据权利要求17至20之一所述的方法,其特征在于,引线框架(20)的向外适配的可表面安装引线(8)沿安装平面(14)的方向延伸至芯片封装(13)外。
22.根据权利要求17至21之一所述的方法,其特征在于,焊接附件(12)由一高出芯片封装(13)整个高度的适配物形成。
23.根据权利要求17至22之一所述的方法,其特征在于,焊接附件(12)由一凹陷(17),采用刻蚀方法,或一开孔,采用冲孔或刻蚀方法,形成,提供在向外适配的接触元件(4)的面向电路板安装表面(9)的一侧。
24.根据权利要求18至23之一所述的方法,其特征在于,预制引线框架(20)在其面向半导体芯片(6)的表面有一绝缘膜,绝缘膜在焊接附件(12)的范围内和/或在连接引线(8)的范围内,配有开孔(22a,22b)。
25.根据权利要求17至24之一所述的方法,其特征在于,芯片封装(13)有一增强框架(23),它包围半导体芯片(6)并被覆盖半导体芯片(6)的电学上绝缘覆层化合物封闭。
26.根据权利要求17至24之一所述的方法,其特征在于,芯片封装(13)由整个盖住半导体芯片(6)和/或连接引线(8)的覆层化合物形成。
27.使用根据权利要求1至14之一所述的芯片模块(1)来制造芯片卡或类似数据载体。
28.芯片卡,以至少一个根据权利要求1至14之一所述的芯片模块(1)为特征。
29.在外部印刷电路板上或中,或在外部电路板基片(10)上或中使用根据权利要求1至14之一所述的芯片模块(1)。
CN97180008A 1996-09-23 1997-08-21 芯片模块及制造芯片模块的方法 Pending CN1238856A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19639025A DE19639025C2 (de) 1996-09-23 1996-09-23 Chipmodul und Verfahren zur Herstellung eines Chipmoduls
DE19639025.7 1996-09-23

Publications (1)

Publication Number Publication Date
CN1238856A true CN1238856A (zh) 1999-12-15

Family

ID=7806627

Family Applications (1)

Application Number Title Priority Date Filing Date
CN97180008A Pending CN1238856A (zh) 1996-09-23 1997-08-21 芯片模块及制造芯片模块的方法

Country Status (11)

Country Link
US (1) US6313524B1 (zh)
EP (1) EP0948815B1 (zh)
JP (1) JP2000505242A (zh)
KR (1) KR100363296B1 (zh)
CN (1) CN1238856A (zh)
AT (1) ATE213359T1 (zh)
BR (1) BR9712107A (zh)
DE (2) DE19639025C2 (zh)
RU (1) RU2165660C2 (zh)
UA (1) UA57033C2 (zh)
WO (1) WO1998013870A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100521470C (zh) * 2003-05-12 2009-07-29 西铁城电子股份有限公司 表面安装型电源电路装置及其制造方法
CN101012330B (zh) * 2006-01-30 2011-07-27 瑞萨电子株式会社 光学半导体封止用透明环氧树脂组合物和使用该组合物的光学半导体集成电路器件

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19541072A1 (de) * 1995-11-03 1997-05-07 Siemens Ag Chipmodul
EP1009023A1 (de) * 1998-12-09 2000-06-14 ESEC Management SA Verfahren zur Verbindung von zwei Leiterstrukturen und Kunststoffobjekt
FR2798000B1 (fr) * 1999-08-27 2002-04-05 St Microelectronics Sa Procede de mise en boitier d'une puce a capteurs en particulier optiques et dispositif semi-conducteur ou boitier renfermant une telle puce
US7102892B2 (en) 2000-03-13 2006-09-05 Legacy Electronics, Inc. Modular integrated circuit chip carrier
US6713854B1 (en) 2000-10-16 2004-03-30 Legacy Electronics, Inc Electronic circuit module with a carrier having a mounting pad array
FR2808608A1 (fr) * 2000-05-03 2001-11-09 Schlumberger Systems & Service Carte a memoire electronique destinee a etre introduite dans un dispositif de traitement
US7337522B2 (en) 2000-10-16 2008-03-04 Legacy Electronics, Inc. Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips
EP1378152A4 (en) * 2001-03-14 2006-02-01 Legacy Electronics Inc METHOD AND DEVICE FOR PREPARING A PCB WITH A THREE-DIMENSIONAL ARRAY OF SEMICONDUCTOR CHIPS USED ON THE SURFACE
JP2003100980A (ja) * 2001-09-27 2003-04-04 Hamamatsu Photonics Kk 半導体装置及びその製造方法
FR2831718B1 (fr) * 2001-10-31 2004-09-24 Gemplus Card Int Raccordement electrique male d'un plot de connexion d'une puce a une interface de communication, notamment pour objet portable intelligent tel qu'une carte a puce
DE10208168C1 (de) * 2002-02-26 2003-08-14 Infineon Technologies Ag Datenträgerkarte
JP4303699B2 (ja) * 2002-04-01 2009-07-29 パナソニック株式会社 半導体装置およびその製造方法
DE10303740B4 (de) * 2003-01-30 2006-09-14 Infineon Technologies Flash Gmbh & Co. Kg Sicherheitsspeicherkarte und Herstellungsverfahren
DE10325566A1 (de) * 2003-06-05 2005-01-13 Infineon Technologies Ag Chipkartenmodul
DE10350699B3 (de) 2003-10-30 2005-06-30 Rehm Anlagenbau Gmbh Verfahren und Vorrichtung zum Aufschmelzlöten mit Volumenstromsteuerung
US20100140627A1 (en) * 2005-01-10 2010-06-10 Shelton Bryan S Package for Semiconductor Devices
WO2006076381A2 (en) 2005-01-12 2006-07-20 Legacy Electronics, Inc. Radial circuit board, system, and methods
US8030746B2 (en) * 2008-02-08 2011-10-04 Infineon Technologies Ag Integrated circuit package
WO2009104303A1 (ja) 2008-02-22 2009-08-27 凸版印刷株式会社 トランスポンダ及び冊子体
US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
USD703208S1 (en) 2012-04-13 2014-04-22 Blackberry Limited UICC apparatus
USD701864S1 (en) 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus
DE102013211117A1 (de) * 2013-06-14 2014-12-18 Robert Bosch Gmbh Trägerplatte für elektrische Schaltungen mit Abstandshaltern zur Montage von Bauteilen
FR3034552B1 (fr) * 2015-04-02 2017-05-05 Oberthur Technologies Module dual pour carte duale a microcircuit
DE102016110780A1 (de) 2016-06-13 2017-12-14 Infineon Technologies Austria Ag Chipkartenmodul und Verfahren zum Herstellen eines Chipkartenmoduls
EP3499560B1 (en) * 2017-12-15 2021-08-18 Infineon Technologies AG Semiconductor module and method for producing the same
US20220157671A1 (en) * 2020-11-13 2022-05-19 Cree, Inc. Packaged rf power device with pcb routing

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3517438A (en) * 1966-05-12 1970-06-30 Ibm Method of packaging a circuit module and joining same to a circuit substrate
DE3307704C2 (de) * 1983-03-04 1986-10-23 Brown, Boveri & Cie Ag, 6800 Mannheim Stromrichtermodul mit Befestigungslaschen
FR2579798B1 (fr) * 1985-04-02 1990-09-28 Ebauchesfabrik Eta Ag Procede de fabrication de modules electroniques pour cartes a microcircuits et modules obtenus selon ce procede
US4996411A (en) * 1986-07-24 1991-02-26 Schlumberger Industries Method of manufacturing a card having electronic memory and a card obtained by performing said method
JPH0831556B2 (ja) * 1987-02-20 1996-03-27 株式会社東芝 半導体装置用リードフレーム
JPS6450444U (zh) * 1987-09-22 1989-03-29
FR2645680B1 (fr) * 1989-04-07 1994-04-29 Thomson Microelectronics Sa Sg Encapsulation de modules electroniques et procede de fabrication
DE3912891A1 (de) * 1989-04-19 1990-11-08 Siemens Ag Montagevorrichtung zur kontaktierung und zum einbau eines integrierten schaltkreissystems fuer eine wertkarte
FR2659157B2 (fr) 1989-05-26 1994-09-30 Lemaire Gerard Procede de fabrication d'une carte dite carte a puce, et carte obtenue par ce procede.
JPH034543A (ja) * 1989-05-31 1991-01-10 Ricoh Co Ltd 半導体装置
JPH0324741A (ja) * 1989-06-21 1991-02-01 Toshiba Corp Tab用フイルムキャリア
EP0408904A3 (en) * 1989-07-21 1992-01-02 Motorola Inc. Surface mounting semiconductor device and method
JPH03241765A (ja) * 1990-02-20 1991-10-28 Matsushita Electron Corp 半導体装置
JP2756184B2 (ja) * 1990-11-27 1998-05-25 株式会社日立製作所 電子部品の表面実装構造
JPH0555438A (ja) * 1991-08-26 1993-03-05 Rohm Co Ltd 電子部品のリード端子構造
CH686462A5 (de) * 1992-11-27 1996-03-29 Esec Sempac Sa Elektronikmodul und Chip-Karte.
US5455740A (en) * 1994-03-07 1995-10-03 Staktek Corporation Bus communication system for stacked high density integrated circuit packages
US5474958A (en) * 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
US5367124A (en) * 1993-06-28 1994-11-22 International Business Machines Corporation Compliant lead for surface mounting a chip package to a substrate
JP3233507B2 (ja) * 1993-08-13 2001-11-26 株式会社東芝 半導体装置
DE4336501A1 (de) * 1993-10-26 1995-04-27 Giesecke & Devrient Gmbh Verfahren zur Herstellung von Ausweiskarten mit elektronischen Modulen
DE4431754C1 (de) * 1994-09-06 1995-11-23 Siemens Ag Trägerelement
US5541450A (en) * 1994-11-02 1996-07-30 Motorola, Inc. Low-profile ball-grid array semiconductor package
FR2734983B1 (fr) * 1995-05-29 1997-07-04 Sgs Thomson Microelectronics Utilisation d'un micromodule comme boitier de montage en surface et procede correspondant
JPH09260550A (ja) * 1996-03-22 1997-10-03 Mitsubishi Electric Corp 半導体装置
JP3779789B2 (ja) * 1997-01-31 2006-05-31 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US5869889A (en) * 1997-04-21 1999-02-09 Lsi Logic Corporation Thin power tape ball grid array package
US6122171A (en) * 1999-07-30 2000-09-19 Micron Technology, Inc. Heat sink chip package and method of making
US6184580B1 (en) * 1999-09-10 2001-02-06 Siliconware Precision Industries Co., Ltd. Ball grid array package with conductive leads
US6197614B1 (en) * 1999-12-20 2001-03-06 Thin Film Module, Inc. Quick turn around fabrication process for packaging substrates and high density cards

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100521470C (zh) * 2003-05-12 2009-07-29 西铁城电子股份有限公司 表面安装型电源电路装置及其制造方法
CN101012330B (zh) * 2006-01-30 2011-07-27 瑞萨电子株式会社 光学半导体封止用透明环氧树脂组合物和使用该组合物的光学半导体集成电路器件

Also Published As

Publication number Publication date
KR20000048549A (ko) 2000-07-25
DE19639025C2 (de) 1999-10-28
DE19639025A1 (de) 1998-04-02
WO1998013870A1 (de) 1998-04-02
BR9712107A (pt) 1999-08-31
US6313524B1 (en) 2001-11-06
EP0948815B1 (de) 2002-02-13
RU2165660C2 (ru) 2001-04-20
ATE213359T1 (de) 2002-02-15
KR100363296B1 (ko) 2002-11-30
JP2000505242A (ja) 2000-04-25
UA57033C2 (uk) 2003-06-16
DE59706411D1 (de) 2002-03-21
EP0948815A1 (de) 1999-10-13

Similar Documents

Publication Publication Date Title
CN1238856A (zh) 芯片模块及制造芯片模块的方法
CN1295645C (zh) 非接触式数据载体的制造方法
US7902652B2 (en) Semiconductor package and semiconductor system in package using the same
US7992790B2 (en) Method of producing a contactless microelectronic device, such as for an electronic passport
US20080283983A1 (en) Semiconductor device and manufacturing method thereof
CN1134064C (zh) 半导体芯片用的载体元件
US8408473B2 (en) Method for producing an RFID transponder product, and RFID transponder product produced using the method
CN101278383B (zh) 电子电路装置及其制造方法
KR20000075916A (ko) 스마트 카드 모듈 및 스마트 카드 모듈을 포함하는 스마트 카드
US20040256150A1 (en) Nonconducting substrate, forming a strip or a panel, on which a multiplicity of carrier elements are formed
JP4579924B2 (ja) デュアルインタフェースを有するカードの生産方法と同方法から得られたマイクロ回路カード
CN1555576A (zh) 电子标签及其制造方法
KR20010078385A (ko) 마이크로 트랜스폰더 제조방법
CN1213386C (zh) 便携式数据载体
US20110074005A1 (en) Semiconductor device, method for fabricating a semiconductor device and lead frame, comprising a bent contact section
CN113823608A (zh) 一种芯片组件及其制作方法
WO2012014005A1 (en) Rfid tag and method for manufacturing such a rfid tag
US6891254B2 (en) Semiconductor device with protrusions
EP1804202A1 (en) Tape carrier and module for contact type IC card and method for manufacturing the tape carrier
CN1788275A (zh) 用于将电子器件安装在基板上的方法
CN216084865U (zh) 一种芯片组件
CN1460291A (zh) 具有小回路高度的接线连接的片状模块
US20030043555A1 (en) Electronic component with at least two stacked semiconductor chips and process for producing the electronic component
MXPA99002697A (en) Chip module and manufacturing process
CN1208487A (zh) 用于制造一种含有线圈的芯片卡的芯片卡体

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
AD01 Patent right deemed abandoned
C20 Patent right or utility model deemed to be abandoned or is abandoned