WO2012014005A1 - Rfid tag and method for manufacturing such a rfid tag - Google Patents

Rfid tag and method for manufacturing such a rfid tag Download PDF

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Publication number
WO2012014005A1
WO2012014005A1 PCT/IB2010/002187 IB2010002187W WO2012014005A1 WO 2012014005 A1 WO2012014005 A1 WO 2012014005A1 IB 2010002187 W IB2010002187 W IB 2010002187W WO 2012014005 A1 WO2012014005 A1 WO 2012014005A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
rfid tag
connection ends
electronic chip
holes
Prior art date
Application number
PCT/IB2010/002187
Other languages
French (fr)
Inventor
Stéphane BARLERIN
Jean-Pierre Radenne
Original Assignee
Fci
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fci filed Critical Fci
Priority to PCT/IB2010/002187 priority Critical patent/WO2012014005A1/en
Publication of WO2012014005A1 publication Critical patent/WO2012014005A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07718—Constructional details, e.g. mounting of circuits in the carrier the record carrier being manufactured in a continuous process, e.g. using endless rolls
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07722—Physical layout of the record carrier the record carrier being multilayered, e.g. laminated sheets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2208—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems
    • H01Q1/2225—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems used in active tags, i.e. provided with its own power source or in passive tags, i.e. deriving power from RF signal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q7/00—Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10098—Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components

Definitions

  • the invention relates to an RFID (Radio Frequency Identification) tag and a "ready-to-use" endless RFID circuit tape.
  • RFID Radio Frequency Identification
  • endless intends to define a tape adapted for use in reel-to-reel processes, as opposed to substrate sheets for discontinuous processes and/or processes by batch.
  • the invention also relates to a method for
  • Radio Frequency Identification is becoming an important identification technology for tracking objects such as luggage, packages, merchandise, and the like through distribution networks and processes.
  • a typical RFID tag or transponder consists of a semiconductor chip having RF circuits, logic, and memory, an antenna (and a battery in the case of active tags) , mounted to a substrate. Such an RFID tag is capable to exchange information with a reader via its antenna.
  • a RFID tag which is adapted to work in harsh environment.
  • “harsh environment” relates to high temperature and/or corrosive and/or humid environment.
  • One example of the harsh applications is the tracking of manufacturing process of printed circuit boards in which a substrate is usually subjected to metallization and chemical etching steps; these steps being definitely harsh conditions in terms of temperature, corrosivity.
  • a RFID tag comprising a substrate layer 23 supporting an antenna pattern 24 which is electrically connected to an IC chip 25.
  • a protective glop-top material 26 In the area of IC chip, it is provided a protective glop-top material 26.
  • the tag also includes a laminated film 27 covering not only the substrate layer 23 but also the encapsulated IC chip 25.
  • such a RFID tag structure may present weak point located at the junction point between the substrate layer, the glob-top and the laminated film as shown by the circle of Fig. 1.
  • the prior art RFID tag may present performance failure due to, for instance, moisture and/or dust contamination through the layer stack.
  • the invention relates to a RFID tag according to claim 1 and a method for manufacturing such a RFID tag according to claim 8.
  • the RFID tag of the present invention can be produced by a "reel-to-reel" process which delivers benefits in terms of productivity and reliability. Since the implementation of a "reel-to-reel process implies the use of relatively flexible material, one may propose a thin flexible tag for applications in which the tag is exposed to bending and/or torsional actions.
  • a "ready-to-use" continuous (or endless) circuit tape of claim 10 it is proposed a "ready-to-use" continuous (or endless) circuit tape of claim 10.
  • the RFID tag manufacturer is able to manage his production line depending on the bookings on a daily basis, with reduce time out, i.e. the manufacturer only needs to change the endless tape and then proceed to the IC chip connection to shift to a different RFID tag part number.
  • Fig.l shows a partial cross sectional view of a prior art
  • Fig.2 shows a partial cross sectional view of an RFID tag according to the invention
  • Fig.3a shows a perspective view of an exemplary "ready-to- use" RFID tape comprising conductive pattern with a laminated cover layer tape prior to IC chip mounting;
  • Fig. 3b is a perspective view of the "ready-to-use" RFID circuit tape with an IC chip connected to the RFID circuit .
  • Fig.4 is a schematic process line.
  • Fig. 2 is an enlarged partial cross-sectional view of a RFID tag according to the present invention.
  • This RFID tag includes a support substrate 1 on which is formed conductive pattern 2 providing an electrical circuit of an antenna.
  • the support substrate is made of insulating material, preferably made of a flexible high temperature polymer.
  • the flexible material may be chosen a polyimide film.
  • the circuit pattern 2 is formed onto the upper surface of the support substrate 1 by plating, by printing, by etching, by chemical deposition, etc...
  • the conductive material of the circuit pattern may be chosen among silver, copper, aluminium, etc..
  • the circuit pattern forms either a HF or an UHF antenna pattern .
  • the RFID tag further comprises an IC chip 3 electrically connected to the first and second connection ends of the circuit pattern.
  • the IC chip is connected to the circuit pattern connection ends by a wire bonding technique implementing conductive leads (for instance silver, gold or copper) .
  • conductive leads for instance silver, gold or copper
  • the IC chip may be also directly attached to the antenna circuit by flip-chip technology or by implementing IC chips provided with SMT (Surface Mount) contact (e.g. SOT type Chip) which are directly soldered to the antenna pads.
  • SMT Surface Mount
  • the RFID tag according to the invention further includes a cover layer 5, provided with a through-hole 6, which has been attached on top of the upper surface of the support substrate 1 so as to overlay the circuit pattern and thereby protecting it from external environment.
  • the through-hole 6 is located at a position in respect to the circuit pattern so as to give an access to the antenna connection end 6', 6" for connecting the IC chip 3. Finally the through-hole 6 is filled with an encapsulation material or glob-top material 7, the purpose of which is to isolate the IC chip 3 from external environment and to provide mechanical reinforcement.
  • the cover layer 5 is a flexible film of high temperature polymer type provided with an adhesive means 5' .
  • the flexible film is laminated over the upper surface of the substrate and is firmly fixed to it via the adhesive means 5' .
  • the flexible film is about 75ym thick.
  • the substrate and the cover layer are flexible material, i.e. the material is flexible enough to withstand flexure force without permanent deformation or breaking.
  • the substrate and the cover layer can be implemented in a high speed line using a "reel-to-reel" technology. Further providing an encapsulation material in replacement of a laminated cover layer in the IC chip area highly reduces risk of air bubble formation which may impart attachment of the cover layer to the substrate over a period of use.
  • Fig. 3a is a schematic representation of the lamination step of the manufacturing process of the RFID tag, in which a cover layer tape 11 is applied over the upper surface of the substrate tape 9.
  • the substrate tape 9 has been beforehand plated with a metallic layer to provide a circuit pattern 2.
  • an electrically conductive ink which behaves as a priming electrically conductive layer, is applied to the substrate tape.
  • the application of the conductive ink can be performed by gravure printing or screen printing to constitute a primary circuit pattern.
  • the substrate tape is put into contact with an electro-plating bath comprising the metallic ions to be deposited by an electro- reduction reaction.
  • the reduction reaction is achieved by applying a current or a voltage between an anode (for instance a soluble anode of the metal to be deposited) and a cathode.
  • connection bridge 8 The cathode of the electrochemical cell is electrically connected to the priming conductive ink through a connection bridge 8.
  • the circuit pattern 2 is centrally disposed in respect to the edges of the substrate tape and when the cathode is located on at one edge of the substrate, it is necessary to provide a connection bridge 8 extending from the edge towards the centrally positioned circuit pattern.
  • connection bridge 8 comprises a corrugated profile (not shown) .
  • the connection bridge 8 comprises a corrugated profile (not shown) .
  • the corrugated profile minimises the length of the path from the edge of the substrate to the circuit pattern, with the benefit that the time required for reaching the circuit pattern 2 is also increased, thereby improving the product lifetime further to liquid contamination .
  • Fig. 3b shows the RFID tape with an IC chip 3 positioned through the through-hole and electrically connected to the antenna circuit pattern.
  • a tape of flexible support substrate 9 with its circuit patterns is unwound from roll 10.
  • a cover tape 11 of flexible material is unwounded from roll 12.
  • the cover tape 11 is provided with an adhesive film (not shown), covered by a protective film 14, over a first surface 13.
  • the protective film 14 is removed from the cover tape 11 and wound on roll 15.
  • the cover tape 11 is subjected to a "stamping" unit 16 wherein through-holes (not shown) are formed.
  • the cover tape 11 and the substrate tape 9 are subsequently laminated so as to glue both parts together to form a layered tape.
  • the resulting tape is submitted to a "die attach" unit 17 in which an IC chip is put in place in the through-hole of the layered tape.
  • the IC chip is then electrically connected to the circuit pattern for instance in a "wire bonding" unit 18.
  • the circuit tape with its IC chips is brought into a "casting" unit 19 in which a glob top material is cast in order to fill up the through-holes. During casting, the walls formed by the through-holes serve as a limiting frame for the glob-top material so as to prevent material overflow.
  • the resulting cast layered tape is subsequently submitted to a "Curing" unit 20 to harden the glob-top material.
  • the finalized tape 21 is then either wound onto roll 22 or immediately processed, for instance by stamping, to provide individualized RFID tags.
  • the tape obtained just before being submitted to the "die attach" unit 17 is wound on a roll (and possibly sold as such) for a subsequent mounting of the chip 3.
  • the RFID tag according to the present invention is therefore of simple construction which is especially adapted to be manufactured through a reel-to-reel process.
  • a RFID tag product in which the constituents are intimately associated, is fabricated via the above-mentioned process. Such an intimate structure is beneficial for proposing a harsh environment RFID tag.

Abstract

The present invention relates to an RFID tag comprising a substrate (1). A plurality of conductive patterns (2) is formed onto a first surface of the substrate (1). Each conductive pattern has at least a first and a second connection ends. An electronic chip (3) is electrically connected the first and the second connection ends. Laminated cover layer overlays the conductive patterns. The cover layer is provided with through-holes (6) of a dimension larger than the electronic chip (3) so as to expose the electronic chip. The through-holes (6) are filled with an encapsulation material (7).

Description

RFID TAG AND METHOD FOR MANUFACTURING SUCH A RFID TAG
Field of the invention
The invention relates to an RFID (Radio Frequency Identification) tag and a "ready-to-use" endless RFID circuit tape. In this document, "endless" intends to define a tape adapted for use in reel-to-reel processes, as opposed to substrate sheets for discontinuous processes and/or processes by batch.
The invention also relates to a method for
manufacturing such a RFID tag and the endless RFID circuit tape .
Description of prior art
Radio Frequency Identification (RFID) is becoming an important identification technology for tracking objects such as luggage, packages, merchandise, and the like through distribution networks and processes.
A typical RFID tag or transponder consists of a semiconductor chip having RF circuits, logic, and memory, an antenna (and a battery in the case of active tags) , mounted to a substrate. Such an RFID tag is capable to exchange information with a reader via its antenna.
There is still a demand for RFID tag which is adapted to work in harsh environment. In the context of the present invention "harsh environment" relates to high temperature and/or corrosive and/or humid environment. One example of the harsh applications is the tracking of manufacturing process of printed circuit boards in which a substrate is usually subjected to metallization and chemical etching steps; these steps being definitely harsh conditions in terms of temperature, corrosivity. It is known from the international application WO 2008/132287 (Fig. 1), a RFID tag comprising a substrate layer 23 supporting an antenna pattern 24 which is electrically connected to an IC chip 25. In the area of IC chip, it is provided a protective glop-top material 26. The tag also includes a laminated film 27 covering not only the substrate layer 23 but also the encapsulated IC chip 25.
Although functionally valid, such a RFID tag structure may present weak point located at the junction point between the substrate layer, the glob-top and the laminated film as shown by the circle of Fig. 1. In use, over a period of time, the prior art RFID tag may present performance failure due to, for instance, moisture and/or dust contamination through the layer stack.
Summary of the invention
It is therefore an object of the invention to provide an improved RFID tag, which is adapted to work in harsh environment over a large period of time and which is less expensive to manufacture with regard to the prior art RFID tags .
To this end, the invention relates to a RFID tag according to claim 1 and a method for manufacturing such a RFID tag according to claim 8.
Thus, by providing a laminated cover layer, on top of the conductive pattern, having a small through-hole (of substantially the size of the IC chip) , it is possible to form an intimately-attached layered tag assembly by lamination process. This provides a layer stack structure for which risk of detachment of the cover layer from the substrate, due to the presence of weak sticking points, is reduced . Further the RFID tag of the present invention can be produced by a "reel-to-reel" process which delivers benefits in terms of productivity and reliability. Since the implementation of a "reel-to-reel process implies the use of relatively flexible material, one may propose a thin flexible tag for applications in which the tag is exposed to bending and/or torsional actions.
According to another aspect of the invention, it is proposed a "ready-to-use" continuous (or endless) circuit tape of claim 10. With the present endless circuit tape, the RFID tag manufacturer is able to manage his production line depending on the bookings on a daily basis, with reduce time out, i.e. the manufacturer only needs to change the endless tape and then proceed to the IC chip connection to shift to a different RFID tag part number.
Short description of the drawings
These and further aspects of the invention will be explained in greater detail by way of example and with reference to the accompanying drawings in which:
Fig.l shows a partial cross sectional view of a prior art
RFID tag;
Fig.2 shows a partial cross sectional view of an RFID tag according to the invention;
Fig.3a shows a perspective view of an exemplary "ready-to- use" RFID tape comprising conductive pattern with a laminated cover layer tape prior to IC chip mounting;
Fig. 3b is a perspective view of the "ready-to-use" RFID circuit tape with an IC chip connected to the RFID circuit . Fig.4 is a schematic process line.
The figures are not drawn to scale. Generally, identical components are denoted by the same reference numerals in the figures.
Detailed description of preferred embodiments
Fig. 2 is an enlarged partial cross-sectional view of a RFID tag according to the present invention. This RFID tag includes a support substrate 1 on which is formed conductive pattern 2 providing an electrical circuit of an antenna. The support substrate is made of insulating material, preferably made of a flexible high temperature polymer. For instance, the flexible material may be chosen a polyimide film.
The circuit pattern 2 is formed onto the upper surface of the support substrate 1 by plating, by printing, by etching, by chemical deposition, etc... The conductive material of the circuit pattern may be chosen among silver, copper, aluminium, etc.. According to the present invention, the circuit pattern forms either a HF or an UHF antenna pattern .
The RFID tag further comprises an IC chip 3 electrically connected to the first and second connection ends of the circuit pattern. As shown in Fig. 2, the IC chip is connected to the circuit pattern connection ends by a wire bonding technique implementing conductive leads (for instance silver, gold or copper) . It should be noted that the IC chip may be also directly attached to the antenna circuit by flip-chip technology or by implementing IC chips provided with SMT (Surface Mount) contact (e.g. SOT type Chip) which are directly soldered to the antenna pads. The RFID tag according to the invention further includes a cover layer 5, provided with a through-hole 6, which has been attached on top of the upper surface of the support substrate 1 so as to overlay the circuit pattern and thereby protecting it from external environment. The through-hole 6 is located at a position in respect to the circuit pattern so as to give an access to the antenna connection end 6', 6" for connecting the IC chip 3. Finally the through-hole 6 is filled with an encapsulation material or glob-top material 7, the purpose of which is to isolate the IC chip 3 from external environment and to provide mechanical reinforcement.
According to a preferred embodiment, the cover layer 5 is a flexible film of high temperature polymer type provided with an adhesive means 5' . The flexible film is laminated over the upper surface of the substrate and is firmly fixed to it via the adhesive means 5' . For instance the flexible film is about 75ym thick.
As previously-mentioned, the substrate and the cover layer are flexible material, i.e. the material is flexible enough to withstand flexure force without permanent deformation or breaking. By virtue to the fact of their flexibility, the substrate and the cover layer can be implemented in a high speed line using a "reel-to-reel" technology. Further providing an encapsulation material in replacement of a laminated cover layer in the IC chip area highly reduces risk of air bubble formation which may impart attachment of the cover layer to the substrate over a period of use.
Fig. 3a is a schematic representation of the lamination step of the manufacturing process of the RFID tag, in which a cover layer tape 11 is applied over the upper surface of the substrate tape 9. The substrate tape 9 has been beforehand plated with a metallic layer to provide a circuit pattern 2.
Now is described an exemplary way, among other available technique, to form the conductive circuit pattern 2 onto the substrate tape 1. In a first step, an electrically conductive ink, which behaves as a priming electrically conductive layer, is applied to the substrate tape. The application of the conductive ink can be performed by gravure printing or screen printing to constitute a primary circuit pattern. In subsequent step, the substrate tape is put into contact with an electro-plating bath comprising the metallic ions to be deposited by an electro- reduction reaction. The reduction reaction is achieved by applying a current or a voltage between an anode (for instance a soluble anode of the metal to be deposited) and a cathode. The cathode of the electrochemical cell is electrically connected to the priming conductive ink through a connection bridge 8. As shown in Fig. 3a, the circuit pattern 2 is centrally disposed in respect to the edges of the substrate tape and when the cathode is located on at one edge of the substrate, it is necessary to provide a connection bridge 8 extending from the edge towards the centrally positioned circuit pattern.
Advantageously, the connection bridge 8 comprises a corrugated profile (not shown) . Thus in the event where undesired liquid soaks between the substrate 1 and the cover layer 5, the liquid will preferentially follow the path defined along the connection bridge 6. Thanks to the corrugated profile, the length of the path from the edge of the substrate to the circuit pattern is substantially increased, with the benefit that the time required for reaching the circuit pattern 2 is also increased, thereby improving the product lifetime further to liquid contamination .
Fig. 3b shows the RFID tape with an IC chip 3 positioned through the through-hole and electrically connected to the antenna circuit pattern.
In reference to Fig. 4, is described a possible process line for manufacturing a RFID tag according to the invention. A tape of flexible support substrate 9 with its circuit patterns is unwound from roll 10. Parallel to this step, a cover tape 11 of flexible material is unwounded from roll 12. The cover tape 11 is provided with an adhesive film (not shown), covered by a protective film 14, over a first surface 13. The protective film 14 is removed from the cover tape 11 and wound on roll 15. After protective film removal, the cover tape 11 is subjected to a "stamping" unit 16 wherein through-holes (not shown) are formed. The cover tape 11 and the substrate tape 9 are subsequently laminated so as to glue both parts together to form a layered tape. The resulting tape is submitted to a "die attach" unit 17 in which an IC chip is put in place in the through-hole of the layered tape. The IC chip is then electrically connected to the circuit pattern for instance in a "wire bonding" unit 18. The circuit tape with its IC chips is brought into a "casting" unit 19 in which a glob top material is cast in order to fill up the through-holes. During casting, the walls formed by the through-holes serve as a limiting frame for the glob-top material so as to prevent material overflow. The resulting cast layered tape is subsequently submitted to a "Curing" unit 20 to harden the glob-top material. The finalized tape 21 is then either wound onto roll 22 or immediately processed, for instance by stamping, to provide individualized RFID tags.
According to a variant of the above described process, the tape obtained just before being submitted to the "die attach" unit 17 is wound on a roll (and possibly sold as such) for a subsequent mounting of the chip 3.
The RFID tag according to the present invention is therefore of simple construction which is especially adapted to be manufactured through a reel-to-reel process. In addition, a RFID tag product, in which the constituents are intimately associated, is fabricated via the above-mentioned process. Such an intimate structure is beneficial for proposing a harsh environment RFID tag.
The present invention has been described in terms of specific embodiments, which are illustrative of the invention and not to be construed as limiting.

Claims

1. RFID tag comprising:
- a substrate;
- a conductive pattern formed onto a first surface of the substrate and having at least a first and a second connection ends;
- an electronic chip electrically connected the first and the second connection ends;
- a laminated cover layer overlaying the conductive pattern;
wherein the cover layer is provided with a through-hole of a dimension larger than the electronic chip so as to expose the electronic chip and wherein the through-hole is filled with an encapsulation material.
2. RFID tag according to claim 1, wherein the electronic chip is electrically connected to the first and the second connection free ends by wire-bonding.
3. RFID tag according to claim 1 or 2, wherein the cover member is attached to the first surface of the substrate with an adhesive material.
4. RFID tag according to any preceding claims, wherein the substrate, the cover member and the encapsulation material are chosen among high temperature polymers .
5. RFID tag according to claim 4, wherein the high temperature polymers have a glass transition temperature above 300 °C.
6. RFID tag according to any preceding claims, wherein the conductive pattern forms an UHF or HF antenna.
7. RFID tag according to any preceding claims, wherein the cover member comprises an adhesive layer on a surface opposite to that one facing the first surface of the substrate .
8. Reel-to-reel method for manufacturing an RFID tag web comprising the following steps:
a) providing a continuous web of substrate having a plurality of conductive patterns, each one of which comprising a first and a second free connection ends and being formed on a first surface of the substrate;
b) laminating a cover web having through-holes over the conductive patterns so that the first and the second free connection ends are exposed through the through-holes;
c) electrically connecting an electronic chip to the first and a second free connection ends so that the electronic chip is received in the through- hole;
d) encapsulating the through-holes with an encapsulating material.
9. Reel-to-reel method for manufacturing a continuous RFID tape comprising the following steps:
a) providing a continuous web of substrate having a plurality of conductive patterns, each one of which comprising a first and a second free connection ends and being formed on a first surface of the substrate;
b) laminating a cover web having through-holes over the conductive pattern such that the first and the second free connection ends are exposed through the through-holes.
10. Continuous RFID tape comprising:
- a substrate;
- a plurality conductive patterns formed onto a first surface of the substrate and each one of which having at least a first and a second connection ends;
- a laminated cover layer overlaying the conductive patterns ;
wherein the cover layer is provided with through-holes, each one of which, exposing the first and the second connection ends and being sized to receive an IC chip.
PCT/IB2010/002187 2010-07-26 2010-07-26 Rfid tag and method for manufacturing such a rfid tag WO2012014005A1 (en)

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WO2015043626A1 (en) 2013-09-25 2015-04-02 Prowerb Ag Spacer for spacing glass panes of a multi-glazed window, multi-glazed window, vapour barrier film for a spacer, method for producing a vapour barrier film, and method for producing a spacer
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