CN1225019C - 防止化学机械抛光中的凹陷和侵蚀的半导体器件制造方法 - Google Patents

防止化学机械抛光中的凹陷和侵蚀的半导体器件制造方法 Download PDF

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Publication number
CN1225019C
CN1225019C CNB031064248A CN03106424A CN1225019C CN 1225019 C CN1225019 C CN 1225019C CN B031064248 A CNB031064248 A CN B031064248A CN 03106424 A CN03106424 A CN 03106424A CN 1225019 C CN1225019 C CN 1225019C
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China
Prior art keywords
dielectric film
wiring layer
layer
insulating film
wiring
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Expired - Fee Related
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CNB031064248A
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English (en)
Chinese (zh)
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CN1467817A (zh
Inventor
宫嶋基守
柄沢章孝
细田勉
大塚敏志
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Fujitsu Semiconductor Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CNB031064248A 2002-06-07 2003-02-25 防止化学机械抛光中的凹陷和侵蚀的半导体器件制造方法 Expired - Fee Related CN1225019C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002166621A JP4076131B2 (ja) 2002-06-07 2002-06-07 半導体装置の製造方法
JP166621/2002 2002-06-07

Publications (2)

Publication Number Publication Date
CN1467817A CN1467817A (zh) 2004-01-14
CN1225019C true CN1225019C (zh) 2005-10-26

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CNB031064248A Expired - Fee Related CN1225019C (zh) 2002-06-07 2003-02-25 防止化学机械抛光中的凹陷和侵蚀的半导体器件制造方法

Country Status (5)

Country Link
US (1) US6686285B2 (enExample)
JP (1) JP4076131B2 (enExample)
KR (1) KR100814234B1 (enExample)
CN (1) CN1225019C (enExample)
TW (1) TWI224536B (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004253791A (ja) 2003-01-29 2004-09-09 Nec Electronics Corp 絶縁膜およびそれを用いた半導体装置
US7217649B2 (en) * 2003-03-14 2007-05-15 Lam Research Corporation System and method for stress free conductor removal
JP2006165214A (ja) * 2004-12-07 2006-06-22 Sony Corp 半導体装置およびその製造方法
KR100711912B1 (ko) * 2005-12-28 2007-04-27 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 형성 방법
JP4231055B2 (ja) * 2006-02-06 2009-02-25 株式会社東芝 半導体装置及びその製造方法
JP2007251135A (ja) * 2006-02-18 2007-09-27 Seiko Instruments Inc 半導体装置およびその製造方法
JP2007294514A (ja) * 2006-04-21 2007-11-08 Renesas Technology Corp 半導体装置
US8193087B2 (en) 2006-05-18 2012-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Process for improving copper line cap formation
JP2010171064A (ja) * 2009-01-20 2010-08-05 Panasonic Corp 半導体装置及びその製造方法
JP2012064713A (ja) * 2010-09-15 2012-03-29 Toshiba Corp 半導体装置の製造方法
US11862607B2 (en) * 2021-08-16 2024-01-02 Micron Technology, Inc. Composite dielectric structures for semiconductor die assemblies and associated systems and methods

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FR2630588A1 (fr) * 1988-04-22 1989-10-27 Philips Nv Procede pour realiser une configuration d'interconnexion sur un dispositif semiconducteur notamment un circuit a densite d'integration elevee
KR100238220B1 (en) * 1996-12-17 2000-01-15 Samsung Electronics Co Ltd Plattening method of semiconductor device
US6140226A (en) * 1998-01-16 2000-10-31 International Business Machines Corporation Dual damascene processing for semiconductor chip interconnects
US6420261B2 (en) * 1998-08-31 2002-07-16 Fujitsu Limited Semiconductor device manufacturing method
US6150272A (en) * 1998-11-16 2000-11-21 Taiwan Semiconductor Manufacturing Company Method for making metal plug contacts and metal lines in an insulating layer by chemical/mechanical polishing that reduces polishing-induced damage
KR100292409B1 (ko) * 1999-05-24 2001-06-01 윤종용 실리콘-메틸 결합을 함유하는 절연층을 포함하는 다층 구조의 절연막 및 그 형성방법
JP2001144086A (ja) * 1999-08-31 2001-05-25 Sony Corp 埋め込み配線の形成方法、及び、基体処理装置
US7041599B1 (en) * 1999-12-21 2006-05-09 Applied Materials Inc. High through-put Cu CMP with significantly reduced erosion and dishing
US6380003B1 (en) * 1999-12-22 2002-04-30 International Business Machines Corporation Damascene anti-fuse with slot via
US6503827B1 (en) * 2000-06-28 2003-01-07 International Business Machines Corporation Method of reducing planarization defects
JP3917355B2 (ja) * 2000-09-21 2007-05-23 株式会社東芝 半導体装置およびその製造方法
US20020064951A1 (en) * 2000-11-30 2002-05-30 Eissa Mona M. Treatment of low-k dielectric films to enable patterning of deep submicron features
US6432811B1 (en) * 2000-12-20 2002-08-13 Intel Corporation Method of forming structural reinforcement of highly porous low k dielectric films by Cu diffusion barrier structures
US6583047B2 (en) * 2000-12-26 2003-06-24 Honeywell International, Inc. Method for eliminating reaction between photoresist and OSG
JP4160277B2 (ja) * 2001-06-29 2008-10-01 株式会社東芝 半導体装置の製造方法
US6562725B2 (en) * 2001-07-05 2003-05-13 Taiwan Semiconductor Manufacturing Co., Ltd Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers
KR100442863B1 (ko) * 2001-08-01 2004-08-02 삼성전자주식회사 금속-절연체-금속 커패시터 및 다마신 배선 구조를 갖는반도체 소자의 제조 방법
JP4131786B2 (ja) * 2001-09-03 2008-08-13 株式会社東芝 半導体装置の製造方法およびウエハ構造体
US6440840B1 (en) * 2002-01-25 2002-08-27 Taiwan Semiconductor Manufactoring Company Damascene process to eliminate copper defects during chemical-mechanical polishing (CMP) for making electrical interconnections on integrated circuits
US6531386B1 (en) * 2002-02-08 2003-03-11 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dish-free copper interconnects

Also Published As

Publication number Publication date
JP4076131B2 (ja) 2008-04-16
KR100814234B1 (ko) 2008-03-17
CN1467817A (zh) 2004-01-14
JP2004014828A (ja) 2004-01-15
US6686285B2 (en) 2004-02-03
TW200307589A (en) 2003-12-16
TWI224536B (en) 2004-12-01
KR20030095189A (ko) 2003-12-18
US20030228765A1 (en) 2003-12-11

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