KR100814234B1 - 반도체 장치의 제조 방법 - Google Patents

반도체 장치의 제조 방법 Download PDF

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Publication number
KR100814234B1
KR100814234B1 KR1020030000520A KR20030000520A KR100814234B1 KR 100814234 B1 KR100814234 B1 KR 100814234B1 KR 1020030000520 A KR1020030000520 A KR 1020030000520A KR 20030000520 A KR20030000520 A KR 20030000520A KR 100814234 B1 KR100814234 B1 KR 100814234B1
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KR
South Korea
Prior art keywords
insulating film
layer
wiring
wiring layer
polishing
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Expired - Fee Related
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KR1020030000520A
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English (en)
Korean (ko)
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KR20030095189A (ko
Inventor
미야지마모또슈
가라사와도시유끼
호소다쯔또무
오쯔까사또시
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후지쯔 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020030000520A 2002-06-07 2003-01-06 반도체 장치의 제조 방법 Expired - Fee Related KR100814234B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2002-00166621 2002-06-07
JP2002166621A JP4076131B2 (ja) 2002-06-07 2002-06-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
KR20030095189A KR20030095189A (ko) 2003-12-18
KR100814234B1 true KR100814234B1 (ko) 2008-03-17

Family

ID=29706730

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020030000520A Expired - Fee Related KR100814234B1 (ko) 2002-06-07 2003-01-06 반도체 장치의 제조 방법

Country Status (5)

Country Link
US (1) US6686285B2 (enExample)
JP (1) JP4076131B2 (enExample)
KR (1) KR100814234B1 (enExample)
CN (1) CN1225019C (enExample)
TW (1) TWI224536B (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004253791A (ja) * 2003-01-29 2004-09-09 Nec Electronics Corp 絶縁膜およびそれを用いた半導体装置
US7217649B2 (en) * 2003-03-14 2007-05-15 Lam Research Corporation System and method for stress free conductor removal
JP2006165214A (ja) * 2004-12-07 2006-06-22 Sony Corp 半導体装置およびその製造方法
KR100711912B1 (ko) * 2005-12-28 2007-04-27 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 형성 방법
JP4231055B2 (ja) * 2006-02-06 2009-02-25 株式会社東芝 半導体装置及びその製造方法
JP2007251135A (ja) * 2006-02-18 2007-09-27 Seiko Instruments Inc 半導体装置およびその製造方法
JP2007294514A (ja) * 2006-04-21 2007-11-08 Renesas Technology Corp 半導体装置
US8193087B2 (en) * 2006-05-18 2012-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Process for improving copper line cap formation
JP2010171064A (ja) * 2009-01-20 2010-08-05 Panasonic Corp 半導体装置及びその製造方法
JP2012064713A (ja) * 2010-09-15 2012-03-29 Toshiba Corp 半導体装置の製造方法
US11862607B2 (en) * 2021-08-16 2024-01-02 Micron Technology, Inc. Composite dielectric structures for semiconductor die assemblies and associated systems and methods

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980048378A (ko) * 1996-12-17 1998-09-15 김광호 반도체소자의 평탄화방법
KR20020010440A (ko) * 1999-12-21 2002-02-04 조셉 제이. 스위니 부식 및 다이싱이 감소되는 고스루풋 구리 화학 기계적연마(ｃｍｐ) 방법 및 장치

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FR2630588A1 (fr) * 1988-04-22 1989-10-27 Philips Nv Procede pour realiser une configuration d'interconnexion sur un dispositif semiconducteur notamment un circuit a densite d'integration elevee
US6140226A (en) * 1998-01-16 2000-10-31 International Business Machines Corporation Dual damascene processing for semiconductor chip interconnects
US6420261B2 (en) * 1998-08-31 2002-07-16 Fujitsu Limited Semiconductor device manufacturing method
US6150272A (en) * 1998-11-16 2000-11-21 Taiwan Semiconductor Manufacturing Company Method for making metal plug contacts and metal lines in an insulating layer by chemical/mechanical polishing that reduces polishing-induced damage
KR100292409B1 (ko) * 1999-05-24 2001-06-01 윤종용 실리콘-메틸 결합을 함유하는 절연층을 포함하는 다층 구조의 절연막 및 그 형성방법
JP2001144086A (ja) * 1999-08-31 2001-05-25 Sony Corp 埋め込み配線の形成方法、及び、基体処理装置
US6380003B1 (en) * 1999-12-22 2002-04-30 International Business Machines Corporation Damascene anti-fuse with slot via
US6503827B1 (en) * 2000-06-28 2003-01-07 International Business Machines Corporation Method of reducing planarization defects
JP3917355B2 (ja) * 2000-09-21 2007-05-23 株式会社東芝 半導体装置およびその製造方法
US20020064951A1 (en) * 2000-11-30 2002-05-30 Eissa Mona M. Treatment of low-k dielectric films to enable patterning of deep submicron features
US6432811B1 (en) * 2000-12-20 2002-08-13 Intel Corporation Method of forming structural reinforcement of highly porous low k dielectric films by Cu diffusion barrier structures
US6583047B2 (en) * 2000-12-26 2003-06-24 Honeywell International, Inc. Method for eliminating reaction between photoresist and OSG
JP4160277B2 (ja) * 2001-06-29 2008-10-01 株式会社東芝 半導体装置の製造方法
US6562725B2 (en) * 2001-07-05 2003-05-13 Taiwan Semiconductor Manufacturing Co., Ltd Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers
KR100442863B1 (ko) * 2001-08-01 2004-08-02 삼성전자주식회사 금속-절연체-금속 커패시터 및 다마신 배선 구조를 갖는반도체 소자의 제조 방법
JP4131786B2 (ja) * 2001-09-03 2008-08-13 株式会社東芝 半導体装置の製造方法およびウエハ構造体
US6440840B1 (en) * 2002-01-25 2002-08-27 Taiwan Semiconductor Manufactoring Company Damascene process to eliminate copper defects during chemical-mechanical polishing (CMP) for making electrical interconnections on integrated circuits
US6531386B1 (en) * 2002-02-08 2003-03-11 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dish-free copper interconnects

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980048378A (ko) * 1996-12-17 1998-09-15 김광호 반도체소자의 평탄화방법
KR20020010440A (ko) * 1999-12-21 2002-02-04 조셉 제이. 스위니 부식 및 다이싱이 감소되는 고스루풋 구리 화학 기계적연마(ｃｍｐ) 방법 및 장치

Also Published As

Publication number Publication date
CN1467817A (zh) 2004-01-14
US6686285B2 (en) 2004-02-03
TW200307589A (en) 2003-12-16
JP2004014828A (ja) 2004-01-15
TWI224536B (en) 2004-12-01
JP4076131B2 (ja) 2008-04-16
US20030228765A1 (en) 2003-12-11
KR20030095189A (ko) 2003-12-18
CN1225019C (zh) 2005-10-26

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