CN1222984C - 微电子器件的制造方法及由该方法制造的微电子器件 - Google Patents
微电子器件的制造方法及由该方法制造的微电子器件 Download PDFInfo
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Abstract
提供一种微电子器件的制造方法，通过在GaAs化合物半导体材料上，特别是在例如异质结二极管的异质结结构GaAs化合物半导体材料上制成半导体件，它以简单且价廉的制造工艺获得具有长时间工作低欧姆接触电阻的特点。
Description
本发明涉及一种微电子器件的制造方法，至少在GaAs化合物半导体材料上具有电极，以及根据这种方法制造的微电子器件。
为了使半导材料上构成的微电子器件的电极与衬底上的其它元件和/或外部开关部件电连接，在半导材料上形成导电接点，它至少包括一低欧姆金属导电层，而构成的接点类型完全取决于接点的形式(欧姆接点/肖特基接点/电容接点)，取决于电子器件的类型(双极型晶体管/FET)、半导材料(Si/GaN/Gas/…)和杂质的类型(p/n)和浓度，以便根据上述参数的组合得到其它形式的接点，而在一般情况下，实施中呈现的优点不会明显地转移到其它参数组合中。
例如应用物理通讯第17期第17，24号，2000年4月出版，第2364-2366页由Lee等著的题为“用于n-型GaN的一组Ti/Al/Pt/Au膜层的欧姆接点的长期热稳定性”一文中，提供了通过在Al和Au之间添加铂层，在掺杂n-型杂质的GaN半导材料上现有使用一组Ti-Al-Au膜层欧姆接点，在增加接点的欧姆电阻时可以明显减小衰减。
EP0 402 061公开了在Si-衬底上设置一组TiW/TiWN/TiW/Au膜层，它用Au作为低欧姆导电层，并用钝化层视窗上分离的一组TiW/TiWN/TiW膜层作为粘接层和阻挡层。由IBM技术会刊第25期，第12号，1983年5月出版，第6398-6399页题为“接点金属的新结构”一文中公开了，在n+-掺杂Si半导体区域上的SiO2-钝化层视窗中获得低接触电阻，蒸发淀积TiN膜，并经高温处理，在半导体界面上形成TiSi2层，并由此形成TiN层作为扩散阻挡层，在其上分离出Al作为导电层。
在化合物半导体族领域，由于其电子器件的高载流子迁移率和与其关联的临界频率，其砷化镓(GaAs)技术是特别重要的。这类电子器件特别适用于高频率电路，例如：功率放大器、振荡器、信号混合电路以及分立元件。一般的接点为多层结构，并由金(Au)构成导电层，它通过扩散阻挡层和衬底的粘接层分离。其金导电层的特点在于导电率高，且不易腐蚀。
例如可以用升高(Lift-off)处理获得半导体表面上的接点结构，其中，通过光刻胶层深腐蚀接点表面结构，并在其上分离出接点的膜层顺序。首先在光刻胶掩膜上以低成本分离出包括粘接层、阻挡层和导电层(Au)的整个膜层顺序，另外，保证接点膜层顺序的自动调整。
但是，以公知方式制造的GaAs器件的缺点是，由于功率参数的下降使长期特性令人不满意，例如，对于异质结二极管随着时间推移其电流强度明显下降。
由IBM技术会刊第28期，第7号，1985年12月出版，第3183-3184页题为“用于GaAs的AuNiGe接点”一文中公开了一种方法，其中，由在GaAs半导体表面上经合金化步骤覆盖一组Ni/AuGe/Ni/Au膜层，形成低接触电阻的一组Ni2GeAs/Au3Ga膜层。
由日本期刊“应用物理”第23期，第8号，1984年8月出版，第L635-L637页Lto等著的题为“用于AlGaAs异质结二极管的n-GaAs的低电阻欧姆接点”一文中公开了一种用于n-GaAs的接点的制造方法，其中，有低温合金AuGe/Ni/Ti/Au-多层结构，在合金温度约为370℃时，其接触电阻最小。
“应用物理通讯”(62(22)，1993年5月31日出版，第2801-2803页由Stareev著的题为“p-GaAs的低电阻Ti/Pt/Au欧姆接点的构成”一文描述了p-GaAs接点的制造方法，其中在预处理步骤中，通过离子轰击清洗GaAs表面，而后，在分离出作为无合金接点的一组Ti/Pt/Au膜层之前，进行还原热处理步骤。
本发明的目的是，提供一种微电子器件的制造方法，至少在GaAs-化合物半导材料上具有电极，由此成本低的制造具有长期稳定性的微电子器件，以及根据这种方法制造的微电子器件。
在GaAs化合物半导体材料上的接点导电层结构完全或至少主要由铝构成，以替代现有的GaAs接点用Au作为导电材料，这样，可以简单并低成本制造低欧姆接点，制成的微电子器件具有良好的长期稳定性，特别是提高了异质结二极管(HBT)的电流强度的长期稳定性。有利于用升高工艺制造接点。
按本发明方案，通过升高工艺，在将接点分成例如Au导电层和位于其下的阻挡层时，用深腐蚀构成的升高处理用的光刻胶掩膜的分离作用，使接点的各层朝着接点边缘方向变薄，并与现有的GaAs接点相比，降低了在接点边缘的扩散抑制作用，低欧姆导电层中的金能扩散到半导体衬底的电极区域。对此，能使金扩散到例如有碳(C)杂质的GaAs半导体材料的电极区域，通过在半导体中起杂质物作用的金使在GaAs技术中的例如异质结二极管的基极出现载流子复合增多，由此减小了电流强度。
在电极接点上用铝作为导电层材料不会在GaAs化合物半导体材料中导致其微电子器件特性的衰减。由此，本发明特别适合用GaAs技术制造异质结二极管的基极。其微电子器件可以是复合单片集成电路的部件。
在现有技术中，将接点的一组膜层的相应层理解为接点的导电层，由于材料具较小的电阻率和较厚的膜膜厚度，主要考虑平行于衬底表面电流的接点电导。电极导电层中铝的实际扩散不会对复合中心的形成产生作用，例如，在金处于有杂质碳(C)的电极情况下。对此，在优选技术方案中，完全可以省去扩散阻挡层。可以以现有方式分出粘接层作为衬底接点的第一层，该层可以补偿半导体材料和导电层之间的机械压力，并保证半导体材料的膜层粘合，并减小了导电层和衬底材料之间的接点电位阻挡层。其粘接层最好主要由Ti、Pt、Mo、Ni、Pd构成，最好主要或完全由Ti构成。其粘接层的厚度小于导电层的厚度，并最好不大于50nm。其导电层的厚度至少为粘接膜厚度的5倍。通过导电层和半导体材料之间较小的粘接膜厚度及使用Ti构成，使得垂直于膜层的欧姆电阻很小。
有利的是，在升高处理工艺中，还在Al-导电层上分离出防止铝被腐蚀的防氧化层。其防氧化层至少主要由Ti、Ni、Pt中的一种或多种元素构成。并最好通过蒸发淀积镀膜形成粘接层和导电层，特别是直接先后分离出如粘接层和导电层。特别是在优选使用Ti作为粘接材料时，不通过离子轰击对半导体表面进行预处理。此外，本发明的方法不需要合金化步骤，使接点的制造工艺特别简单且成本低。
例如，如果受到技术环境条件的限制不能省去导电层中的金，根据本发明的一个有利变型，可以分离出含有金的现有的一组膜层，它包括：导电层和与半导体材料隔开的扩散阻挡层，以及粘接层，该粘接层在比接点结构表面要大的半导体材料上，特别是在整个半导体表面上，并再腐蚀大面积的一组膜层，形成接点。对此，在接点范围内，获得均匀的阻挡层，通过可靠的抑制作用来防止金扩散到半导体材料中。
本发明的另一有利变型中，为了制造包括导电层和扩散阻挡层的含金的接点，在分离出接点的膜层顺序之前，在半导体材料上首先分离出绝缘层，特别是第一氮化硅层，并在电极上形成绝缘层的接点视窗。通过现有的升高技术，和例如由粘接层、阻挡层和含金的导电层构成的现有的一组膜层，形成接点的一组膜层，但其中接点的结构要覆盖接点视窗的边缘，使得在通过深腐蚀而使掩膜分离时，其膜厚逐渐变薄的接点结构的边缘要位于绝缘层上，其绝缘层的侧面同样起到扩散抑制作用，通过其绝缘层，或在接点视窗内，金不会通过阻挡层扩散到半导体材料中。
下面参照附图借助优选实施例进一步描述本发明。其中：
图1示出了现有结构的横截面图；
图2示出了导电层不含金的接点一组膜层的横截面图；
图3示出了具有再侵蚀一组膜层接点的横截面图；
图4示出了覆盖接点窗的接点横截面图。
图1示出了现有使用的接点结构的横截面图，其中在半导体1上，例如，它特别是根据GaAs技术有碳杂质的、由化合物半导体材料制成的异质结二极管的基层，分离出一组金属膜层，它包括粘接层2、扩散阻挡层3和由金构成的低欧姆导电层4。根据用光刻胶掩膜的升高技术在其表面上形成金属一组膜层2-4的结构，其掩膜口MO经深扩展到半导体层1。用唯一的掩膜通过蒸发淀积镀膜形成一组膜层2-4。在一组膜层分层后，光刻胶掩膜与分层金属分离。其分层在突出于掩膜开口MO的垂直投影的边缘区域RB逐渐变薄，扩散抑制作用使得阻挡层2退回到其边缘区域，或在边缘分布不均匀时还可以部分升高，且使导电层4中的金扩散到半导体层1中，并在那里可能形成复合中心，由于载流子复合作用增加，使得半导体件的性能参数下降，如二极管的强度变差。
如图2中所示，在同样根据可靠且价廉的升高技术得到的接点结构中，在其半导体层1上具有另一组膜层，它包括：粘接层2、完全或至少主要由铝构成的不含金的导电层5和耐腐蚀层6。在铝导电层5和半导体层1之间不需要扩散阻挡层，且最好不设置扩散阻挡层，因为，可能在很小范围内扩散到半导体层1中的铝不产生如金的变异作用。附加扩散阻挡层可以通过限制其边缘区域而明显地进一步减小铝扩散到半导体层中。通过铝的良好导电性和比粘接层2厚的导电层5保证高的平行层电导。其耐腐蚀层6防止在含氧环境下其铝导电层5被氧化，并可以在其它制造工艺中对其结构进行无缺陷处理。其耐腐蚀层，例如，由Ti、Ni、Pt或耐铝腐蚀的其它材料构成。其粘接层用在半导体层1上，对一组膜层进行良好的机械粘接，并使垂直于膜层平面的接点电阻较小，它可以例如由Ti、Pt、Mo、Ni、Pd构成，最好完全或至少主要由Ti构成。
在图3所示的接点结构中，例如可以具有如图1所示的一组膜层，特别是在粘接层21上具有扩散阻挡层31和由金构成的导电层41。其一组膜层的整个表面覆盖在半导体层的表面上(用虚线表示)，并借助再侵蚀的光刻胶掩膜形成在半导体层上。通过完全分层一组膜层的表面，在完成的接点结构中，其阻挡层31的膜厚是均匀的，而且，金不会扩散到半导体层1中。
为了在半导体层1上制成图4所示的包括金导电层42的接点结构，首先分离出最好由氮化硅Si3N4构成的绝缘层10，且在其中例如采用腐蚀模的干式化学侵蚀，限定接点窗KF。接着，以现有的升高技术，分离出包括：粘接层22、扩散阻挡层32和低欧姆的金导电层42的一组金属膜层，其中，升高工艺用的光刻胶掩膜结构和腐蚀掩模的结构确定为，使其接点结构可靠覆盖接点窗KF的边缘，使接点的边缘区域通过在绝缘层10上伸出的薄层距接点窗有一定距离。在一组金属膜层的边缘区域下面，通过阻挡层32可靠阻止金向半导体层扩散。在接点视窗上，通过厚度均匀的阻挡层防止扩散。
本发明不只限于所述的实施例，本领域的普通技术人员可以以不同的方式进行变换。
Claims (14)
1.一种微电子器件的制造方法，具有在化合物半导体材料上的电极，并且在该半导体材料上具有至少一个与该电极接触的低欧姆金属接点，
其中，该接点借助升高工艺形成，并由具有低欧姆导电层的多个不同的膜层构成；
其中，形成用于在掩膜(PL)中进行升高工艺的带有侧凹陷的开口(MO)；
其中，分离在该开口内用作该接点的、具有朝边缘区域(RB)变薄的膜厚度的一组金属膜层(2，3，4)；
其特征在于：在该半导体材料上分离该接点的该组膜层的各膜层之前，分离出一绝缘层(10)；
在该电极上该绝缘层中形成视窗(KF)；以及
分离该接点，使该接点覆盖接点视窗的边缘，并且使该接点的边缘区域(RB)通过在该绝缘层(10)上伸出的变薄的膜层而距该接点视窗一定距离。
2.如权利要求1的方法，其特征在于：在其导电层上分出防氧化层。
3.如权利要求2的方法，其特征在于：该防氧化层至少由Ti、Ni、Pt中的一种或多种元素构成。
4.如权利要求2的方法，其特征在于：在该导电层和化合物半导体材料之间没有分离扩散阻挡层。
5.如权利要求1的方法，其特征在于：分离一粘接层(2)作为该组膜层的第一层。
6.如权利要求5的方法，其特征在于：粘接层至少由Ti、Pt、Mo、Ni、Pd中的一种或多种元素构成。
7.如权利要求1的方法，其特征在于：该组膜层(2，3，4)的各层彼此直接覆盖，特别是蒸发淀积镀膜形成的膜层彼此直接覆盖。
8.如权利要求7的方法，其特征在于：导电层、粘接层和防氧化层不进行合金化处理。
9.如权利要求1的方法，其特征在于：其半导体材料是GaAs材料。
10.如权利要求1的方法，其特征在于：分离出氮化物作为绝缘层。
11.一种微电子器件，具有在化合物半导体材料上的电极，并且在该化合物半导体材料上具有至少一个与该电极接触的低欧姆金属接点，其中，该接点由一组膜层构成，该组膜层具有带有低欧姆导电层的多个不同的膜层，并且该组膜层的各膜层的膜厚度朝边缘区域变薄，其特征在于：在该化合物半导体材料上设置绝缘层(10)，在该电极上该绝缘层中形成视窗(KF)，并且在该触点视窗中该接点被分离为，使该接点的边缘区域通过在该绝缘层上变薄的膜厚度而距该接点视窗一定距离。
12.如权利要求11的微电子器件，其特征在于：该化合物半导体材料为GaAs化合物半导体材料。
13.如权利要求11的微电子器件，其特征在于：该导电层完全或主要由铝构成。
14.如权利要求11的微电子器件，其特征在于：该器件是异质结二极管。
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| JPS57183071A (en) * | 1981-05-06 | 1982-11-11 | Nec Corp | Formation of recess type fine multi-layer gate electrode |
| JPS60123026A (ja) * | 1983-12-08 | 1985-07-01 | Toshiba Corp | 半導体装置の製造方法 |
| JPH0722141B2 (ja) * | 1984-03-07 | 1995-03-08 | 住友電気工業株式会社 | 半導体素子の製造方法 |
| JPS6298768A (ja) * | 1985-10-25 | 1987-05-08 | Nec Corp | 半導体素子用電極 |
| US4994892A (en) * | 1986-10-09 | 1991-02-19 | Mcdonnell Douglas Corporation | Aluminum germanium ohmic contacts to gallium arsenide |
| WO1989004057A1 (en) * | 1987-10-20 | 1989-05-05 | Bell Communications Research, Inc. | Epitaxial intermetallic contact for compound semiconductors |
| US5849630A (en) * | 1989-03-29 | 1998-12-15 | Vitesse Semiconductor Corporation | Process for forming ohmic contact for III-V semiconductor devices |
| JP2661333B2 (ja) * | 1989-06-05 | 1997-10-08 | モトローラ・インコーポレーテツド | 金属被覆化プロセス処理方法 |
| FR2697945B1 (fr) * | 1992-11-06 | 1995-01-06 | Thomson Csf | Procédé de gravure d'une hétérostructure de matériaux du groupe III-V. |
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| JPH0945635A (ja) * | 1995-07-27 | 1997-02-14 | Mitsubishi Electric Corp | 半導体装置の製造方法，及び半導体装置 |
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