WO1989004057A1 - Epitaxial intermetallic contact for compound semiconductors - Google Patents

Epitaxial intermetallic contact for compound semiconductors Download PDF

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Publication number
WO1989004057A1
WO1989004057A1 PCT/US1988/003663 US8803663W WO8904057A1 WO 1989004057 A1 WO1989004057 A1 WO 1989004057A1 US 8803663 W US8803663 W US 8803663W WO 8904057 A1 WO8904057 A1 WO 8904057A1
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Prior art keywords
contact
transition metal
group iii
semiconductor
intermetallic
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PCT/US1988/003663
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French (fr)
Inventor
Timothy David Sands
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Bell Communications Research, Inc.
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Publication of WO1989004057A1 publication Critical patent/WO1989004057A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds

Definitions

  • This invention relates to metallic contacts for compound semiconductors. More particularly, the present invention relates to epitaxial metallic contacts for III-V compound semiconductors and to a method for the preparation thereof.
  • intermetallic compounds of the invention permit the fabrication of novel electronic and photonic devices based upon compound semiconductor/metal/compound semiconductor heterojunctions, for example, metal base and permeable base transistors.
  • a suitable substrate is first selected and prepared for deposition of the intermetallic contact.
  • Substrates suitable for this purpose may be selected from among the commercially available Group III-V materials, for example, indium gallium arsenide, gallium arsenide, aluminum gallium arsenide, indium phosphide and the like.
  • the substrate selected is initially cleansed by conventional cleansing techniques for the purpose of removing deleterious organics from the surface thereof and forming thereon a thin film, typically 10-20 Angstroms in thickness, of a native oxide.
  • a transition metal is deposited upon the substrate selectively by vacuum evaporation or electron beam techniques, the metal selected being such that its lattice parameters are sufficient to yield a monocrystalline film with the Group III metals employed herein. Transition metals meeting this requirement include cobalt, nickel, iron, manganese, iridium, osinium, rhodium and ruthenium.
  • the structure so prepared is subjected to thermal annealing at a temperature ranging from 350-950°C for a time period ranging from a few seconds to several minutes, the anneal resulting in the formation of a monocrystalline or epitaxial intermetallic contact which is now amenable for fabrication of any device requiring a Schottky barrier.
  • devices incorporating this intermetallic contact may include field effect transistors, metal base transistors including two layers of a compound semiconductor separated by a thin film of my intermetallic compound, permeable base transistors comprising a semiconductor sandwich having a patterned intermediate layer comprising a thin film of the intermetallic compound, and buried interconnects including the intermetallic compound in accordance with my invention.
  • Example 1 The following example is set forth for purposes of exposition. It will, however, be understood that the example is solely for purposes of exposition and is not to be construed as limiting.
  • Example 2 The following example is set forth for purposes of exposition. It will, however, be understood that the example is solely for purposes of exposition and is not to be construed as limiting.
  • a polished (100) gallium arsenide wafer was etched with a 5:1:1 mixture of sulfuric acid, hydrogen peroxide and water and then given a one minute dip in a
  • the wafer was loaded into an electron gun evaporation chamber which was then pumped down to _7 8x10 torr.
  • Thin alternate layers of nickel and aluminum were then deposited to yield a layering sequence comprising 10 nm nickel - 34 nm aluminum - 10 n nickel - gallium arsenide.
  • This film sequence was chosen based upon prior efforts which revealed that a thin nickel layer will penetrate the native oxide of gallium arsenide at moderate temperatures (room temperature to approximately 300 C, depending on oxide thickness) .
  • the layer thicknesses were chosen to give an average composition of approximately Ni._ Al_ 5 . Studies have shown that the nickel-aluminum phase can accommodate compositions from i 45 l 55 to Ni 6Q Al 40 .
  • the gallium arsenide wafer was capped with 200 nm of aluminum nitride deposited by reactive ion beam sputtering. This cap served to prevent the loss of arsenic from the gallium arsenide substrate during the subsequent high temperature annealing step.
  • Annealing was then effected with an incoherent light rapid annealing station at a temperature of 850°C for 10 seconds following which the aluminum nitride cap was removed by dipping in buffered hydrogen flouride.
  • the film so annealed was then characterized by transmission electron microscopy, electron diffraction and x-ray diffraction.
  • the electron diffraction studies revealed the presence of a well oriented layer of single crystal nickel aluminum. This was confirmed by the transmission electron microscopy and x-ray diffraction studies. Forward I-V measurements were made with a

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A class of intermetallic compound contact materials for III-V semiconductors is obtained by depositing successively and concurrently a thin film of a transition metal and a Group III metal upon the semiconductor and annealing the resultant structure, so resulting in the formation of a monocrystalline intermetallic contact. The contacts are stable at temperatures ranging from 600-900°C and may be fabricated by conventional vacuum deposition.

Description

EPITAXIAL INTERMETALLIC CONTACT FOR COMPOUND SEMICONDUCTORS
This invention relates to metallic contacts for compound semiconductors. More particularly, the present invention relates to epitaxial metallic contacts for III-V compound semiconductors and to a method for the preparation thereof.
During the past two decades, considerable effort has been spent upon the development of metallic contacts for compound semiconductors. In general, workers in the art have focused upon three goals, namely, the attainment of epitaxy, thermodynamic stability at high temperature, and the use of conventional fabrication processes. Unfortunately, none of the prior art efforts has succeeded in satisfying each of these criteria. Thus, for example, nominally monocrystalline films of aluminum have been grown on gallium arsenide by molecular beam epitaxy under ultra-high vacuum conditions. However, the melting point of aluminum (660°C) is too low for the majority of desired applications. Furthermore, the deposition of aluminum
—6 —V under conventional vacuum conditions (10 to 10 torr. upon chemically cleaned substrates) results in the formation of polycrystalline films which may be attributed to the disruptive effect of the native oxide on gallium arsenide. These polycrystalline films evidence rapid degradation of electrical properties at temperatures as low as 290°C notwithstanding the fact that the epitaxial aluminum contacts are relatively stable at this temperature. Still further efforts to effect the desired end involved the deposition of cobalt and iron upon gallium arsenide under high vacuum conditions. Although such techniques resulted in the formation of films evidencing a high degree of crystallographic texture, neither metal proved stable on gallium arsenide since moderate annealing at temperatures above 400°C is sufficient to produce ternary and binary product phases.
In accordance with the present invention, these prior art limitations are effectively obviated by the use of a class of intermetallic compound contact materials to III-V semiconductors which are stable at temperatures ranging from 600-900°C, epitaxial or onocrystalline in nature and capable of being fabricated by conventional vacuum deposition and electron beam deposition techniques. The described intermetallic compounds comprise approximately 50 atomic percent of a Group III element such as aluminum or gallium, so minimizing the enthalpic driving force for reaction with the Group III-V substrate. The remaining 50 atomic percent comprises a transition metal such that transition metal with Group III metal films are intermetallic compounds having the cesium chloride structure. The novel contacts are the first contact materials for III-V compound semiconductors reported in the literature that are both epitaxial and stable at high temperatures (600-900°C) . Accordingly, these intermetallic compounds are ideally suited for rectifying gate contacts to field effect transistors, particularly those fabricated by a self-aligning process involving 800-900°C annealing of the gate contact. The single crystal nature of these contacts eliminates contact degradation mechanisms which involve grain boundary diffusion, a major source of instability.
Still further, the intermetallic compounds of the invention permit the fabrication of novel electronic and photonic devices based upon compound semiconductor/metal/compound semiconductor heterojunctions, for example, metal base and permeable base transistors.
In the fabrication of the described contacts, a suitable substrate is first selected and prepared for deposition of the intermetallic contact. Substrates suitable for this purpose may be selected from among the commercially available Group III-V materials, for example, indium gallium arsenide, gallium arsenide, aluminum gallium arsenide, indium phosphide and the like.
The substrate selected is initially cleansed by conventional cleansing techniques for the purpose of removing deleterious organics from the surface thereof and forming thereon a thin film, typically 10-20 Angstroms in thickness, of a native oxide. Next, a transition metal is deposited upon the substrate selectively by vacuum evaporation or electron beam techniques, the metal selected being such that its lattice parameters are sufficient to yield a monocrystalline film with the Group III metals employed herein. Transition metals meeting this requirement include cobalt, nickel, iron, manganese, iridium, osinium, rhodium and ruthenium. However, it will be understood that stable epitaxial contacts for Group III-V compound semiconductors must be matched to provide compatible lattice parameters and electrical characteristics, such being known to those skilled in the art. Deposition of the transition metal on the substrate surface is effected to yield a thickness ranging from 50-200 Angstroms, the film so deposited serving to mechanically disperse the native oxide on the substrate. Following, a Group III metal in elemental form is deposited upon the transition metal in a thickness ranging from 100-800 Angstroms such that the atomic ratio between the two deposited metals is approximately 1:1, deposition being effected as described above. Then, a second film of the transition metal may optionally be deposited, as previously described to provide protection to the aluminum surface of the contact, thereby avoiding oxidation during handling outside the vacuum system.
At this juncture, the structure so prepared is subjected to thermal annealing at a temperature ranging from 350-950°C for a time period ranging from a few seconds to several minutes, the anneal resulting in the formation of a monocrystalline or epitaxial intermetallic contact which is now amenable for fabrication of any device requiring a Schottky barrier. Specifically in accordance with aspects of my invention devices incorporating this intermetallic contact may include field effect transistors, metal base transistors including two layers of a compound semiconductor separated by a thin film of my intermetallic compound, permeable base transistors comprising a semiconductor sandwich having a patterned intermediate layer comprising a thin film of the intermetallic compound, and buried interconnects including the intermetallic compound in accordance with my invention.
The following example is set forth for purposes of exposition. It will, however, be understood that the example is solely for purposes of exposition and is not to be construed as limiting. Example
A polished (100) gallium arsenide wafer was etched with a 5:1:1 mixture of sulfuric acid, hydrogen peroxide and water and then given a one minute dip in a
1:1 solution of hydrochloric acid and deionized water.
The wafer was next blown dry with nitrogen.
Following, the wafer was loaded into an electron gun evaporation chamber which was then pumped down to _7 8x10 torr. Thin alternate layers of nickel and aluminum were then deposited to yield a layering sequence comprising 10 nm nickel - 34 nm aluminum - 10 n nickel - gallium arsenide. This film sequence was chosen based upon prior efforts which revealed that a thin nickel layer will penetrate the native oxide of gallium arsenide at moderate temperatures (room temperature to approximately 300 C, depending on oxide thickness) . The layer thicknesses were chosen to give an average composition of approximately Ni._ Al_5. Studies have shown that the nickel-aluminum phase can accommodate compositions from i45 l55 to Ni6Q Al40.
Following deposition, the gallium arsenide wafer was capped with 200 nm of aluminum nitride deposited by reactive ion beam sputtering. This cap served to prevent the loss of arsenic from the gallium arsenide substrate during the subsequent high temperature annealing step. Annealing was then effected with an incoherent light rapid annealing station at a temperature of 850°C for 10 seconds following which the aluminum nitride cap was removed by dipping in buffered hydrogen flouride. The film so annealed was then characterized by transmission electron microscopy, electron diffraction and x-ray diffraction. The electron diffraction studies revealed the presence of a well oriented layer of single crystal nickel aluminum. This was confirmed by the transmission electron microscopy and x-ray diffraction studies. Forward I-V measurements were made with a
Keithley model 220 programmable current source and a Keithley model 619 electrometer. These measurements are summarized in the Table which follows.
TABLE
I
I
10
Figure imgf000008_0002
Figure imgf000008_0001
In the table, data is presented indicating the barrier heights and ideality factors of nickel aluminum contacts to n-gallium arsenide, the data being based upon the current-voltage studies. For comparative purposes, barrier heights and ideality factors of selected refractory contacts to n-gallium arsenide are shown. It is noted from the Table that the measured barrier height increases by 200 mV to 0.99V when annealed at temperatures of up to 650°C while retaining an ideality factor approaching unity (1.10), the characteristic sought in a stable Schottky contact. It will be appreciated that this is among the highest measured barrier heights reported in the literature for contacts to n-gallium arsenide. At annealing temperatures greater than 650 C the data deviates from the ideal thermionic emission; however, the contacts remain rectifying.
The metallurgically stable Schottky contact to n-gallium arsenide described, as noted, evidences a barrier height (0.99v) comparable to or higher than barrier heights measured for nitrides annealed under similar conditions and significantly higher than barrier heights obtained with elemental refractory metals or suicides. Furthermore, the adherence and mechanical properties of the nickel-aluminum-nickel layer structure on gallium arsenide are compatible with conventional lift-off patterning techniques, so suggesting the use thereof in self aligned metal-semiconductor field effect transistors.
It will by appreciated by those skilled in the art that modification within the purview of the skilled artisan may be made without departing from the spirit and scope of the invention. Then, for example, the intermetallic contact may be prepared by co-deposition of the metal components and various combinations of metallizations may be prepared so long as the lattice parameters of the resultant product evidence the cesium chloride structure. It will be further understood that the described intermetallic contact may serve as a template for the growth of crystalline compound semiconductors.

Claims

What is claimed is:
1. Intermetallic contact for III-V semiconductor comprising an essentially 1:1 atomic ratio of a Group III element and a transition metal, said contact having a cesium chloride structure.
2. Contact in accordance with Claim 1 wherein said semiconductor is gallium arsenide.
3. Contact in accordance with Claim 1 wherein said contact comprises nickel and aluminum.
4. Contact in accordance with Claim 2 wherein said contact comprises nickel and aluminum.
5. Method for the preparation of an intermetallic contact upon a III-V semiconductor which comprises the steps of (a) depositing a thin film of a transition metal of a thickness ranging from 50-200 Angstroms upon said semiconductor,
(b) depositing a thin film of a Group III metal in a thickness ranging from 100-800 Angstroms upon said transition metal such that the atomic ratio between all deposited metals is approximately 1:1, and
(c) subjecting the resultant structure to thermal annealing at a temperature ranging from 350-950°C for a time period ranging from a few seconds to several minutes, so resulting in the formation of a monocrystalline intermetallic contact.
6. Method in accordance with Claim 5 wherein deposition is effected by vacuum evaporation.
7. Method in accordance with Claim 5 wherein a second thin film of said transition metal is deposited upon the Group III metal prior to annealing.
8. Method in accordance with CLaim 5 wherein said transition metal is nickel and said Group III metal is aluminum.
9. Field effect transistor including an inter ettallic contact to the semiconductor thereof, said contact comprising an essentially 1:1 atomic ratio of a Group III element and a transition metal and having the cesium chloride structure.
10. Metal base transitor including two layers of a compound semiconductor separated by a thin film of an intermetallic contact comprising an essentially 1:1 atomic ratio of a Group III element and a transition metal and having the cesium chloride structure.
11. Permeable base transistor comprising a semiconductor sandwich having a patterned intermediate layer comprising a thin film of an intermetallic contact comprising as essentially 1:1 atomic ratio of a Group III element and a transition metal and having the cesium chloride structure.
12. Buried interconnect including an intermetallic contact comprising an essentially 1:1 atomic ratio of a Group III element and a transition metal and having the cesium chloride structure.
PCT/US1988/003663 1987-10-20 1988-10-18 Epitaxial intermetallic contact for compound semiconductors WO1989004057A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5516725A (en) * 1992-03-17 1996-05-14 Wisconsin Alumni Research Foundation Process for preparing schottky diode contacts with predetermined barrier heights
US5706168A (en) * 1995-07-07 1998-01-06 Itronix Corporation Impact-resistant notebook computer having hard drive mounted on shock-isolating mounting bridge and impact attenuating covering
WO2002052626A2 (en) 2000-12-22 2002-07-04 United Monolithic Semiconductors Gmbh Method for producing a microelectronic component and component produced according to said method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55145366A (en) * 1979-04-27 1980-11-12 Mitsubishi Electric Corp Ohmic electrode of n-type semiconductor of groups 3-5 metals in periodic table and forming method of the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55145366A (en) * 1979-04-27 1980-11-12 Mitsubishi Electric Corp Ohmic electrode of n-type semiconductor of groups 3-5 metals in periodic table and forming method of the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, volume 5, no. 15 (E-43)(687), 29 January 1981; & JP-A-55145366 (MITSUBISHI DENKI K.K.) 12 November 1980 *
Patent Abstracts of Japan, volume 8, no. 115 (E-247)(1552), 5 May 1984; & JP-A-5929466 (NIPPON DENKI K.K.) 16 February 1984 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5516725A (en) * 1992-03-17 1996-05-14 Wisconsin Alumni Research Foundation Process for preparing schottky diode contacts with predetermined barrier heights
US5706168A (en) * 1995-07-07 1998-01-06 Itronix Corporation Impact-resistant notebook computer having hard drive mounted on shock-isolating mounting bridge and impact attenuating covering
WO2002052626A2 (en) 2000-12-22 2002-07-04 United Monolithic Semiconductors Gmbh Method for producing a microelectronic component and component produced according to said method
WO2002052626A3 (en) * 2000-12-22 2003-02-13 United Monolithic Semiconduct Method for producing a microelectronic component and component produced according to said method

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EP0383821A1 (en) 1990-08-29
JPH02502324A (en) 1990-07-26

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