WO2002052626A2 - Verfahren zur herstellung eines mikroelektronischen bauelements und danach hergestelltes bauelement - Google Patents
Verfahren zur herstellung eines mikroelektronischen bauelements und danach hergestelltes bauelement Download PDFInfo
- Publication number
- WO2002052626A2 WO2002052626A2 PCT/EP2001/014955 EP0114955W WO02052626A2 WO 2002052626 A2 WO2002052626 A2 WO 2002052626A2 EP 0114955 W EP0114955 W EP 0114955W WO 02052626 A2 WO02052626 A2 WO 02052626A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- contact
- conductive layer
- semiconductor material
- deposited
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000004377 microelectronic Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 37
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 23
- -1 GaAs compound Chemical class 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 152
- 239000010931 gold Substances 0.000 claims description 35
- 230000004888 barrier function Effects 0.000 claims description 27
- 239000012790 adhesive layer Substances 0.000 claims description 24
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 22
- 229910052737 gold Inorganic materials 0.000 claims description 22
- 238000009792 diffusion process Methods 0.000 claims description 20
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 239000011241 protective layer Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000005275 alloying Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 230000007774 longterm Effects 0.000 abstract description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 238000005215 recombination Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910018170 Al—Au Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
- H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the invention relates to a method for producing a microelectronic component with at least one electrode in a GaAs connection semiconductor material and to a component produced using such a method.
- an electrically conductive contact is generated on the semiconductor material which contains at least one low-resistance metallic conductive layer.
- the type of contact formation depends strongly on the type of contact (ohmic / schottky / capacitive), the type of component (bipolar / FET), the semiconductor material (Si / GaN / Gas / ...) and the type (p / n) and the amount of the doping, so that, depending on the combination of such parameters, different types of contacts are used and the advantages that occur in one type are generally not readily transferable to other parameter combinations
- EP 0 402 061 shows on a Si substrate a TiW / TiWN / TiW / Au layer sequence with Au as a low-resistance conductive layer and the TiW / TiWN / TiW layer sequence deposited over a window of a passivation layer as an adhesive layer and barrier. From "New structure for contact metallurgy" in IBM Technical Disclosure Bulletin, Vol. 25, No. 12, May 1983, pp.
- the contact has a multilayer structure and comprises a gold (Au) conductive layer, which is separated from the substrate by a diffusion barrier layer and an adhesive layer.
- Au gold
- the gold conductive layer is characterized by a particularly high conductivity and is corrosion-free.
- the structure of the contact on the semiconductor surface can be produced, for example, in a lift-off process in which the surface structure of the contact with an undercut is etched free in a photoresist layer and the layer sequence of the contact is then deposited thereon.
- the deposition of the entire layer sequence of adhesive layer, barrier layer and conductive layer (Au) on a photoresist mask is, on the one hand, inexpensive and, on the other hand, ensures the self-aligned deposition of the successive layers of the contact.
- GaAS components produced in this customary manner disadvantageously show unsatisfactory long-term behavior with decreasing performance data, for example in the form of a current gain in heterobipolar transistors which decreases significantly over time.
- the invention is based on the object of specifying a production method for microelectronic components with at least one electrode in a GaAs compound semiconductor material, with which components with long-term stable properties can be produced in a cost-effective manner, and a component produced using such a method.
- the structure of the conductive layer in a contact on GaAs compound semiconductor material completely or at least predominantly made of aluminum instead of the Au as usual for GaAs contacts as the conductive layer material enables simple and inexpensive production of a low-resistance contact with good long-term stability of the component properties, in particular the current gain of one Hetero-bipolar transistor (HBT).
- the contact can advantageously be made in a lift-off process.
- the invention makes use of the observation that when a contact with, for example, an Au conductive layer and an underlying barrier layer is deposited by means of a lift-off process, the layer thicknesses of the individual layers of the contact towards the edges of the contact due to the deposition become thinner in the undercut-structured photoresist mask of the lift-off process and then the diffusion barrier effect of the barrier layer at the edges of the contact decreases with the usual contacts on GaAs and gold from the low-resistance conductive layer in the electrode area of the semiconductor substrate can diffuse.
- the invention is therefore also particularly advantageous for the production of a base contact of a hetero bipolar transistor using GaAs technology.
- the device can be part of a more complex monolithically integrated circuit.
- the conductive layer of the contact is understood to be that layer of the layer sequence of the contact which, due to the low specific resistance of the material and the relatively large layer thickness, makes the main contribution to the conductance of the contact for current conduction parallel to the substrate surface. Any diffusion of aluminum from the conductive layer into the electrode does not have the effect of forming recombination centers such as this. B. is the case with gold in a carbon-doped GaAs electrode. The diffusion barrier layer can therefore be omitted entirely in a preferred embodiment.
- An adhesive layer which, on the one hand, compensates for mechanical stresses between the semiconductor material and the conductive layer and can ensure layer adhesion on the semiconductor material and on the other hand, above all, reducing contact potential barriers between the materials of the conductive layer and substrate, can be deposited on the substrate as the first layer of the contact in a manner which is conventional per se.
- the adhesive layer advantageously consists predominantly of one or more of the elements Ti, Pt, Mo, Ni, Pd, preferably predominantly or entirely of Ti.
- the thickness of the adhesive layer is small compared to the thickness of the conductive layer and is preferably not more than 50 nm.
- the thickness of the conductive layer is advantageously at least 5 times the thickness of the adhesive layer. Due to the small layer thickness of the adhesive layer between the conductive layer and the semiconductor material and the use of Ti, the ohmic resistance perpendicular to the layers is very low.
- a protective layer is deposited on the Al conductive layer during the lift-off process, which prevents corrosion of the aluminum.
- the protective layer advantageously consists at least predominantly of one or more of the elements Ti, Ni, Pt and, like the adhesive layer and the conductive layer, is preferably deposited directly in succession by vapor deposition.
- preparation of the semiconductor surface by ion bombardment is not provided.
- An alloy step is also not provided in the method according to the invention, so that there is a particularly simple and inexpensive process for producing the contact.
- a layer sequence that is conventional per se with a gold-containing conductive layer and a diffusion barrier layer separating it from the semiconductor material, and optionally one Adhesive layer on the semiconductor material larger than the contact structure, in particular deposited over the entire area on the semiconductor and the contact can be produced by structured etching back of this large-area layer sequence.
- a uniform barrier layer with a reliable barrier effect against gold diffusion into the semiconductor material is achieved within the contact.
- a further advantageous variant of the invention provides for the production of a contact with a gold-containing conductive layer and a diffusion barrier layer that before the deposition of the contact layer sequence, an insulating layer, preferably a silicon nitride layer, is deposited on the semiconductor material and above the electrode a contact window is created in this insulating layer.
- the subsequent generation of the layer sequence of the contact can be done with the usual lift-off technique and the usual layer sequence of e.g. B. adhesive layer, barrier layer and gold-containing conductive layer, but the structure of the contact the edges of the
- Contact window overlaps so that the edges of the contact structure, at which the layer thicknesses become thinner when deposited with an undercut mask, lie on the insulating layer, which in turn also acts as a diffusion barrier, so that no gold through the insulating layer or in the contact window through the Barrier layer diffuses to the semiconductor material.
- FIG. 1 shows a cross section through a conventional structure.
- FIG. 2 shows a cross section through a contact layer sequence with gold-free
- FIG. 3 shows a cross section through a contact with a back-etched layer sequence.
- FIG. 4 shows a cross section through an overlapping contact window
- Contact Fig. 1 shows a cross section through a common structure of a contact, in which on a semiconductor layer 1, which, for. B. is a carbon-doped base layer of a hetero-bipolar transistor made of compound semiconductor material, in particular in GaAs technology, a metallic layer sequence of an adhesive layer 2, a diffusion barrier layer 3 and a low-resistance conductive layer 4 Gold is deposited.
- the structuring of the metallic layer sequence 2 to 4 on the surface takes place in lift-off technology by means of a photoresist mask PL, the mask opening MO of which is widened towards the semiconductor layer 1 by an undercut.
- Layer sequence 2 to 4 is produced by vapor deposition with a single mask. After the layer sequence has been deposited, the photoresist mask and the metal deposited thereon are detached. The deposited layers run thinner in an edge region RB that extends beyond the vertical projection of the mask opening MO, so that the diffusion-blocking effect of the barrier layer 2 in this edge region decreases or in some cases can also be omitted in the case of an irregular edge profile and gold from the guide layer 4 in can diffuse the semiconductor layer 1 and form recombination centers there, which by increased charge carrier recombination the characteristic data of the semiconductor component, for. B. deteriorate the current gain of a bipolar transistor.
- a gold-free conductive layer 5 lies entirely or at least predominantly of aluminum and a corrosion protection layer 6 on the semiconductor layer 1 in front.
- a diffusion barrier layer between the Al conductive layer 5 and the semiconductor layer 1 is not necessary and is preferably not present, since aluminum, which may diffusing conductor layer, there does not develop the degrading effect like gold.
- An additional diffusion barrier layer can further significantly reduce the aluminum diffusion into the semiconductor layer by restricting it to the edge regions.
- a high layer-parallel conductivity is ensured by the good specific conductivity of aluminum and the layer thickness of the conductive layer 5 that is large compared to the adhesive layer 2.
- the protective layer 6 prevents the oxidation of the aluminum of the conductive layer 5 in an oxygen-containing atmosphere and thus permits unproblematic handling of the arrangement in the further manufacturing process.
- the protective layer consists, for example, of Ti, Ni, Pt or other materials that protect against corrosion by Al.
- the adhesive layer ensures good mechanical adhesion of the layer sequence on the semiconductor layer 1 and for a low contact resistance perpendicular to the layer plane and can, for. B. from Ti, Pt, Mo, Ni, Pd, preferably completely or at least predominantly consist of Ti.
- the contact sketched in cross section in FIG. 3 can have, for example, the same layer sequence as in FIG. 1 and in particular comprise a diffusion barrier layer 31 and a conductive layer 41 made of gold on an adhesive layer 21.
- the layer sequence is applied to the entire surface of the surface of the semiconductor layer (indicated by broken lines) and structured by means of a photoresist mask by etching back to the semiconductor layer. Due to the deposition of the layer sequence over the entire surface, the barrier layer 31 in the finished structured contact has a uniform layer thickness which effectively prevents gold from diffusing into the semiconductor layer 1.
- an insulating layer 10 preferably made of silicon nitride Si 3 N, is first deposited and in this, z. B. defined by dry chemical etching with an etching mask, a contact window KF.
- the metallic layer sequence of contact with the adhesive layer 22, diffusion barrier layer 32 and low-resistance gold conductive layer 42 is then deposited in a customary manner using lift-off technology, the structures of the photoresist mask of the lift-off process on the one hand and the etching mask on the other are matched to one another in such a way that the contact structure reliably overlaps the edges of the contact window KF, so that the edge regions of the contact with the thinner layers on the insulating layer 10 are spaced apart from the contact window.
- a diffusion of gold to the semiconductor layer through the barrier layer 32 is then reliably prevented under the edge regions of the metallic layer sequence. Diffusion over the contact window is prevented by the uniformly thick barrier layer.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01988040A EP1346403A2 (de) | 2000-12-22 | 2001-12-18 | Verfahren zur herstellung eines mikroelektronischen bauelements und danach hergestelltes bauelement |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10064479A DE10064479A1 (de) | 2000-12-22 | 2000-12-22 | Verfahren zur Herstellung eines mikroelektronischen Bauelements |
DE10064479.1 | 2000-12-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002052626A2 true WO2002052626A2 (de) | 2002-07-04 |
WO2002052626A3 WO2002052626A3 (de) | 2003-02-13 |
Family
ID=7668595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2001/014955 WO2002052626A2 (de) | 2000-12-22 | 2001-12-18 | Verfahren zur herstellung eines mikroelektronischen bauelements und danach hergestelltes bauelement |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1346403A2 (de) |
CN (1) | CN1222984C (de) |
DE (1) | DE10064479A1 (de) |
TW (1) | TW550715B (de) |
WO (1) | WO2002052626A2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106553992B (zh) * | 2015-09-25 | 2018-06-29 | 中芯国际集成电路制造(上海)有限公司 | 金属电极结构的制造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1989004057A1 (en) | 1987-10-20 | 1989-05-05 | Bell Communications Research, Inc. | Epitaxial intermetallic contact for compound semiconductors |
US5777389A (en) | 1995-07-27 | 1998-07-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including ohmic contact to-n-type GaAs |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2543518A1 (de) * | 1975-09-30 | 1977-04-07 | Licentia Gmbh | Halbleiterbauelement mit einem mehrschichtigen ohmschen anschlusskontakt |
JPS57183071A (en) * | 1981-05-06 | 1982-11-11 | Nec Corp | Formation of recess type fine multi-layer gate electrode |
JPS60123026A (ja) * | 1983-12-08 | 1985-07-01 | Toshiba Corp | 半導体装置の製造方法 |
JPH0722141B2 (ja) * | 1984-03-07 | 1995-03-08 | 住友電気工業株式会社 | 半導体素子の製造方法 |
JPS6298768A (ja) * | 1985-10-25 | 1987-05-08 | Nec Corp | 半導体素子用電極 |
US4994892A (en) * | 1986-10-09 | 1991-02-19 | Mcdonnell Douglas Corporation | Aluminum germanium ohmic contacts to gallium arsenide |
US5849630A (en) * | 1989-03-29 | 1998-12-15 | Vitesse Semiconductor Corporation | Process for forming ohmic contact for III-V semiconductor devices |
JP2661333B2 (ja) * | 1989-06-05 | 1997-10-08 | モトローラ・インコーポレーテツド | 金属被覆化プロセス処理方法 |
FR2697945B1 (fr) * | 1992-11-06 | 1995-01-06 | Thomson Csf | Procédé de gravure d'une hétérostructure de matériaux du groupe III-V. |
JP2606581B2 (ja) * | 1994-05-18 | 1997-05-07 | 日本電気株式会社 | 電界効果トランジスタ及びその製造方法 |
-
2000
- 2000-12-22 DE DE10064479A patent/DE10064479A1/de not_active Withdrawn
-
2001
- 2001-12-18 CN CNB018208916A patent/CN1222984C/zh not_active Expired - Fee Related
- 2001-12-18 EP EP01988040A patent/EP1346403A2/de not_active Withdrawn
- 2001-12-18 WO PCT/EP2001/014955 patent/WO2002052626A2/de not_active Application Discontinuation
- 2001-12-20 TW TW090131716A patent/TW550715B/zh not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1989004057A1 (en) | 1987-10-20 | 1989-05-05 | Bell Communications Research, Inc. | Epitaxial intermetallic contact for compound semiconductors |
US5777389A (en) | 1995-07-27 | 1998-07-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including ohmic contact to-n-type GaAs |
Non-Patent Citations (2)
Title |
---|
"Formation of extremely low resistance Ti/Pt/Au ohmic contacts to p-GaAs", APPL. PHYS. LETT., vol. 62, no. 22, 31 May 1993 (1993-05-31), pages 2801 - 2803 |
See also references of EP1346403A2 |
Also Published As
Publication number | Publication date |
---|---|
CN1222984C (zh) | 2005-10-12 |
EP1346403A2 (de) | 2003-09-24 |
WO2002052626A3 (de) | 2003-02-13 |
DE10064479A1 (de) | 2002-07-04 |
TW550715B (en) | 2003-09-01 |
CN1481579A (zh) | 2004-03-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE112017003754B4 (de) | Halbleitervorrichtung und verfahren zum herstellen einer halbleitervorrichtung | |
EP2015372B1 (de) | Halbleiterchip und Verfahren zur Herstellung eines Halbleiterchips | |
DE112018007009T5 (de) | Halbleitervorrichtung und Herstellungsverfahren für diese | |
DE102014115174B4 (de) | Halbleitervorrichtung mit einer korrosionsbeständigen metallisierung und verfahren zu ihrer herstellung | |
DE2436449C3 (de) | Schottky-Diode sowie Verfahren zu ihrer Herstellung | |
DE10048196A1 (de) | Verbindungshalbleiter-Bauteil und Verfahren zum Herstellen desselben | |
US6809352B2 (en) | Palladium silicide (PdSi) schottky electrode for gallium nitride semiconductor devices | |
DE10203801A1 (de) | Halbleiterbauelement und Verfahren zu dessen Herstellung | |
EP1794816A2 (de) | Verfahren zur herstellung eines d]nnfilmhalbleiterchips | |
EP1658643B1 (de) | Strahlungemittierendes halbleiterbauelement | |
DE102016104446B4 (de) | Kontakt mit geringem Widerstand für Halbleiter-Einheiten | |
WO2002052626A2 (de) | Verfahren zur herstellung eines mikroelektronischen bauelements und danach hergestelltes bauelement | |
EP1835528B1 (de) | Verfahren zur Herstellung eines Halbleiterbauelements mit einer metallischen Steuerelektrode und Halbleiterbauelement | |
DE102016122399A1 (de) | Gate-Struktur und Verfahren zu dessen Herstellung | |
DE1961492B2 (de) | Auf druck ansprechendes halbleiterbauelement und verfahren zum herstellen | |
DE19954319C1 (de) | Verfahren zum Herstellen von mehrschichtigen Kontaktelektroden für Verbindungshalbeiter und Anordnung | |
DE102014111482A1 (de) | Optoelektronischer Halbleiterchip und Verfahren zu dessen Herstellung | |
JP2630208B2 (ja) | オーミック電極 | |
JPH05218047A (ja) | 半導体装置の製造方法 | |
DE10308322B4 (de) | Verfahren zum Herstellen eines elektrischen Kontaktbereiches auf einer Halbleiterschicht und Bauelement mit derartigem Kontaktbereich | |
DE1236661B (de) | Halbleiteranordnung mit einem durch Einlegieren einer Metallpille erzeugten pn-UEbergang | |
JP2889240B2 (ja) | 化合物半導体装置及びその製造方法 | |
DE19647618C2 (de) | Gate-Metallisierung auf Feldeffekttransistoren | |
EP0292015A1 (de) | Leistungshalbleiterbauelement | |
DE19847368A1 (de) | Bipolartransistor mit Heteroübergang und Verfahren zu seiner Herstellung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
AK | Designated states |
Kind code of ref document: A3 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
REEP | Request for entry into the european phase |
Ref document number: 2001988040 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2001988040 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 018208916 Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 2001988040 Country of ref document: EP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
NENP | Non-entry into the national phase |
Ref country code: JP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: JP |