WO2002052626A3 - Verfahren zur herstellung eines mikroelektronischen bauelements und danach hergestelltes bauelement - Google Patents

Verfahren zur herstellung eines mikroelektronischen bauelements und danach hergestelltes bauelement Download PDF

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Publication number
WO2002052626A3
WO2002052626A3 PCT/EP2001/014955 EP0114955W WO02052626A3 WO 2002052626 A3 WO2002052626 A3 WO 2002052626A3 EP 0114955 W EP0114955 W EP 0114955W WO 02052626 A3 WO02052626 A3 WO 02052626A3
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WO
WIPO (PCT)
Prior art keywords
component
producing
produced according
semiconductor material
microelectronic
Prior art date
Application number
PCT/EP2001/014955
Other languages
English (en)
French (fr)
Other versions
WO2002052626A2 (de
Inventor
Klaus J Riepe
Herve Blanck
Wolfgang Doser
Original Assignee
United Monolithic Semiconduct
Klaus J Riepe
Herve Blanck
Wolfgang Doser
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Monolithic Semiconduct, Klaus J Riepe, Herve Blanck, Wolfgang Doser filed Critical United Monolithic Semiconduct
Priority to EP01988040A priority Critical patent/EP1346403A2/de
Publication of WO2002052626A2 publication Critical patent/WO2002052626A2/de
Publication of WO2002052626A3 publication Critical patent/WO2002052626A3/de

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Für die Herstellung eines Halbleiterbauelements in einem GaAs-Verbindungs-Halbleiter-Material, insbesondere einem Heterostruktur-GaAs-Halbleiter-Material, z. B. eines Hetero-Bipolar-Transistors, werden Herstellungsverfahren beschrieben, welche bei einfachem und kostengünstigem Prozessverlauf einen niederohmigen Kontaktwiderstend mit hoher Langzeitstabilität der Bauelelmenteigenschaften gewährleisten.
PCT/EP2001/014955 2000-12-22 2001-12-18 Verfahren zur herstellung eines mikroelektronischen bauelements und danach hergestelltes bauelement WO2002052626A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP01988040A EP1346403A2 (de) 2000-12-22 2001-12-18 Verfahren zur herstellung eines mikroelektronischen bauelements und danach hergestelltes bauelement

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10064479.1 2000-12-22
DE10064479A DE10064479A1 (de) 2000-12-22 2000-12-22 Verfahren zur Herstellung eines mikroelektronischen Bauelements

Publications (2)

Publication Number Publication Date
WO2002052626A2 WO2002052626A2 (de) 2002-07-04
WO2002052626A3 true WO2002052626A3 (de) 2003-02-13

Family

ID=7668595

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/014955 WO2002052626A2 (de) 2000-12-22 2001-12-18 Verfahren zur herstellung eines mikroelektronischen bauelements und danach hergestelltes bauelement

Country Status (5)

Country Link
EP (1) EP1346403A2 (de)
CN (1) CN1222984C (de)
DE (1) DE10064479A1 (de)
TW (1) TW550715B (de)
WO (1) WO2002052626A2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106553992B (zh) * 2015-09-25 2018-06-29 中芯国际集成电路制造(上海)有限公司 金属电极结构的制造方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57183071A (en) * 1981-05-06 1982-11-11 Nec Corp Formation of recess type fine multi-layer gate electrode
JPS60123026A (ja) * 1983-12-08 1985-07-01 Toshiba Corp 半導体装置の製造方法
JPS6298768A (ja) * 1985-10-25 1987-05-08 Nec Corp 半導体素子用電極
US4673593A (en) * 1984-03-07 1987-06-16 Sumitomo Electric Industries Ltd. Process for forming an ohmic electrode on a p-type III-V compound semiconductor
WO1989004057A1 (en) * 1987-10-20 1989-05-05 Bell Communications Research, Inc. Epitaxial intermetallic contact for compound semiconductors
EP0402061A2 (de) * 1989-06-05 1990-12-12 Motorola, Inc. Metallisierungsprozess
US4994892A (en) * 1986-10-09 1991-02-19 Mcdonnell Douglas Corporation Aluminum germanium ohmic contacts to gallium arsenide
US5770489A (en) * 1994-05-18 1998-06-23 Nec Corporation Method of making a compound semiconductor field-effect transistor
US5777389A (en) * 1995-07-27 1998-07-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including ohmic contact to-n-type GaAs
US5849630A (en) * 1989-03-29 1998-12-15 Vitesse Semiconductor Corporation Process for forming ohmic contact for III-V semiconductor devices

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2543518A1 (de) * 1975-09-30 1977-04-07 Licentia Gmbh Halbleiterbauelement mit einem mehrschichtigen ohmschen anschlusskontakt
FR2697945B1 (fr) * 1992-11-06 1995-01-06 Thomson Csf Procédé de gravure d'une hétérostructure de matériaux du groupe III-V.

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57183071A (en) * 1981-05-06 1982-11-11 Nec Corp Formation of recess type fine multi-layer gate electrode
JPS60123026A (ja) * 1983-12-08 1985-07-01 Toshiba Corp 半導体装置の製造方法
US4673593A (en) * 1984-03-07 1987-06-16 Sumitomo Electric Industries Ltd. Process for forming an ohmic electrode on a p-type III-V compound semiconductor
JPS6298768A (ja) * 1985-10-25 1987-05-08 Nec Corp 半導体素子用電極
US4994892A (en) * 1986-10-09 1991-02-19 Mcdonnell Douglas Corporation Aluminum germanium ohmic contacts to gallium arsenide
WO1989004057A1 (en) * 1987-10-20 1989-05-05 Bell Communications Research, Inc. Epitaxial intermetallic contact for compound semiconductors
US5849630A (en) * 1989-03-29 1998-12-15 Vitesse Semiconductor Corporation Process for forming ohmic contact for III-V semiconductor devices
EP0402061A2 (de) * 1989-06-05 1990-12-12 Motorola, Inc. Metallisierungsprozess
US5770489A (en) * 1994-05-18 1998-06-23 Nec Corporation Method of making a compound semiconductor field-effect transistor
US5777389A (en) * 1995-07-27 1998-07-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including ohmic contact to-n-type GaAs

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 007, no. 027 (E - 156) 3 February 1983 (1983-02-03) *
PATENT ABSTRACTS OF JAPAN vol. 009, no. 280 (E - 356) 8 November 1985 (1985-11-08) *
PATENT ABSTRACTS OF JAPAN vol. 011, no. 306 (E - 546) 6 October 1987 (1987-10-06) *
See also references of EP1346403A2 *

Also Published As

Publication number Publication date
DE10064479A1 (de) 2002-07-04
CN1481579A (zh) 2004-03-10
EP1346403A2 (de) 2003-09-24
TW550715B (en) 2003-09-01
CN1222984C (zh) 2005-10-12
WO2002052626A2 (de) 2002-07-04

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