WO2000052738A3 - Verfahren zur herstellung hochdotierter halbleiterbauelemente - Google Patents

Verfahren zur herstellung hochdotierter halbleiterbauelemente Download PDF

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Publication number
WO2000052738A3
WO2000052738A3 PCT/DE2000/000546 DE0000546W WO0052738A3 WO 2000052738 A3 WO2000052738 A3 WO 2000052738A3 DE 0000546 W DE0000546 W DE 0000546W WO 0052738 A3 WO0052738 A3 WO 0052738A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
highly doped
semiconductor components
glass layer
doped semiconductor
Prior art date
Application number
PCT/DE2000/000546
Other languages
English (en)
French (fr)
Other versions
WO2000052738A2 (de
Inventor
Richard Spitz
Alfred Goerlach
Barbara Will
Helga Uebbing
Roland Riekert
Christian Adamski
Original Assignee
Bosch Gmbh Robert
Richard Spitz
Alfred Goerlach
Barbara Will
Helga Uebbing
Roland Riekert
Christian Adamski
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert, Richard Spitz, Alfred Goerlach, Barbara Will, Helga Uebbing, Roland Riekert, Christian Adamski filed Critical Bosch Gmbh Robert
Priority to JP2000603076A priority Critical patent/JP2002538619A/ja
Priority to EP00912386A priority patent/EP1157413A2/de
Priority to US09/914,404 priority patent/US6806173B1/en
Publication of WO2000052738A2 publication Critical patent/WO2000052738A2/de
Publication of WO2000052738A3 publication Critical patent/WO2000052738A3/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66136PN junction diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2254Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Recrystallisation Techniques (AREA)
  • Thyristors (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

Es wird ein Verfahren zur Herstellung von Halbleiterbauelementen vorgeschlagen, bei dem in einem Wafer mindestens ein dotiertes Gebiet eingebracht wird, wobei zumindest auf einer der beiden Seiten eines Halbleiterwafers (1) eine mit Dotierstoff versehene feste Glasschicht (2; 4; 2, 3; 4, 5) aufgebracht wird, in einem weiteren Schritt der Wafer auf hohe Temperaturen erhitzt wird, so daß der Dotierstoff aus der Glasschicht tief in den Wafer eindringt zur Erzeugung des mindestens einen dotierten Gebiets (10; 11), und in einem weiteren Schritt die Glasschicht entfernt wird. Das Verfahren dient zur Herstellung homogener hoch dotierter Gebiete, wobei diese Gebiete auch beidseitig im Wafer eingebracht werden können und von unterschiedlichem Dotiertyp sein können.
PCT/DE2000/000546 1999-02-26 2000-02-25 Verfahren zur herstellung hochdotierter halbleiterbauelemente WO2000052738A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000603076A JP2002538619A (ja) 1999-02-26 2000-02-25 高度にドーピングされた半導体構造部品の製造方法
EP00912386A EP1157413A2 (de) 1999-02-26 2000-02-25 Verfahren zur herstellung hochdotierter halbleiterbauelemente
US09/914,404 US6806173B1 (en) 1999-02-26 2000-02-25 Method for producing highly doped semiconductor components

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19908400.9 1999-02-26
DE19908400A DE19908400A1 (de) 1999-02-26 1999-02-26 Verfahren zur Herstellung hochdotierter Halbleiterbauelemente

Publications (2)

Publication Number Publication Date
WO2000052738A2 WO2000052738A2 (de) 2000-09-08
WO2000052738A3 true WO2000052738A3 (de) 2000-12-21

Family

ID=7898991

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/000546 WO2000052738A2 (de) 1999-02-26 2000-02-25 Verfahren zur herstellung hochdotierter halbleiterbauelemente

Country Status (5)

Country Link
US (1) US6806173B1 (de)
EP (1) EP1157413A2 (de)
JP (1) JP2002538619A (de)
DE (1) DE19908400A1 (de)
WO (1) WO2000052738A2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10058031B4 (de) * 2000-11-23 2007-11-22 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Bildung leicht dotierter Halogebiete und Erweiterungsgebiete in einem Halbleiterbauelement
US7208396B2 (en) * 2002-01-16 2007-04-24 Tegal Corporation Permanent adherence of the back end of a wafer to an electrical component or sub-assembly
US20080083611A1 (en) * 2006-10-06 2008-04-10 Tegal Corporation High-adhesive backside metallization
US7560355B2 (en) * 2006-10-24 2009-07-14 Vishay General Semiconductor Llc Semiconductor wafer suitable for forming a semiconductor junction diode device and method of forming same
US7999268B2 (en) * 2007-07-27 2011-08-16 Auburn University Low temperature impurity doping of silicon carbide
US8808513B2 (en) * 2008-03-25 2014-08-19 Oem Group, Inc Stress adjustment in reactive sputtering
US20090246385A1 (en) * 2008-03-25 2009-10-01 Tegal Corporation Control of crystal orientation and stress in sputter deposited thin films
US8058159B2 (en) * 2008-08-27 2011-11-15 General Electric Company Method of making low work function component
DE102008055515A1 (de) * 2008-12-12 2010-07-15 Schott Solar Ag Verfahren zum Ausbilden eines Dotierstoffprofils
US8482375B2 (en) * 2009-05-24 2013-07-09 Oem Group, Inc. Sputter deposition of cermet resistor films with low temperature coefficient of resistance
DE102011000973A1 (de) * 2011-02-28 2012-08-30 Schott Solar Ag Verfahren zur flächigen Gasphasenbehandlng von Halbleiterbauelementen
DE102012204346A1 (de) * 2012-03-19 2013-09-19 Gebr. Schmid Gmbh Verfahren zur Herstellung eines beidseitig unterschiedlich dotierten Halbleiterwafers

Citations (4)

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FR2145772A5 (en) * 1971-07-09 1973-02-23 Radiotechnique Compelec Semiconductor component prodn - by doping silicon with antimony for prodn of various regions
US3914138A (en) * 1974-08-16 1975-10-21 Westinghouse Electric Corp Method of making semiconductor devices by single step diffusion
US4092185A (en) * 1975-07-26 1978-05-30 International Computers Limited Method of manufacturing silicon integrated circuits utilizing selectively doped oxides
DE3815615A1 (de) * 1988-05-07 1989-11-16 Bosch Gmbh Robert Verfahren zur herstellung einer hochsperrenden leistungsdiode

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FR2246066B1 (de) * 1973-09-17 1976-12-31 Ibm
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US4104091A (en) * 1977-05-20 1978-08-01 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Application of semiconductor diffusants to solar cells by screen printing
DE3037316C2 (de) * 1979-10-03 1982-12-23 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Verfahren zur Herstellung von Leistungsthyristoren
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FR2145772A5 (en) * 1971-07-09 1973-02-23 Radiotechnique Compelec Semiconductor component prodn - by doping silicon with antimony for prodn of various regions
US3914138A (en) * 1974-08-16 1975-10-21 Westinghouse Electric Corp Method of making semiconductor devices by single step diffusion
US4092185A (en) * 1975-07-26 1978-05-30 International Computers Limited Method of manufacturing silicon integrated circuits utilizing selectively doped oxides
DE3815615A1 (de) * 1988-05-07 1989-11-16 Bosch Gmbh Robert Verfahren zur herstellung einer hochsperrenden leistungsdiode

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Also Published As

Publication number Publication date
JP2002538619A (ja) 2002-11-12
US6806173B1 (en) 2004-10-19
EP1157413A2 (de) 2001-11-28
DE19908400A1 (de) 2000-09-07
WO2000052738A2 (de) 2000-09-08

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