CN1179011A - 半导体器件封装 - Google Patents
半导体器件封装 Download PDFInfo
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Abstract
一种半导体器件封装包括多列的多个内引线,其最外端内引线具有相应的虚拟块引线,从它们的端部延伸并与它们形成为整体。该虚拟块引线形成时带有一斜角并且在它的侧面呈锯齿状。本封装包括边杆,该连杆具有自此而延伸的部件,所述延伸部件被分离开以便在它们之间具有一定的空间并且形成时带有一斜角。依据本发明,连杆的延伸部件在它们的侧面呈锯齿状。
Description
本发明一般地涉及半导体器件封装,尤其是涉及在其中无形成气穴或空穴可能性,并且具有很高可靠性的半导体器件封装。
具有其上装贴有一个或多个芯片的管芯焊垫的半导体器件封装约占总的半导体器件封装的产量的70~80%。它们能够通过使用现有的生产设备借助于一种简单的方法被制造,按照这一点,这种类型的封装是很便利的,但是,另一方面,在批量生产中,它们同样有一些问题,因此,在传递模型中,当用诸如封装树脂这样的密封剂,比如是环氧树脂模塑化合物,来对它们的装配体进行密封时,在接近引线框或者是电间连部分会产生涡流,因而在所得的密封封装体中导致气穴或是空穴的形成,位于接近引线框或电间连部分的气穴或空穴会引起封装失效,比如电短路。
图1是常规半导体器件封装的分解透视图;图2是图1中沿线′2-2′切开的剖视图;和图3是图1中沿线′3-3′切开的剖视图。
参照图1至3,半导体器件封装100有芯片10,管芯焊垫30和内部引线50。通过使用粘结剂20比如Ag-环氧树脂粘结剂,芯片10贴装在管芯焊垫30的上表面。通过键合线70,芯片10电连接至内部引线50。通过连杆40,管芯焊垫30机械地连接到边架上(未示出)。封装100还具有密封剂,它覆盖着芯片10,管芯焊垫30,连杆40,内部引线50,以及包括键合线70的电连接部分以形成封装体80。密封剂可以是封装树脂比如环氧树脂模塑化合物。和内引线50的每根引线分别相对应而与之形成为整体并且从封装体80中暴露出来的外部引线60已经形成,比如是具有适合于安装在外部器件上的J-形结构。
图4描述了封装组件密封期间在模型内封装树脂的流动。
参照图4,在由上模具310以及下模具410所确定的凹腔312,412中,用从下模具410的入口414所注入的封装树脂对封装组件进行密封。
箭头指示出凹腔内封装树脂的流动方向。当封装树脂与芯片10和管芯焊垫30相碰撞时,它的速度下降,而接近模具310,410内壁的封装树脂则保持其原始速度。这样在凹腔312,412内便会引起封装树脂的流动速度的偏差,该偏差即产生封装树脂流动涡流,并因此在所得的封装体80中形成了气穴或空穴。这种现象在封装组件包含有更大的芯片时显得更加突出。
当该封装在接受可靠性试验时,其中该试验在升高的温度以及升高的压力下进行,水蒸汽被施加到封装体中,如果封装里面含有气穴或空穴,水蒸汽便会集中在气穴或是空穴内,随后进行膨胀,这样对封装体80的机械强度会有不利的影响并且使封装的可靠性变坏。
另外,由于封装体具有一多管脚引线框,封装树脂与内部引线(图1中的50)相碰撞,并且同样也产生涡流,这样在接近或是位于内部引线处会形成气穴,导致电连接内部引线与芯片的键合线的电短路。
本发明提供了高可靠性的半导体器件封装。
本发明提供了高可靠性的半导体器件封装,在模制封装体中没有气穴。
依据本发明的半导体器件封装包括多列的多个内引线,其最外端的内引线具有一自它们的端部延伸出的相应的虚拟块引线(dummy blocklead)并与它们形成整体。依据本发明,该虚拟块引线形成时带有一斜角,并在其侧面呈锯齿状。
依据本发明半导体器件封装包括连杆,该连杆具有自此而为扩展的部分,所述扩展部分被分成若干个部件以便在它们之间有一定的空间并被形成面带有一斜角,依据本发明,连杆的扩展部分在它们的侧面呈锯齿状。
参照下列详细的说明并连带附图,本发明的上述以及各种其他的特征和优点将会更容易地理解。在附图中,同样的标号表示相同的结构单元,并且,其中:
图1是表示常规半导体器件封装的分解透视图;
图2是图1中沿线′2-2′所取的剖视图;
图3是图1中沿线′3-3′所取的剖视图;
图4描述了在模制过程中模型内封装树脂的流动;
图5是依据本发明的半导体器件的分解透视图;
图6是图5中沿线′6-6′所取的剖视图;
图7是图5中沿线′7-7′所取的剖视图;
图8是图5中沿线′8-8′所取的剖视图;
图9和10描述了在模制过程中模型内封装树脂的流动。
参照附图,下文正将更详细地描述本发明,其中,本发明的优选实施例即被说明。尽管如此,本发明能够以许多不同的形式来实现,而且并不应该认为只局限于现在所阐述的实施例;相反,提供这些实施例以便使得本公开将更彻底和完全,并将本发明的范围充分地传达给本领域技术人员。在附图中,为清晰起见,层和区域的厚度被放大了,相同的标号始终表示同样的部件。
图5是依据本发明的半导体器件的分解透视图;图6是图5中沿线′6-6′所取的剖视图;图7是图5中沿线′7-7′所取的剖视图;和图8是图5中沿线′8-8′所取的剖视图。
参照图5至8,半导体器件封装200包括芯片110和贴装在芯片110的下表面的管芯焊垫130。半导体器件封装200包含有数列多个内引线150,152,152′,它们与管芯焊垫130相隔开。
依据本发明,最外端内引线152仅仅会在接近模具(图9中的420)的注入口(图9中的424)的位置形成。另外,封装可能还包括其它的位于管芯焊垫130的反边的最外端内引线152′,它正对着入口(图9中的424)。
列的最外端内引线152,152′在它们的一端具有内虚拟块引线,所述虚拟块引线154,154′自端部延伸出。
封装200还具有电连接装置170,以便将芯片110电连接至内引线150,152,152′。封装200还包括连杆140,它与管芯焊垫130成为一个整体;密封剂180,它覆盖着芯片110,内引线150,152,152′,154,154′电连接装置170及连杆140以形成一封装体;和外部引线,它与内引线150,152,152′形成一个整体,并且从密封剂180中暴露出。
对于封装200,通过使用粘结剂120,比如Ag-环氧树脂粘结剂,芯片110贴装在管芯焊垫130的上表面,通过键合线170,芯片110同样电连接至内引线150,152,152′。通过连杆140管芯焊垫130连接到引线框的边架上(未示出),连杆140形成于两个相对的侧端。
在管芯焊垫130的相对的侧边多个内引线150,152形成两列,或者,在管芯焊垫130的每一边,它们可能形成4列。可能有4个最外端内引线152,152,152′,152′,每一个位于封装体180的相应的角部。位于注入口(图9中的424)附近的两个最外端内引线152具有自其扩展的虚拟块引线154,其中封树脂被注入注入口。另外两个位于正对着注入口(图9中的424)的地方的最外端内引线152′同样可能具有自其扩展的虚拟块引线154′。
虚拟块引线154或154′可以朝着连杆140的方向延伸。虚拟块引线154或154′在它们的侧面可以呈锯齿状,并且可在被形成面带有一个相对于水平线成大约30到40度的斜角,该倾斜的虚拟块引线154,154′可以用冲压的方法来制成。尽管图5所示为向上倾斜的虚拟块引线154(154′),虚拟块引线154(154′)也可以向下倾斜,虚拟块引线154或154′具有相同的倾斜方向,而虚拟块引线154′可以有与虚拟块引线154相反方向的倾斜。
依据本发明,封装可以有两个相对的连杆140,140′,当它被密封在模具中时,连杆140在即将接近注入口(图9中的424)位置形成。
连杆140从管芯焊垫130处向外(或者是向着封装体的内壁)延伸,并且扩展部分140A被分成若干的部件以便具有空间140B。该被分开的部件相互之间连成为整体并与连杆140相连接。扩展部分140A倾斜30至40度而且在其侧面呈锯齿状。该倾斜的扩展部分140A可以通过冲压的方法制成。扩展部分140A具有突起140C,140C在它们的侧面可以呈锯齿状。
另一个正对着边杆140的连杆140′同样也会从管芯焊垫130处向外延伸。扩展部分140A′被分成若干个部件以便具有空间140B′。该被分开的部件相互之间连成为整体并与连杆140′相连接。140A′部分倾斜30至40度而且在它们的侧面呈锯齿状。该扩展的倾斜部分140A′可以通过冲压的方法制成。扩展的倾斜部分140A′具有突起140C′,140C′在它们的侧面可呈锯齿状。
扩展部分140A或者是140′可以倾斜因而其被分开的部件具有相同的倾斜方向。反之扩展部分140A可以具有与其对面的扩展部分140′的倾斜方向相反的倾斜方向。
封装200同样还有密封剂,比如是环氧树脂封装树脂,它覆盖着芯片110,管芯焊垫130,连杆140,140′,140A,140A′,140B,140B′,140C,140C′,内引线150,152,152′及包括键合线170的电连接部分以便形成封装体180。和内引线150的多根引线分别相对应而与之形成为整体并且从封装体180向外延伸的外引线160已经形成,且具有适合于安装在外部器件上的J-形结构。
图9和10描述了图5中所示的依据本发明的半导体器件封装的密封期间模具内封装树脂的流动。
参照图9和10,图9描述了从图6中所取的截面的封装树脂的流动。而图10则描述了从图9中所取的截面的封装树脂的流动。正如从图9和10中所看到的,通过让树脂经过空间140B,可以有效地防止涡流的形成。由于它们具有同关于图4中所描述的模具那样相同的结构,模具320,420的详细结构的描述将被省略。
倾斜的被扩展的连杆部分140A以一定的倾斜方向,非水平方向而导引着封装树脂的流动,因此它能够有效地防止封装树脂与管芯焊垫130和芯片110相碰撞,及防止由于相撞而引起的速度的突然下降。这样即避免了涡流的形成,因而最终在封装体中避免了气穴的形成。
另外,虚拟块引线154同样也减小了封装树脂的速度,因而在芯片110和管芯焊垫130所位于的地方以及在没有任何封装元件的地方封装树脂的流动速度都是一致的。换句话说,流动于模具凹腔中的封装树脂的流动速度没有或者只有非常小的变化,因此,位于或是接近于引线框150,152,152′处的气穴能够被有效地防止。
本发明可以应用于引线装在芯片上(LOC)的封装,其中内引线直接与芯片相键合,同样也可电连接至芯片的焊盘上。另外,不必制作外引线,只要外引线能够电连接至外部电子器件上即可。
尽管上文已经详细地描述了本发明的优选实施例,应该清楚地理解到有关此处所述的基本的发明构思的许多变化和/或修改可对本领域技术人员是很明了的,但仍将不脱离所附权利要求中所限定的本发明的精神以及范围。
Claims (17)
1.一种半导体器件封装,其特征在于包括:
一半导体芯片;
一管芯焊垫,所述芯片贴装在其上面;
数列多个内引线,它们电连接至所述芯片并且与所述管芯焊垫隔离开;
内虚拟块引线,与最外端内引线连成为整体并且自此而延伸;
电连接装置,用于将所述芯片电连接至所述内引线;
连杆,与所述管芯焊垫形成为整体;
密封剂,覆盖所述芯片,内引线,内虚拟块引线,电连接装置及连杆以形成封装体;和
外引线,和所述内引线的每根引线分别相对应而与之形成为整体,并且从所述封装体向外延伸。
2.根据权利要求1所述的半导体器件封装,其特征在于所述数列内引线以一定的间距形成于所述管芯焊垫的每一边。
3.根据权利要求1所述的半导体器件封装,其特征在于它包括两个相对的边部件,当放置于传递模具中时具有一封装树脂注入的入口,所述边部件中的一个接近该入口,而另一个则位于所述管芯焊垫的相对的那边,并且其中所述内虚拟块引线形成于接近所述入口的所述边部件处。
4.根据权利要求3所述的半导体器件封装,其特征在于还包括内虚拟块引线,它形成于另一个边部件处。
5.根据权利要求3所述的半导体器件封装,其特征在于形成所述内虚拟块引线以便使它们延伸而互相接近。
6.根据权利要求4所述的半导体器件封装,其特征在于所述内虚拟块引线被形成以便使它们延伸而互相接近。
7.根据权利要求3所述的半导体器件封装,其特征在于所述内虚拟块引线在它们的侧面呈锯齿状。
8.根据权利要求3所述的半导体器件封装,其特征在于所述内虚拟块引线被形成而带有一斜角。
9.根据权利要求4所述的半导体器件封装,其特征在于所述内虚拟块引线在它们的侧面呈锯齿状并且被形成而带有一斜角。
10.根据权利要求9所述的半导体器件封装,其特征在于位于接近所述入口的所述边部件处的所有的所述内虚拟引线具有相同的倾斜方向,而在另一个边部件处它们具有和内虚拟引线相反的倾斜方向。
11.根据权利要求1所述的半导体器件封装,其特征在于所述连杆具有向着所述封装体的内壁而延伸的部分并且该延伸部分被分成若干个部件以便在所述部件之间具有一定的空间,所述若干个部件相互之间仍然成为整体。
12.根据权利要求1所述的半导体器件封装,其特征在于所述连杆具有自其延伸的突起部分。
13.根据权利要求11所述的半导体器件封装,其特征在于所述延伸部分在它的侧面呈锯齿状。
14.根据权利要求12所述的半导体器件封装,其特征在于所述突起部分在它们的侧面呈锯齿状。
15.根据权利要求11所述的半导体器件封装,其特征在于包括两个相对边部件,当放置于传递模具中时具有一封装树脂注入的入口,所述边部件中的一个接近该入口,而另一个则位于所述管芯焊垫的相对的那边,并且其中所述连杆形成于接近所述入口的所述边部件处。
16.根据权利要求15所述的半导体器件封装,其特征在于还包括连杆,它形成于另一个边部件处。
17.根据权利要求15所述的半导体器件封装,其特征在于所述连杆具有形成时带有斜角的延伸部分,而且该延伸部分被分成若干个部件以便在该部件之间具有一定的空间,并且位于接近该入口的所述边部件处的所有的被分开部件具有相同的倾斜方向,而在另一个边部件处它们具有和被分开部件相反的倾斜方向。
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KR44028/96 | 1996-10-04 | ||
KR1019960044028A KR100195513B1 (ko) | 1996-10-04 | 1996-10-04 | 반도체 칩 패키지 |
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JP (1) | JP3155729B2 (zh) |
KR (1) | KR100195513B1 (zh) |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100373717C (zh) * | 2004-07-09 | 2008-03-05 | 索尼株式会社 | 搭载半导体元件的引线框架和使用该引线框架的半导体器件 |
CN103395158A (zh) * | 2005-11-04 | 2013-11-20 | 东和株式会社 | 电子器件的树脂封固成形装置 |
CN107204296A (zh) * | 2016-03-18 | 2017-09-26 | 富士电机株式会社 | 模制产品的制造方法及模制产品 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6515359B1 (en) | 1998-01-20 | 2003-02-04 | Micron Technology, Inc. | Lead frame decoupling capacitor semiconductor device packages including the same and methods |
US6329705B1 (en) * | 1998-05-20 | 2001-12-11 | Micron Technology, Inc. | Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes |
TW419810B (en) * | 1998-06-18 | 2001-01-21 | Hitachi Ltd | Semiconductor device |
JP3105200B2 (ja) * | 1998-10-07 | 2000-10-30 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
US6278175B1 (en) | 2000-01-21 | 2001-08-21 | Micron Technology, Inc. | Leadframe alteration to direct compound flow into package |
IT1319406B1 (it) * | 2000-04-28 | 2003-10-10 | St Microelectronics Srl | Involucro protettivo per il contenimento di un circuito integrato susemiconduttore. |
US6414379B1 (en) * | 2000-09-29 | 2002-07-02 | Siliconware Precision Industries Co., Ltd. | Structure of disturbing plate having down set |
JP2006066008A (ja) * | 2004-08-30 | 2006-03-09 | Hitachi Global Storage Technologies Netherlands Bv | 磁気ディスクおよび磁気ディスクの製造方法 |
US7927923B2 (en) * | 2006-09-25 | 2011-04-19 | Micron Technology, Inc. | Method and apparatus for directing molding compound flow and resulting semiconductor device packages |
CN108735701B (zh) * | 2017-04-13 | 2021-12-24 | 恩智浦美国有限公司 | 具有用于包封期间的毛刺缓解的虚设引线的引线框架 |
JP7109347B2 (ja) * | 2018-12-03 | 2022-07-29 | 三菱電機株式会社 | 半導体装置および電力変換装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61168251A (ja) * | 1985-01-21 | 1986-07-29 | Mitsubishi Electric Corp | 半導体装置 |
JPS63265454A (ja) * | 1987-12-24 | 1988-11-01 | Nec Corp | 半導体装置 |
JPH01192154A (ja) * | 1988-01-28 | 1989-08-02 | Nippon Motoroola Kk | リードフレーム |
IT1239644B (it) * | 1990-02-22 | 1993-11-11 | Sgs Thomson Microelectronics | Struttura di supporto degli adduttori perfezionata per contenitori di dispositivi integrati di potenza |
JPH0468557A (ja) * | 1990-07-10 | 1992-03-04 | Hitachi Ltd | 半導体装置及びそのモールド用金型 |
JPH04239164A (ja) * | 1991-01-11 | 1992-08-27 | Fujitsu Ltd | 半導体装置 |
JP3006285B2 (ja) * | 1991-05-27 | 2000-02-07 | 株式会社日立製作所 | 半導体装置 |
US5293065A (en) * | 1992-08-27 | 1994-03-08 | Texas Instruments, Incorporated | Lead frame having an outlet with a larger cross sectional area than the inlet |
JPH0846119A (ja) * | 1994-08-02 | 1996-02-16 | Sony Corp | リードフレームおよびこれを用いた半導体装置 |
-
1996
- 1996-10-04 KR KR1019960044028A patent/KR100195513B1/ko not_active IP Right Cessation
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1997
- 1997-07-04 DE DE19728617A patent/DE19728617C2/de not_active Expired - Fee Related
- 1997-07-17 FR FR9709063A patent/FR2754387B1/fr not_active Expired - Fee Related
- 1997-07-18 CN CN971122733A patent/CN1094257C/zh not_active Expired - Fee Related
- 1997-07-19 TW TW086110276A patent/TW345707B/zh not_active IP Right Cessation
- 1997-09-03 JP JP23811697A patent/JP3155729B2/ja not_active Expired - Fee Related
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Cited By (6)
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CN100373717C (zh) * | 2004-07-09 | 2008-03-05 | 索尼株式会社 | 搭载半导体元件的引线框架和使用该引线框架的半导体器件 |
CN103395158A (zh) * | 2005-11-04 | 2013-11-20 | 东和株式会社 | 电子器件的树脂封固成形装置 |
CN103395157A (zh) * | 2005-11-04 | 2013-11-20 | 东和株式会社 | 电子器件的树脂封固成形装置 |
CN103395157B (zh) * | 2005-11-04 | 2015-09-02 | 东和株式会社 | 电子器件的树脂封固成形装置 |
CN103395158B (zh) * | 2005-11-04 | 2015-10-07 | 东和株式会社 | 电子器件的树脂封固成形装置 |
CN107204296A (zh) * | 2016-03-18 | 2017-09-26 | 富士电机株式会社 | 模制产品的制造方法及模制产品 |
Also Published As
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KR19980025782A (ko) | 1998-07-15 |
KR100195513B1 (ko) | 1999-06-15 |
DE19728617A1 (de) | 1998-04-09 |
JPH10112518A (ja) | 1998-04-28 |
FR2754387A1 (fr) | 1998-04-10 |
DE19728617C2 (de) | 2002-10-31 |
CN1094257C (zh) | 2002-11-13 |
US5932923A (en) | 1999-08-03 |
FR2754387B1 (fr) | 2003-08-08 |
TW345707B (en) | 1998-11-21 |
JP3155729B2 (ja) | 2001-04-16 |
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