IT1319406B1 - Involucro protettivo per il contenimento di un circuito integrato susemiconduttore. - Google Patents

Involucro protettivo per il contenimento di un circuito integrato susemiconduttore.

Info

Publication number
IT1319406B1
IT1319406B1 IT2000MI000942A ITMI20000942A IT1319406B1 IT 1319406 B1 IT1319406 B1 IT 1319406B1 IT 2000MI000942 A IT2000MI000942 A IT 2000MI000942A IT MI20000942 A ITMI20000942 A IT MI20000942A IT 1319406 B1 IT1319406 B1 IT 1319406B1
Authority
IT
Italy
Prior art keywords
integrated circuit
lead frame
susemiconductor
containment
protective enclosure
Prior art date
Application number
IT2000MI000942A
Other languages
English (en)
Inventor
Roberto Tiziani
Marzio Terzoli
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2000MI000942A priority Critical patent/IT1319406B1/it
Publication of ITMI20000942A0 publication Critical patent/ITMI20000942A0/it
Priority to US09/844,506 priority patent/US6593665B2/en
Publication of ITMI20000942A1 publication Critical patent/ITMI20000942A1/it
Application granted granted Critical
Publication of IT1319406B1 publication Critical patent/IT1319406B1/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
IT2000MI000942A 2000-04-28 2000-04-28 Involucro protettivo per il contenimento di un circuito integrato susemiconduttore. IT1319406B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2000MI000942A IT1319406B1 (it) 2000-04-28 2000-04-28 Involucro protettivo per il contenimento di un circuito integrato susemiconduttore.
US09/844,506 US6593665B2 (en) 2000-04-28 2001-04-27 Protective envelope for a semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2000MI000942A IT1319406B1 (it) 2000-04-28 2000-04-28 Involucro protettivo per il contenimento di un circuito integrato susemiconduttore.

Publications (3)

Publication Number Publication Date
ITMI20000942A0 ITMI20000942A0 (it) 2000-04-28
ITMI20000942A1 ITMI20000942A1 (it) 2001-10-28
IT1319406B1 true IT1319406B1 (it) 2003-10-10

Family

ID=11444942

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2000MI000942A IT1319406B1 (it) 2000-04-28 2000-04-28 Involucro protettivo per il contenimento di un circuito integrato susemiconduttore.

Country Status (2)

Country Link
US (1) US6593665B2 (it)
IT (1) IT1319406B1 (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1075022A1 (en) * 1999-08-04 2001-02-07 STMicroelectronics S.r.l. Offset edges mold for plastic packaging of integrated semiconductor devices
DE102004042145A1 (de) * 2004-08-31 2006-03-02 Infineon Technologies Ag Chipmodul
DE102005038755B4 (de) * 2005-08-17 2016-03-10 Robert Bosch Gmbh Mikromechanisches Bauelement
US11862540B2 (en) * 2020-03-06 2024-01-02 Stmicroelectronics Sdn Bhd Mold flow balancing for a matrix leadframe

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01268159A (ja) 1988-04-20 1989-10-25 Nec Corp 樹脂封止半導体装置及び成型用金型
KR100195513B1 (ko) * 1996-10-04 1999-06-15 윤종용 반도체 칩 패키지

Also Published As

Publication number Publication date
ITMI20000942A1 (it) 2001-10-28
US6593665B2 (en) 2003-07-15
US20020050630A1 (en) 2002-05-02
ITMI20000942A0 (it) 2000-04-28

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