JP3105200B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法Info
- Publication number
- JP3105200B2 JP3105200B2 JP10285222A JP28522298A JP3105200B2 JP 3105200 B2 JP3105200 B2 JP 3105200B2 JP 10285222 A JP10285222 A JP 10285222A JP 28522298 A JP28522298 A JP 28522298A JP 3105200 B2 JP3105200 B2 JP 3105200B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- resin
- shielding plate
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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Description
装置およびその製造方法、特に、LOC(Lead O
n Chip)型の半導体装置およびその製造方法に関
するものである。
の機能を含めるために、そのサイズが大型化する傾向に
ある。逆に、半導体パッケージの動向としては電気製品
高密度実装化背景により小型化を求められている。
イスを収容しなければならなくなり、LOC(Lead
On Chip)パッケージが提案されている。
可塑性絶縁性両面接着テープを介してリードを固定し、
このリードとデバイス表面に設けられている電極とを接
続し、これらデバイス、リードを樹脂にて封止する技術
である。
74234号公報に開示されているものがある。
LOCパッケージでは半導体素子の表面にリードが存在
しているため、樹脂封止時に半導体素子の表面と裏面と
で樹脂の注入速度が異なる場合がある。このため、樹脂
の注入速度の不均一性に起因するチップ上面のボイドの
発生が問題となっている。
に、本願発明の半導体装置は、表面に複数の電極を有す
る半導体素子と、半導体素子の表面に絶縁層を介して固
着されたインナーリードと、半導体素子の第1の側辺近
傍に配置される遮蔽板と、半導体素子、インナーリー
ド、遮蔽板を封止する封止樹脂とを含み、封止樹脂は、
半導体素子の第1の側辺と対向する半導体素子の第2の
側辺方向から注入される。
施形態について説明する。
半導体装置の上面図、図2は図1のA−A’における断
面図、図3は図1のB−B’における断面図、図4は樹
脂の注入状態を示す図である。
れている。この半導体素子1の表面にインナーリード3
が絶縁テープ4により固定されている。絶縁テープとし
ては、表裏面に接着剤の塗布されたポリイミドテープな
どが用いられる。インナーリード3の先端と電極2とは
導電性のワイヤ5により接続されている。導電性のワイ
ヤとしては例えば金線が用いられる。
3’に接続されている。また、この遮蔽板5には、半導
体素子1の下面側に折り曲げられた傾斜部6’が設けら
れている。これら半導体素子1、インナーリード3、
3’、遮蔽板6は樹脂7により封止されている。
する。半導体装置はモールド上金型10とモールド下金
型11とにより挟まれて固定される。この上下金型に挟
まれた空間にゲート部12から樹脂が注入される。ゲー
ト部12は下金型11に設けられている。この注入され
た樹脂13は半導体素子1まで達し、その後半導体素子
1の上面と下面とに分かれて注入が進んでいく。
ード3が存在するため、抵抗が大きくなり、流速が遅く
なる。このため、樹脂7は下面の方が早く注入される。
ここで、遮蔽板6がゲート12が設けられる側と反対側
に設けられているため、半導体素子1の下面を流れてき
た樹脂13がこの遮蔽板5に到達すると、流路が狭くな
り、それ以降は半導体素子1の上面の注入速度が速くな
る。
封止時の注入速度を半導体素子の上下で最終的に均一に
することが可能となり、半導体素子上面側のボイド発生
を低減できる。
られており、樹脂はこの傾斜部6’を境に注入速度が遅
くなり、半導体素子の上面側を流れる樹脂と下面側を流
れる樹脂との最終的な速度をより細かく調整することが
できる。
図5、図6を用いて説明する。
から見た図、図6は図5におけるA−A’の断面図であ
る。
れている。この半導体素子1の表面にインナーリード3
が絶縁テープ4により固定されている。絶縁テープとし
ては、表裏面に接着剤の塗布されたポリイミドテープな
どが用いられる。インナーリード3の先端と電極2とは
導電性のワイヤ5により接続されている。導電性のワイ
ヤとしては例えば金線が用いられる。
レール部15に、接続部16により接続されている。こ
の遮蔽板には下方向に折り曲げられた傾斜部13’が設
けられている。この傾斜部13’は遮蔽板13の形状を
形成した後、プレス金型の曲げ加工により形成すること
ができる。
入れ、樹脂を注入する場合の樹脂の流れの様子が図6に
示されている。
型10とモールド下金型11とにより挟まれて固定され
る。この上下金型に挟まれた空間にゲート部12から樹
脂7が注入される。ゲート部12は下金型11に設けら
れている。この注入された樹脂7は半導体素子1まで達
し、その後半導体素子1の上面と下面とに分かれて注入
が進んでいく。
ード3が存在するため、抵抗が大きくなり、流速が遅く
なる。このため、樹脂7は下面の方が早く注入される。
ここで、遮蔽板13がゲート12が設けられる側と反対
側に設けられているため、半導体素子1の下面を流れて
きた樹脂7がこの遮蔽板13に到達すると、流路が狭く
なり、それ以降は半導体素子1の上面の注入速度が速く
なる。
脂封止時の注入速度を半導体素子の上下で最終的に均一
にすることが可能となり、半導体素子上面側のボイド発
生を低減できる。
けた場合、樹脂はこの傾斜部5’を境に注入速度が遅く
なり、半導体素子の上面側を流れる樹脂と下面側を流れ
る樹脂との最終的な速度をより細かく調整することがで
きる。
びサイドレール15に接続されているため、樹脂注入時
の注入圧力による遮蔽板の位置ずれを抑制することがで
きる。
半導体装置の第3の実施形態について説明する。図3、
図4において、第1実施形態および第2実施形態と同一
構成については同一符号を付し、その説明を省略する。
A−A’における断面図である。
の実施形態において説明した半導体装置に加えて、図7
および図8に示すようにゲート部12近傍にも第2の遮
蔽板17が設けられている。この第2の遮蔽板17はタ
イバー14およびサイドレール15に接続されている。
また、この第2の遮蔽板にはスリット18が設けられて
いる。
の樹脂の流れを図8を用いて説明する。
型10とモールド下金型11とにより挟まれて固定され
る。この上下金型に挟まれた空間にゲート部12から樹
脂7が注入される。ゲート部12は下金型11に設けら
れている。この注入された樹脂7は半導体素子1まで達
し、その後半導体素子1の上面と下面とに分かれて注入
が進んでいくが、半導体素子1の上面には、ゲート12
側に設けられた第2の遮蔽板17のスリット18を通り
注入されていく。
ード3が存在するため、抵抗が大きくなり、流速が遅く
なる。このため、樹脂7は下面の方が早く注入される。
ここで、遮蔽板13がゲート12が設けられる側と反対
側に設けられているため、半導体素子1の下面を流れて
きた樹脂7がこの遮蔽板13に到達すると、流路が狭く
なり、それ以降は半導体素子1の上面の注入速度が速く
なる。
脂封止時の注入速度を半導体素子の上下で最終的に均一
にすることが可能となり、半導体素子上面側のボイド発
生を低減できる。
けた場合、樹脂はこの傾斜部5’を境に注入速度が遅く
なり、半導体素子の上面側を流れる樹脂と下面側を流れ
る樹脂との最終的な速度をより細かく調整することがで
きる。
びサイドレール15に接続されているため、樹脂注入時
の注入圧力による遮蔽板の位置ずれを抑制することがで
きる。
ドを設けた構造の半導体装置は、リードから見て下側の
樹脂の方が厚くなっている。このため、この上下モール
ド厚不均一などが原因となり、半導体素子が反ってしま
う場合がある。
ば、第2の遮蔽板17を設けているため、この第2の遮
蔽板17が骨組みの役目を果たし、半導体装置において
上下モールド厚不均一などが原因で起るモールド後のモ
ールド樹脂収縮によるパッケージ反り防止が期待でき
る。
板を設けて半導体素子の上側と下側との樹脂の注入速度
を制御しているため、樹脂の注入速度を最終的に均一に
することができるため、半導体素子の上面側のボイド発
生を抑制することができる。
図である。
図である。
説明する図である。
である。
である。
Claims (4)
- 【請求項1】 複数の電極が形成された表面と、この表
面と反対側の裏面とを有する半導体素子と、 前記半導体素子の前記表面に絶縁層を介して固着された
インナーリードと、 前記半導体素子の第1の側辺近傍に配置され、前記半導
体素子の前記裏面方向に曲げられた傾斜部を有する遮蔽
板と、 前記半導体素子、前記インナーリード、前記遮蔽板を封
止する封止樹脂とを含み、 前記封止樹脂は、前記半導体素子の前記第1の側辺と対
向する前記半導体素子の第2の側辺方向から注入される
ことを特徴とする半導体装置。 - 【請求項2】 前記遮蔽板は、隣接する前記インナーリ
ードから連続して設けられていることを特徴とする請求
項1記載の半導体装置。 - 【請求項3】 前記遮蔽板は、前記半導体素子の前記電
極とは電気的に接続されないことを特徴とする請求項1
記載の半導体装置。 - 【請求項4】 複数の電極が形成された表面と、この表
面と反対側の裏面とを有する半導体素子を準備する工程
と、 複数のインナーリードと、前記インナーリードと略同一
平面内に配置されるとともにその一部が前記半導体素子
の前記裏面側に曲げられている遮蔽板とを有するリード
フレームの前記複数のインナーリードを前記半導体素子
表面に絶縁層を介して固着する工程と、 前記半導体素子、前記インナーリード、前記遮蔽板を金
型内に配置し、前記遮蔽板が配置される側と反対の側か
ら樹脂を注入する工程と、 を含むことを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10285222A JP3105200B2 (ja) | 1998-10-07 | 1998-10-07 | 半導体装置およびその製造方法 |
US09/225,301 US6153923A (en) | 1998-10-07 | 1999-01-05 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10285222A JP3105200B2 (ja) | 1998-10-07 | 1998-10-07 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000114292A JP2000114292A (ja) | 2000-04-21 |
JP3105200B2 true JP3105200B2 (ja) | 2000-10-30 |
Family
ID=17688694
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10285222A Expired - Fee Related JP3105200B2 (ja) | 1998-10-07 | 1998-10-07 | 半導体装置およびその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US6153923A (ja) |
JP (1) | JP3105200B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7069080B2 (ja) | 2019-04-23 | 2022-05-17 | 三菱電機株式会社 | 管制装置 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6555412B1 (en) * | 1999-12-10 | 2003-04-29 | Micron Technology, Inc. | Packaged semiconductor chip and method of making same |
JP2002289758A (ja) * | 2001-03-23 | 2002-10-04 | Hitachi Chem Co Ltd | 半導体装置 |
KR20030018642A (ko) | 2001-08-30 | 2003-03-06 | 주식회사 하이닉스반도체 | 스택 칩 모듈 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW199235B (en) * | 1991-05-27 | 1993-02-01 | Hitachi Seisakusyo Kk | Method to enclose semiconductor devices in resin and semiconductor apparatuses |
JPH05291461A (ja) * | 1992-04-14 | 1993-11-05 | Toshiba Corp | 樹脂封止型半導体装置 |
JPH0846119A (ja) * | 1994-08-02 | 1996-02-16 | Sony Corp | リードフレームおよびこれを用いた半導体装置 |
JPH0888308A (ja) * | 1994-09-15 | 1996-04-02 | Toshiba Corp | リードフレーム及び半導体装置の製造方法 |
JPH08274234A (ja) * | 1995-03-30 | 1996-10-18 | Hitachi Ltd | 半導体装置およびその製造方法並びに半導体実装モジュール |
KR100195513B1 (ko) * | 1996-10-04 | 1999-06-15 | 윤종용 | 반도체 칩 패키지 |
US5926695A (en) * | 1997-06-10 | 1999-07-20 | National Semiconductor Corporation | Lead frame incorporating material flow diverters |
-
1998
- 1998-10-07 JP JP10285222A patent/JP3105200B2/ja not_active Expired - Fee Related
-
1999
- 1999-01-05 US US09/225,301 patent/US6153923A/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7069080B2 (ja) | 2019-04-23 | 2022-05-17 | 三菱電機株式会社 | 管制装置 |
Also Published As
Publication number | Publication date |
---|---|
US6153923A (en) | 2000-11-28 |
JP2000114292A (ja) | 2000-04-21 |
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