CN1174481C - 塑料芯片载具的无毛边堡形通孔的制造方法和产品 - Google Patents
塑料芯片载具的无毛边堡形通孔的制造方法和产品 Download PDFInfo
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Abstract
本发明系结合一种用于制造塑料芯片载具里的堡形通孔之新制造方法和结构,它可以产生均匀的半圆柱形侧壁接触,而没有任何毛边和粉末灰尘颗粒,当这些粉末灰尘颗粒出现在塑料芯片载具里面的时候,会引起电气上的短路或开路而妨碍电气接触的可靠性。因此,本发明使塑料芯片载具能够成为传统陶瓷芯片载具的实用之替代品。
Description
技术领域
本发明涉及一种新和改进之堡形通孔制造方法,该制造方法能够防止因在传统制造方法产生的毛边和微尘颗粒而引起“电气短路”和/或“电气开路”的问题。
背景技术
传统上,无接脚芯片载具是以陶瓷材料和制造方法以及非常高的成本生产的。为了降低成本,塑料芯片载具被发展出来,作为这种陶瓷无接脚芯片载具的替代物,而这成本的节省大约是3对1之比例的降低。对于这种新的塑料载具,要能够成为原有陶瓷的功能替代物应注意到的一个重要特征是:能够对半圆柱形(堡形)之侧面接触脚,提供高品质结构和表面的精密加工,这种侧面接触脚是以挖出一个全圆柱形电镀贯穿孔的一半来生成的。但是制造此类塑料芯片载具的现有技术很容易发生“毛边”310的现象,这种现象引起很多问题,包括在制造后立即发生的电气开路和短路,以及在该产品的使用寿命期间内发生的电气开路和短路。
发明内容
本发明之目的在于提供一种新和改进的堡形通孔制造方法,该制造方法能够预防由于在传统制造方法里产生的毛边和灰尘颗粒引起的电气短路和开路问题。依照本发明,无接脚半导体芯片载具制造程序的毛边和灰尘颗粒可以被减少到最低的程度、或被完全消除——这种制造程序包括将载具基底以镀铜处理,形成一个镀铜芯片载具基底,以及在该镀铜芯片载具基底里挖出一个或多个沟槽。这种改进包含:在挖掘一个或多个沟槽之前,先以一种厚度只有大约2微米至6微米之范围内的薄电镀层进行镀铜处理,以防止发生毛边。在挖出这些沟槽以后,接着以电镀使铜的厚度加厚到达最终的厚度范围以内,这种最终厚度较佳是在15至25微米之间。本制造方法的另一个特性是:一个保护性的覆盖层,譬如在薄电镀制造方法之后,涂布一种可用紫外线(UV)固化的油墨。该UV固化油墨层能够对薄铜层在挖掘期间提供保护,并且在挖掘沟槽之后,就予以剥离或去除。该UV被覆层提供底部的支撑,并且防止薄铜层在挖掘沟槽期间被拉离而形成毛边。
由此而产生一个无接脚半导体芯片载具,该载具表面有铜镀层的基底,和一个或多个贯穿该铜镀层与基底之机械挖掘沟槽,其中之改进在于:镀铜系由一个第一薄铜镀层(具有一个约为2至6微米范围内之厚度)组成,且该薄铜层施加于机械挖沟之前;在机械挖掘沟槽之后,再施加至少一层较厚的铜质被覆层,以便铜镀层的厚度是较佳地大概为15微米至25微米之间。
附图说明
考虑以下说明和随附图式,本发明之以上和其它的目标、优点和特征将可变得更加明白。
图1为一带有钻孔之基底核心材料之等角投影图。
图2为该基底的等角投影图,说明该基材上面带有铜被覆层。
图3为该基底的等角投影图,说明该基底上面已涂布有阻焊遮蔽层(solder mask)。
图4为一等角投影图,说明带有干膜开孔之镍/金区域。
图5为一等角投影图,显示一条用以挖掘沟槽之直线。
图6A和图6B为沿图5挖掘线的剖面线剖切之剖面视图和俯视图。
图7是一说明图,显示多个结合本发明之塑料芯片载具。
图8是一个结合有本发明之塑料芯片载具的俯视图。
图9是该基底之仰视平面图。
图10是结合本发明之结构与其角落部份的剖面轮廓之图解说明图。
图11是一个结合有本发明之堡形芯片载具之部份等角投影图。
图12是一个现有技术之说明图,说明在传统制造方法中的一些缺点。
图号说明:
(110)开孔;(120)支撑板;(125)铜;(130)贯穿孔;(135)侧面接触脚;(140)铜;(150)镍;(160)金;(170)阻焊遮蔽层;(210)沟槽;(220)塑料载具;(310)毛边;(320)粉末状灰尘颗粒;(330)侧边接触。
具体实施方式
对现有技术作仔细观察,便可以明白以上所讨论造成现有技术之缺点的原因。以下为遵循现有技术制造方法的典型步骤:
1.钻削多个开孔110(如图1所示)。
2.薄层覆盖贯穿孔(PTH)130和铜140。利用蚀刻非电路区域上的铜材125和140之方式界定电路系统(如图2所示)。
3.涂布阻焊遮蔽层170(如图3所不)。
4.薄层覆盖Ni/Au160(镍150/金160)(如图4所示)。
5.挖掘沟槽210(如图5所示)。
6.层压结合支撑板120,譬如以防火型4(FR4)或是Bismaleimide三氯化物(BT)120(即Bismaleimide Triazine 120)材料(如图10所示)。
7.最终精整挖掘沟槽210加工(如图9、10所示)。
在步骤5之中,该步骤是要挖掘沟槽210以便形成半圆形坑(在三次元立体视图中,它们是半圆柱体形),会产生严重的毛边310和粉末状灰尘颗粒320(参见图12)。已广为人所知的是:金属毛边310会造成短路,而塑料粉末灰尘颗粒320会堵塞住开孔110,当完成品夹合住侧面接触点的时候,产生电气的开路(如图6A和6B所示)。
此外,即使没有毛边,在侧墙上面,铜层会因为挖掘加工的关系而曝露出来。铜/镍/金层也可能被挖掘刀具拉开,并且与层压结合的侧壁之间变得剥离或松动。这两种现象都造成产品使用期间的可靠性问题(如图7和图8所示)。
毛边310和灰尘颗粒320的根本原因是由于厚的铜/镍/金之金属层125、140、150和160是非常具有弹性的,且不能够被挖掘加工轻易断裂分离开来(如图11和12所示)。
在本发明之中,一种用于制造此类侧边接触330的新生产制造方法被开发出来;在这个新制造方法里面,不会有毛边和粉末灰尘颗粒产生,或它们能够被减少到最小的程度,并因而减轻以上所提及的所有问题。
以下说明较佳之制造方法步骤顺序,虽然熟悉印刷电路板(PCB)和高密度连接(HDI)制造技术的人士可很容易地作各种变化,本发明之制造方法步骤顺序是建议如下:
1.在核心材料120(BT120材料,厚度约在0.4mm,但也可使用范围在0.2mm至1mm之间的任何所想要的厚度之材料,且该厚度不是一个极重要的参数)里,钻取开孔110(孔径大小是大约为0.5mm,一般范围可在0.25mm至1mm之间)(如图1所示)。
2.薄薄地覆盖贯穿孔(PTH)130和铜,厚度较佳为从大约2微米至大约6微米的范围,较佳的厚度是大约5微米(如图2所示)。
3.预蚀刻铜,在高密度和靠近沟槽边缘区域135里面产生电气线路图案(如图11所示)。
4.挖掘沟槽210以产生半圆柱形内侧面接触表面(如图5所示)。
5.完全覆盖这些贯穿孔和铜140,使达到它的最终厚度(范围为大约15微米到大约25微米之间,较佳的厚度为20微米)(如图11所示)。
6.以干膜开孔界定非高密度区域里面的镍/金区域150-160,同时保持高密度区域或侧缘区域完全开放,并且以电解电镀方式覆盖以镍/金,其中镍150是大约5微米厚(其范围是大约3微米至大约7微米),而金是大约0.75微米厚(其范围是大约0.5微米至大约1微米)。换句话说,镍/金是被覆盖在(i)侧缘区域,(ii)高密度区域,以及(iii)非高密度区域里的电路上面;只有非高密度区域里的非线路部份是维持在裸铜状态,以作为在镍/金之电解电镀期间覆盖总线连接的信道。
7.使用金160作为遮蔽层,以蚀刻非高密度电气线路区域里的铜。
8.层压结合支撑板120(FR4或BT120材料)(如图10所示)。
9.进行最终之精整挖掘沟槽210加工(如图9、图10所示)。
应注意到:在这个举例性质之制造方法里面,没有使用阻焊遮蔽层170。在需要使用阻焊遮蔽层170作为非镀金表面区域之保护层的应用上,可以采用以下两种选择其中任一种:
(a)修改步骤7,使用干膜遮蔽层来保护除了自然的金遮蔽层160之外的铜区域,然后蚀刻出电镀之总线区域,并继之以一个额外的阻焊遮蔽层170之印刷和开孔步骤,造成对任何铜表面的完全覆盖;或,
(b)假如不需要非镍/金/铜区域130-140,在步骤7之后,只加上一个阻焊遮蔽层170步骤。
采用修改选择项目(a)将会产生以下的程序步骤:
1.钻取开孔110(如图1所示)。
2.薄薄地覆盖贯穿孔130和铜,其厚度范围约在2微米到6微米之间(如图2所示)。
3.预先蚀刻高密度或靠近沟槽侧缘区域135里的铜线路图案(如图11所示)。
4.挖掘沟槽210(如图5所示)。
5.完全覆盖贯穿孔130和铜140到它的最终厚度(大约15微米至大约25微米之间)。
6.在保持高密度区域或侧缘区域完全开放的同时,在非高密度区域里,以干膜开孔界定镍/金区域150-160,并且以电镀法覆盖镍/金150-160。
7.干膜覆盖必须保持的铜区域,并蚀刻铜;(同时,在高密度区域或靠近侧缘的部位,使用镍/金150-160作为自然的蚀刻遮蔽层)。
8.涂布阻焊遮蔽层170,以保护不得曝露的区域;阻焊遮蔽层的厚度是大约在20微米到大约30微米,虽然,也可以使用高达50微米的较厚遮蔽层(如图3所示)。
9.层压结合支撑板120(FR4或是BT120材料)。
10.作最终的精整挖沟加工。
采用修改选项(b)将会产生以下的制造方法步骤:
1.钻取开孔110(如图1所示)。
2.薄薄地覆盖贯穿孔130和铜,其厚度范围约在2微米到6微米之间(如图2所示)。
3.预先蚀刻高密度或靠近沟槽侧缘区域135里的铜线路图案(如图11所示)。
4.挖掘沟槽210(如图5所示)。
5.完全覆盖贯穿孔和铜140到它的最终厚度(大约15微米至大约25微米范围之间)。
6.在保持高密度区域或侧缘区域完全开放的同时,在非高密度区域里,以干膜开孔界定镍/金区域150-160,并且以电镀法覆盖镍/金150-160。
7.使用金160作为遮蔽层,蚀刻非高密度线路区域里的铜。
8.涂布阻焊遮蔽层170,以保护不得曝露的区域;阻焊遮蔽层的厚度是大约在20微米到大约30微米,虽然,也可以使用高达50微米的较厚遮蔽层170(如图4所示)。
9.层压结合支撑板120(FR4或是BT120材料)。
10.作最终的精整挖掘沟槽210加工(如图9和图10所示)。
一种可更进一步地减少毛边之更精细制造方法顺序:
为了要更进一步地减少毛边,我们添加两个额外的步骤到原先的制造方法中
(3.1)涂布紫外线(UV)可固化之油墨进入到贯穿孔里面,并且以紫外线固化该油墨,以堵塞住贯穿孔(PTH)。
(4.1)以NaOH(氢氧化钠)剥离剂,剥离掉覆盖在贯穿孔内表面(在挖掘沟槽210之后留下的一半贯穿孔内表面)上的紫外线可固化之油墨。
注意:步骤3.1应该在本制造方法之所有变化应用里的步骤3之后完成。而步骤4.1应该在本制造方法之所有变化应用里的步骤4之后完成。
即使额外的步骤会增加制造方法的时间和成本,它能够更进一步地减少毛边310的可能性,因为在挖掘沟槽期间,可以紫外线固化的油墨是覆盖在薄铜上面,而防止了铜125、130、和140被剥离。虽然,可以紫外线固化的油墨是被引用作为一个堵塞贯穿孔壁的例子,但可在挖掘沟槽之前涂布并且可在挖掘沟槽之后剥离的其它材料和机构都可以被使用。
虽然,本发明已经以较佳的实施例来作为说明,显而易见地,本发明其它实施例的修改和变化对熟悉本技术领域之人士来说是可被察知的。
Claims (10)
1.一种用于制造无接脚半导体芯片载具的制造方法,其特征在于该无接脚半导体芯片载具包含有金属导体覆盖在该载具的基底上,该载具的基底具有多个可挖掘的开孔,以形成一个被导体金属覆盖的芯片载具基底,并且在所述之导体金属覆盖的芯片载具基材里挖掘有一个或多个沟槽,其中,用于防止产生毛边的改进包括:所述的导体金属覆盖是在(a)挖掘所述的一个或多个沟槽以前,使用厚度在2微米至6微米范围以内的薄导体金属电镀来完成的,以及(b)在挖掘所述沟槽之后,加厚所述的导体金属电镀被覆层到一个最终的厚度。
2.如权利要求1所述之制造方法,其特征在于所述之导体金属系为铜,以及,所述之最终厚度是在为15微米至25微米范围之间。
3.一种在如权利要求1所述之制造方法里可更进一步地防止产生毛边之制造方法,其特征在于借助此制造方法,在该薄导体金属被覆和图案蚀刻之后,涂布一种可利用紫外线固化之油墨被覆层,以作为在挖掘沟槽期间该薄导体金属被覆层的保护层,并且在挖掘沟槽之后予以剥离,所述之覆盖层藉此提供支撑作用,并且防止该薄铜被扯脱。
4.如权利要求3所述之制造方法,其特征在于所述之导体金属是铜,以及所述之最终厚度是在15微米至25微米之间的范围之间。
5.一种无接脚半导体芯片载具,其特征在于具有导体金属被覆层掩盖在的基底上面,以及一个或多个以机械加工挖掘的沟槽贯穿所述之导体金属被覆层和基底,其所述导体金属被覆层之改进在于:所述之导体金属被覆层是由一个第一薄导体金属层和至少一个第二较厚之导体金属层组成,所述之第一薄导体金属层是在所述一个或多个机械挖掘沟槽之前被施加在基座上的,而所述之第二较厚之导体金属层是在所述之机械挖掘沟槽之后被施加以达到所述导体金属被覆层之最终厚度。
6.如权利要求5所述之芯片载具,其特征在于所述之第一薄金属层具有一个介于2微米至6微米范围之间的厚度。
7.如权利要求6所述之芯片载具,其特征在于所述之最终厚度是介于15微米至25微米范围之间。
8.如权利要求5所述之芯片载具,其特征在于所述之导体金属是铜。
9.如权利要求6所述之芯片载具,其特征在于所述之导体金属是铜。
10.如权利要求7所述之芯片载具,其特征在于所述之导体金属是铜。
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US09/548,671 US6675472B1 (en) | 1999-04-29 | 2000-04-13 | Process and structure for manufacturing plastic chip carrier |
US09/548,671 | 2000-04-13 |
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TW469559B (en) | 2001-12-21 |
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