US20040141299A1 - Burrless castellation via process and product for plastic chip carrier - Google Patents

Burrless castellation via process and product for plastic chip carrier Download PDF

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Publication number
US20040141299A1
US20040141299A1 US10/753,314 US75331404A US2004141299A1 US 20040141299 A1 US20040141299 A1 US 20040141299A1 US 75331404 A US75331404 A US 75331404A US 2004141299 A1 US2004141299 A1 US 2004141299A1
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Prior art keywords
conductive metal
microns
chip carrier
copper
routing
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Abandoned
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US10/753,314
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Edward Huang
Jonny Ma
Scott Chen
Paul Wu
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Unicap Electronics Industrial Corp
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Unicap Electronics Industrial Corp
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Priority to US10/753,314 priority Critical patent/US20040141299A1/en
Publication of US20040141299A1 publication Critical patent/US20040141299A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • This invention relates to a new and improved castellation via process which can prevent causing “short circuit” and/or “open circuit” problems due to burrs and dust particles generated in the traditional manufacturing processes.
  • the object of the present invention is to provide a new and improved castellation via process which can prevent causing short circuit and open circuit problems due to burrs and dust particles generated in the traditional manufacturing process.
  • burrs and dust particles are eliminated or minimized in the process of manufacturing leadless semiconductor chip carriers which include copper plating the carrier substrate to form a copper plated chip carrier substrate and wherein the routing of one or more slots in the copper plated chip carrier substrate.
  • the improvement comprises preventing burrs wherein the copper plating is performed prior to making the routing of one or more slots by a thin plating in a thickness range of about 2 microns to about 6 microns.
  • the copper is thickened by plating to a thickness of the final thickness range, preferably in the range of 15 to 25 microns.
  • a protective coating layer such as an ultraviolet (UV) curable ink is applied after the thin copper plating.
  • UV curable ink layer provides protection for the thin copper layer during routing and is stripped off or removed after routing.
  • the UV coating layer provides backing support and prevents the thin copper from being pulled off and forming burrs during routing.
  • a leadless semiconductor chip carrier having copper plating on a substrate and one or more machine routings formed through the copper plating and substrate wherein the improvement lies in the copper plating being comprised of a first thin copper layer (having a thickness range of about 2 to 6 microns) and applied prior to the machine routings. At least one thicker copper layer is applied after the machine routing so that the thickness of the copper plating is preferably in the range of from about 15 microns to about 25 microns.
  • FIG. 1 is an isometric view of a substrate core material with drill holes therein
  • FIG. 2 is an isometric view of the substrate with copper coating layers thereon
  • FIG. 3 is an isometric view of the substrate in which the solder mask layer has been applied
  • FIG. 4 is an isometric view showing nickel/gold area with dry film openings
  • FIG. 5 is an isometric view showing a line for the routing slots
  • FIGS. 6A and 6B are sectional and top views along the sectional lines for a routing line of FIG. 5,
  • FIG. 7 is an illustration showing a plurality of plastic chip carriers incorporating the invention
  • FIG. 8 is a top view of one plastic chip carrier substrate incorporating the invention.
  • FIG. 9 is a bottom plan view of the substrate
  • FIG. 10 is a diagrammatic illustration of a sectional profile of the corner of the structure incorporating the invention.
  • FIG. 11 is an isometric view of a portion of a castellated chip carrier incorporating the invention.
  • FIG. 12 is a view of prior art illustrating some of the defects in prior art processes.
  • Plating PTH Platinum Through Holes
  • copper 140 Define circuitry by etching copper 125 and 140 in non-circuitry areas.
  • Laminating the supporting board such as Flame Retardant type 4 (FR4) or Bismaleimide Triazine (BT) 120 material.
  • FR4 Flame Retardant type 4
  • BT Bismaleimide Triazine
  • step 5 which is to route the opening slots 210 for forming the semi-circles (they are semi-cylinders in 3-dimensional view), severe burrs 310 and powder dust particles 320 occur (see FIG. 12). It is known that metallic burrs 310 result in short circuit and the plastic powder dust particles 320 , which block the holes 110 , result in open circuit when the side contacts in the finished product are clamped on.
  • the root cause of the burrs 310 and the dust particles 320 is due to the fact that the thick copper/nickel/gold metal layers 125 , 140 , 150 , and 160 are very resilient and cannot be easily broken off by the routing process.
  • PCB Printed Circuit Board
  • HDI High Density Interconnect
  • Drill holes 110 are around 0.5 mm, typical range can be from 0.25 mm to 1 mm
  • the core 120 BT material, with thickness around 0.4 mm, though any desired thickness ranging from 0.2 mm to 1 mm can be used and is not a critical parameter).
  • Thin-plate PTH 130 Platinum Through Holes
  • copper with thickness preferably ranging from about 2 microns to about 6 microns, with a preferred thickness of about 5 microns.
  • nickel/gold area 150 - 160 with dry-film openings in the non-high-density area while keeping the high-density or edge areas completely open and plate nickel/gold with electrolytic-plating method, where nickel 150 is around 5 microns (with a range of about 3 to about 7 microns) thick and gold is around about 0.75 micron (with a range of about 0.5 to about 1 micron) thick.
  • nickel/gold is plated over i) edge area, ii) high-density area, and iii) circuitry in non-high-density area. Only the non-circuitry portion of the non-high-density area remains bare copper, to serve as conduit for plating buss connection during electrolytic nickel/gold plating.
  • Laminate supporting board (FR4 or BT material 120 ).
  • solder mask 170 is not used. In applications where solder mask 170 is needed as a protective layer for non-gold surface area, either one of the following two options can be adapted:
  • step 7 by using dry-film-mask to protect copper area in addition to the natural gold-mask 160 , then etch out plating buss area and follow with an additional solder mask 170 print and opening step, resulting in complete covering of any copper surface, or
  • solder mask 170 to protect areas not to be exposed; solder mask thickness is around about 20 microns to about 30 microns, though thicker solder mask for up to 50 microns can also be used.
  • Laminate supporting board (FR4 or BT material)
  • solder mask 170 to protect areas not to be exposed; solder mask 170 thickness is around about 20 microns to about 30 microns, though thicker solder mask 170 for up to 50 microns can also be used.
  • Laminate supporting board (FR4 or BT 120 material).
  • step 3.1 is to be done after step 3 in all variations of the process and step 4.1 is to be done after step 4, respectively.
  • UV curable ink covers the thin copper during routing and prevents the copper 125 , 130 , and 140 from being lifted.
  • UV curable ink is cited as an example for plugging the PTH walls, other materials and mechanisms that can be applied before routing and stripped off after routing can be used.

Abstract

This invention incorporates a new process and structure for manufacturing castellation via in plastic chip carrier. It allows the creation of uniform side wall contacts in the shape of half-cylinders, devoid of any burrs and power dust particles, which when present in a plastic chip carrier, would prevent reliable electrical contacts by causing either short or open circuits. Thus the invention enables plastic chip carrier as a practical way of replacing traditional ceramic chip carriers.

Description

    REFERENCE TO RELATED APPLICATION
  • This application is based on provisional Application No. 60/131,492 filed Apr. 29, 1999 entitled BURRLESS CASTELLATION (SEMI-CYLINDER VIA) PROCESS AND STRUCTURE FOR PLASTIC CHIP CARRIER.[0001]
    • FIELD OF THE INVENTION
  • This invention relates to a new and improved castellation via process which can prevent causing “short circuit” and/or “open circuit” problems due to burrs and dust particles generated in the traditional manufacturing processes. [0002]
    • DESCRIPTION OF THE PRIOR ART
  • Traditionally, Leadless Chip Carrier is manufactured with ceramic materials and processes, at very high cost. In order to reduce cost, plastic chip carrier was developed as a replacement for the ceramic leadless chip carrier, whereas the cost saving is around 3 to 1 reduction. Note that one essential aspect for the new [0003] plastic carrier 220 to be a functioning replacement of its ceramic predecessor is the capability to provide high quality structure and surface finish in the half-cylinder shaped (castellation) side contact pins 135, which are made by routing out one-half of a full-cylinder plated through hole. But the prior art in manufacturing such plastic chip carrier is prone to the phenomenon of “burr” 310, which causes many problems including open circuit and short circuit immediately after fabrication and during the useful life cycle of the product.
    • THE PRESENT INVENTION
  • The object of the present invention is to provide a new and improved castellation via process which can prevent causing short circuit and open circuit problems due to burrs and dust particles generated in the traditional manufacturing process. According to the invention, burrs and dust particles are eliminated or minimized in the process of manufacturing leadless semiconductor chip carriers which include copper plating the carrier substrate to form a copper plated chip carrier substrate and wherein the routing of one or more slots in the copper plated chip carrier substrate. The improvement comprises preventing burrs wherein the copper plating is performed prior to making the routing of one or more slots by a thin plating in a thickness range of about 2 microns to about 6 microns. Subsequent to routing of the slots, the copper is thickened by plating to a thickness of the final thickness range, preferably in the range of 15 to 25 microns. In a further aspect of the process, a protective coating layer, such as an ultraviolet (UV) curable ink is applied after the thin copper plating. The UV curable ink layer provides protection for the thin copper layer during routing and is stripped off or removed after routing. The UV coating layer provides backing support and prevents the thin copper from being pulled off and forming burrs during routing. [0004]
  • This results in a leadless semiconductor chip carrier having copper plating on a substrate and one or more machine routings formed through the copper plating and substrate wherein the improvement lies in the copper plating being comprised of a first thin copper layer (having a thickness range of about 2 to 6 microns) and applied prior to the machine routings. At least one thicker copper layer is applied after the machine routing so that the thickness of the copper plating is preferably in the range of from about 15 microns to about 25 microns.[0005]
    • DESCRIPTION OF THE DRAWINGS
  • The above and other objects, advantages and features of the invention will become more apparent when considered with the following specification and accompanying drawings wherein: [0006]
  • FIG. 1 is an isometric view of a substrate core material with drill holes therein, [0007]
  • FIG. 2 is an isometric view of the substrate with copper coating layers thereon, [0008]
  • FIG. 3 is an isometric view of the substrate in which the solder mask layer has been applied, [0009]
  • FIG. 4 is an isometric view showing nickel/gold area with dry film openings, [0010]
  • FIG. 5 is an isometric view showing a line for the routing slots, [0011]
  • FIGS. 6A and 6B are sectional and top views along the sectional lines for a routing line of FIG. 5, [0012]
  • FIG. 7 is an illustration showing a plurality of plastic chip carriers incorporating the invention, [0013]
  • FIG. 8 is a top view of one plastic chip carrier substrate incorporating the invention, [0014]
  • FIG. 9 is a bottom plan view of the substrate, [0015]
  • FIG. 10 is a diagrammatic illustration of a sectional profile of the corner of the structure incorporating the invention, [0016]
  • FIG. 11 is an isometric view of a portion of a castellated chip carrier incorporating the invention, and [0017]
  • FIG. 12 is a view of prior art illustrating some of the defects in prior art processes.[0018]
    • DETAILED DESCRIPTION OF THE INVENTION
  • A closer look at the prior art demonstrates the reasons for the prior art shortcomings discussed above. A prior art process follows the typical steps of: [0019]
  • 1. [0020] Drilling holes 110.
  • 2. Plating PTH (Plated Through Holes) and [0021] copper 140. Define circuitry by etching copper 125 and 140 in non-circuitry areas.
  • 3. Applying [0022] solder mask 170.
  • 4. Plating Ni/Au [0023] 160 (Nickel/Gold).
  • 5. Routing the [0024] slots 210,
  • 6. Laminating the supporting board such as Flame Retardant type 4 (FR4) or Bismaleimide Triazine (BT) [0025] 120 material.
  • 7. [0026] Final route 210.
  • During step 5, which is to route the [0027] opening slots 210 for forming the semi-circles (they are semi-cylinders in 3-dimensional view), severe burrs 310 and powder dust particles 320 occur (see FIG. 12). It is known that metallic burrs 310 result in short circuit and the plastic powder dust particles 320, which block the holes 110, result in open circuit when the side contacts in the finished product are clamped on.
  • In addition, even if there are no burrs, on the side wall, the copper layer is exposed due to the routing process. The copper/nickel/gold layers can also be pulled off by the routing bit and become lifted or loosened from the laminated side wall. Both phenomena are reliability concerns during the operation life of the product. [0028]
  • The root cause of the [0029] burrs 310 and the dust particles 320 is due to the fact that the thick copper/nickel/ gold metal layers 125, 140, 150, and 160 are very resilient and cannot be easily broken off by the routing process.
  • In this invention, a new process for manufacturing [0030] such side contacts 330 is developed, in which no burrs and power dust particles are generated or are minimized and thus alleviating all problems mentioned above.
    • THE PRESENT INVENTION
  • The following describes preferred process step sequence, though variations can be adopted by the skilled in the art of Printed Circuit Board (PCB) and High Density Interconnect (HDI) fabrications, some of which are suggested below: [0031]
  • 1. Drill holes [0032] 110 (hole size is around 0.5 mm, typical range can be from 0.25 mm to 1 mm) in the core 120 (BT material, with thickness around 0.4 mm, though any desired thickness ranging from 0.2 mm to 1 mm can be used and is not a critical parameter).
  • 2. Thin-plate PTH [0033] 130 (Plated Through Holes) and copper with thickness preferably ranging from about 2 microns to about 6 microns, with a preferred thickness of about 5 microns.
  • 3. Pre-etch copper, resulting in circuitry pattern in high density and near-[0034] slot edge area 135.
  • 4. Route the [0035] slots 210 to produce the inner half-cylinder shaped side contact surface.
  • 5. Full-plate the PTH and the [0036] copper 140 to its final thickness (in the range of about 15 microns to about 25 microns, with a preferred thickness of 20 microns).
  • 6. Define nickel/gold area [0037] 150-160 with dry-film openings in the non-high-density area while keeping the high-density or edge areas completely open and plate nickel/gold with electrolytic-plating method, where nickel 150 is around 5 microns (with a range of about 3 to about 7 microns) thick and gold is around about 0.75 micron (with a range of about 0.5 to about 1 micron) thick. In other words, nickel/gold is plated over i) edge area, ii) high-density area, and iii) circuitry in non-high-density area. Only the non-circuitry portion of the non-high-density area remains bare copper, to serve as conduit for plating buss connection during electrolytic nickel/gold plating.
  • 7. Etch copper in non-high-density circuit [0038] area using gold 160 as mask.
  • 8. Laminate supporting board (FR4 or BT material [0039] 120).
  • 9. Final route. [0040]
  • Note that in this exemplary process, [0041] solder mask 170 is not used. In applications where solder mask 170 is needed as a protective layer for non-gold surface area, either one of the following two options can be adapted:
  • (a) modify step 7 by using dry-film-mask to protect copper area in addition to the natural gold-[0042] mask 160, then etch out plating buss area and follow with an additional solder mask 170 print and opening step, resulting in complete covering of any copper surface, or
  • (b) simply add a [0043] solder mask 170 step after step 7, if non-nickel/gold copper-area 130-140 is not needed.
  • Taking modification option a) will result in the following process steps: [0044]  
  • 1. Drill holes [0045] 110.
  • 2. Thin-[0046] plating PTH 130 and copper with thickness ranging from about 2 microns to 6 about microns.
  • 3. Pre-etch copper circuitry pattern in high density or near-[0047] slot edge area 135.
  • 4. Route the slots. [0048]
  • 5. Full-plate the PTH and the [0049] copper 140 to its final thickness (about 15 microns to about 25 microns).
  • 6. Define nickel/gold area [0050] 150-160 with dry-film openings in the non-high-density area while keeping the high-density or edge areas completely open and plate nickel/gold 150-160 with electrolytic-plating method.
  • 7. Dry-film cover copper areas to be retained and etch copper; (while in the high-density area or near the edge, using nickel/gold [0051] 150-160 as the natural etch mask).
  • 8. Apply [0052] solder mask 170 to protect areas not to be exposed; solder mask thickness is around about 20 microns to about 30 microns, though thicker solder mask for up to 50 microns can also be used.
  • 9. Laminate supporting board (FR4 or BT material) [0053]
  • 10. Final route. [0054]
  • Taking modification option (b) will result in the following process steps: [0055]
  • 1. Drill holes [0056] 110.
  • 2. Thin-plating PTH [0057] 130 (plated through holes) and copper with thickness ranging from about 2 microns to about 6 microns.
  • 3. Pre-etch copper circuitry pattern in high density or near-[0058] slot edge area 135.
  • 4. Route the [0059] slots 210.
  • 5. Full-plate the PTH and the [0060] copper 140 to its final thickness (about 15 microns to about 25 microns).
  • 6. Define nickel/gold area [0061] 150-160 with dry-film openings in the non-high-density area while keeping the high-density or edge areas completely open and plate nickel/gold 150-160 with electrolytic-plating method.
  • 7. Etch copper in non-high-density circuit [0062] area using gold 160 as mask.
  • 8. Apply [0063] solder mask 170 to protect areas not to be exposed; solder mask 170 thickness is around about 20 microns to about 30 microns, though thicker solder mask 170 for up to 50 microns can also be used.
  • 9. Laminate supporting board (FR4 or [0064] BT 120 material).
  • 10. Final route. [0065]
  • A More Refined Process Sequence for Further Reduction of Burrs [0066]
  • To further reduce burrs, we add two more steps to the original process. [0067]
  • 3.1) Plug the PTH with Ultra-Violet (UV) curable ink by applying the ink into the holes and curing it with UV light. [0068]
  • 4.1) Strip off the UV curable ink that covers the inner surface of the PTH (the half that remains after routing the slots [0069] 210) with NaOH (Sodium Hydroxide) stripper.
  • Note that step 3.1 is to be done after step 3 in all variations of the process and step 4.1 is to be done after step 4, respectively. [0070]  
  • Even though the additional steps add to process time and cost, it further reduces the possibility of [0071] burrs 310, because the UV curable ink covers the thin copper during routing and prevents the copper 125, 130, and 140 from being lifted. Though UV curable ink is cited as an example for plugging the PTH walls, other materials and mechanisms that can be applied before routing and stripped off after routing can be used.
  • While the invention has been described in relation to preferred embodiments of the invention, it will be appreciated that other embodiments, adaptations and modifications of the invention will be apparent to those skilled in the art. [0072]

Claims (10)

What is claimed is:
1. In a process for manufacturing a leadless semiconductor chip carrier which includes conductive metal plating the carrier substrate having a plurality of routable holes to form a conductive metal plated chip carrier substrate, and, routing one or more slots in said conductive metal plated chip carrier substrate, the improvement for preventing burrs comprising said conductive metal plating is performed (a) prior to making said routing one or more slots by a thin conductive metal plating with a thickness in the range of about 2 microns to about 6 microns and (b) subsequent to routing of said slots, thickening said conductive metal plating to a final thickness.
2. The process defined in claim 1 wherein said conductive metal is copper and said final thickness is in that range of between about 15 microns to about 25 microns.
3. In a process for further preventing burrs in the process prescribed in claim 1, whereby a coating layer such as UV curable ink is applied after the thin conductive metal plating and pattern etching, used as a protection for the thin conductive metal plating during routing, and stripped off after routing whereby said coating layer provides backing support and prevents the thin copper from being pulled off.
4. The process defined in claim 3 wherein said conductive metal is copper and said final thickness is in that range of between about 15 microns to about 25 microns.
5. In a leadless semiconductor chip carrier having a conductive metal plating on a substrate and one or more machined routings formed through said conductive metal plating and substrate, the improvement wherein said conductive metal plating is comprised of a first thin conductive metal layer applied prior to said one or more machined routings and at least a second thicker conductive metal layer applied after said machined routing to a final thickness of said conductive metal plating.
6. The chip carrier defined in claim 5 wherein said first thin layer has a thickness in the range of about 2 microns to about 6 microns.
7. The chip carrier defined in claim 6 wherein said final thickness is in the range of about 15 microns to about 25 microns.
8. The chip carrier defined in claim 5 wherein said conductive metal is copper.
9. The chip carrier defined in claim 6 wherein said conductive metal is copper.
10. The chip carrier defined in claim 7 wherein said conductive metal is copper.
US10/753,314 1999-04-29 2004-01-09 Burrless castellation via process and product for plastic chip carrier Abandoned US20040141299A1 (en)

Priority Applications (1)

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US10/753,314 US20040141299A1 (en) 1999-04-29 2004-01-09 Burrless castellation via process and product for plastic chip carrier

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US13149299P 1999-04-29 1999-04-29
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US6675472B1 (en) 2004-01-13
CN1349659A (en) 2002-05-15
CN1174481C (en) 2004-11-03
WO2000071921A2 (en) 2000-11-30
JP2003500845A (en) 2003-01-07
TW469559B (en) 2001-12-21
AU6585700A (en) 2000-12-12
WO2000071921A3 (en) 2001-08-09

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