CN1203741C - 制造印刷电路板的方法 - Google Patents
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Abstract
这里公开了一种制造印刷电路板的方法。在上层板上镀敷金属形成电路时,可以防止用于与半导体芯片键合的键合条上镀敷金属。即,在多个板的每个中形成其上有墨层的狭槽。然后,限定不同尺寸的窗口区,并在未形成狭槽的部分上进行加工。即,对敷铜箔叠片进行加工,从而形成狭槽,并在每个狭槽中形成墨层。以此方式,在镀敷印刷电路板的上层表面时,可以防止金属侵入窗口区,因而可以防止形成短路。
Description
技术领域
本发明涉及一种制造印刷电路板的方法。特别是,本发明涉及一种制造封装型多层印刷电路板的方法,其中在具有用于安装半导体芯片的窗口区的多层印刷电路板中,在金属镀敷到上层板从而形成电路时,可以防止用于与半导体芯片键合的键合条被电镀上金属。
背景技术
近年来,由于将高密度集成电路芯片制造成具有高速度和高功能,安装半导体芯片的电路板必须具有高速度和高功能。因此,为解决高速度和高功能的问题,提出了封装型电路板(直接安装半导体芯片)。这些封装型电路板中,由多个板构成的芯片于板上型电路板可形成特别高密度电路,因此,该板引起了人们的特别关注。
图1展示了用于安装半导体芯片的常规封装型多层印刷电路板。如该图所示,该印刷电路板由多个板构成,其上形成有电路。除形成底部电路板的第一敷铜箔叠片1a外,其它敷铜箔叠片1b、1c和1d构成窗口4,半导体芯片7将安装于其中。
在上述印刷电路板中,采用了两面敷铜箔叠片(CCL)。因此,腐蚀CCL1a,1b,1c和1d两面的铜箔敷层形成电路。另外,CCL1a、1b、1c和1d通过由半固化片构成的粘附层2a、2b和2c耦合在一起。CCL1a、1b、1c和1d的长度不同。即,不同的CCL,安装半导体芯片的窗口的宽度不同,因此,在CCL1a、1b、1c和1d耦合在一起时,形成多台阶形窗口。
一般情况下,按以下方式制造上述多层印刷电路板。即,各CCL1a、1b、1c和1d分别制备,并形成窗口区。然后,各CCL利用半固化片耦合在一起。因此,如果要形成附图中所示的各窗口区4,则各CCL的窗口区必须具有不同尺寸。
以此方式,窗口4形成多台阶形。因此,第二CCL1b和第三CCL1c的部分暴露于外。在第二和第三CCL1b和1c的暴露部分,设置有铜或其它金属层3a和3b。这些金属层3a和3b通过金属丝10引线键合到半导体芯片7的焊盘9上,因此,金属层3a和3b称为“键合条”。
上述印刷电路板的优点在于,电路板和半导体芯片间的引线键合在窗口内进行。因此,键合引线不暴露于外部,因而不会因外部冲击等造成损伤。
在印刷电路板中,形成有通孔11。这些通孔11用于电连接各上层和最下层,通孔11的内部电镀有金属。另外,在最下层即第四CCL1d的上表面上电镀金属,从而形成电路。因此,在通孔11内和第四CCL1d的上表面上电镀金属时,金属也会镀敷于窗口内。特别是,金属会镀敷在键合条3a和3b上,因此,电路容易短路,引起故障。
为了防止因镀敷键合条3a和3b造成的短路,在第四CCL1d的上表面上镀敷金属形成电路时,必须掩蔽窗口,这样金属便不能侵入窗口4。
图2展示了防止金属侵入窗口的方法。如图2所示,在镀敷金属之前,在第四CCL1d上布设干膜15。因此,在窗口被掩蔽的情况进行金属镀敷,因而键合条不会被金属镀敷。然而,干膜15具有一定的质量,因此,在尺寸为16.7mm×16.7mm的干膜布设于窗口上时,由于其自身的重力,干膜被向下拉,结果干膜破裂。为了防止这种存裂,如果将干膜制备得较厚,则由于大厚度不能形成微细图形。
另一建议中,有一种在第四CCL1d上附着铜箔以掩蔽窗口的方法。然而,这种情况下,由于铜箔处理和腐蚀处理复杂,整个处理成本提高,因而导致了制造成本增加。
发明内容
本发明意在克服常规技术的上述问题。
因此,本发明的目的是提供一种制造印刷电路板的方法,其中首先加工多个板,以在它们每一个中形成狭槽,然后,在狭槽中形成墨层,然后镀敷金属,然后,对板进行第二加工,从而防止在半导体安装区上的金属镀敷。
为实现上述目的,本发明提供一种制造印刷电路板的方法,包括以下步骤:在多个板的每个上形成电路;在多个板的每个中形成狭槽,以便形成具有不同尺寸的窗口区;在狭槽中填充墨,形成墨层;把多个板耦合在一起,形成多层电路板;穿过多层电路板形成通孔,镀敷金属,并腐蚀它;用例如氢氧化钠等处理液处理墨层,从而去掉墨层;去掉多个板上未形成狭槽的区域,从而在多层印刷电路中形成多台阶窗口。
本发明还提供了一种制造具有多层的印刷电路板的方法,包括以下步骤:在多个板的每个上形成电路;在第一板上形成窗口;在第二板中形成多个狭槽,以便限定大于前述窗口的窗口区;在所说第二板的所说多个所说狭槽中形成墨层;把所说第一板和所说第二板连接在一起;穿过所说第一板和第二板形成通孔,在其中镀敷金属,并腐蚀所说金属;去掉所说狭槽中的所说墨层;及去掉所说第二板的未形成所说狭槽的窗口部分,从而形成多台阶窗口。
本发明还提供了一种制造印刷电路板方法,包括以下步骤:在多个板的每个上形成电路;在所说多个板中形成多个狭槽,以便限定具有不同尺寸的各窗口区;把多个所说板连接在一起,从而形成多层电路板;在各所说板的多个所说狭槽中形成墨层;在多个所说板的每个中形成通孔,在其中镀敷金属,并腐蚀所说金属;从所说狭槽中去掉所说墨层;及去掉所说多个板上未形成所说狭槽的窗口部分,从而在所说多层印刷电路中形成多台阶窗口。
半导体芯片安装到多台阶窗口中,在板上形成键合条,以便引线键合到半导体芯片。
附图说明
通过结合附图详细介绍本发明的优选实施例,可以使本发明的上述目的和其它优点变得更清楚,各附图中:
图1展示了用于安装半导体芯片的常规封装型多层印刷电路板;
图2展示了常规多层印刷电路板的结构;
图3a-3d展示了本发明的多层印刷电路板的制造工艺;
图4是图3b的平面图。
具体实施方式
下面结合附图详细介绍根据本发明的制造多层印刷电路板方法。用相同的标记表示与常规方法中相同的参考标记。
图3展示了本发明的多层印刷电路板的制造工艺。在本说明书中,假定采用CCL,但这并不意味着本发明限于CCL,而只是为了介绍方便。
首先,如图3a所示,对CCL1进行第一加工,从而形成狭槽17a。然后,如图3b所示,在CCL1的狭槽17a中填入墨。在形成多层印刷电路板的每个CCL中形成狭槽17a。
图4示出了在其中形成有狭槽的板。如该图所示,每四个狭槽大致构成一个方形。由狭槽包围着的区域20构成用于安装半导体芯片的窗口,该区将被去除。
因此,在制备多个CCL1时,将区域20的面积制备得不同,因而形成多台阶窗口。在CCL1中,通过利用槽刨刀(rauter bit)等机械形成狭槽17a。狭槽17a的宽度约为0.2-3.2mm,将被去除的窗口区的面积约为16.7mm×16.7mm。在到达CCL的下层时,区域20的面积变得较小,从而形成多台阶窗口。每个CCL1的区域20支撑在每个CCL1的四个角部上,在那里没形成狭槽。
墨填入狭槽17a中,在120-130℃的温度下,干燥60-100分钟,使墨固化,从而形成墨层17。在多层印刷电路板的上表面镀敷金属时,由于存在墨层17,所以防止了金属侵入窗口。
然后,如图3b所示,腐蚀CCL1的铜箔,形成电路5。在形成窗口后,该电路可用作电连接半导体芯片的焊盘。
如上所述加工了CCL1后,镀敷金属,从而形成电路5。然而,实际上,在CCL1上镀敷金属,然后进行腐蚀形成电路5,然后形成狭槽17a,这更合乎需要。理由如下,即,在CCL1中形成了狭槽17a后镀敷金属的情况中,狭槽17a内部镀敷有金属,因此,在填充墨期间必须去掉狭槽17a的金属。
然后,如图3c所示,在如图3a和3b所示加工过的CCL1a、1b、1c和1d之间布设了粘附层2a、2b和2c(由半固化片构成)后,将它们耦合在一起。这种条件下,粘附层2a、2b和2c由高粘度的半固化片构成,所以可以防止该半固化片流到窗口区中。
CCL1a-1d每个都具有电路和填充有墨的狭槽17a。因此,在CCL1a-1d耦合在一起时,作用于CCL1a-1d的力均匀分布在CCL1a-1d上,因此,耦合在均匀强度下完成。或者,可以使其中填充墨的狭槽只形成于最外部的CCL1d,并从其余CCL1a-1c中去除窗口区。
然后,利用例如钻等机械装置钻CCL1a-1c和各粘附层2a-2c,从而形成通孔11。然后在通孔11的内部和第四CCL1d的上表面上镀敷金属,然后进行腐蚀,从而形成电路5。此后,利用例如氢氧化钠(NaOH)等处理液去掉墨层17。以此方式,在CCL1a-1d上形成大致为方形的各狭槽17a,如图4所示。
然后,利用例如槽刨等机械装置,对窗口区的角部即各狭槽间在第一加工中没有被加工的CCL的部分,进行第二加工,从而去掉CCL1的窗口区20。以此方式,形成窗口4,如图3d所示。然后,把半导体芯片安装到窗口4中,键合条3a和3b通过各金属丝键合到半导体芯片的焊盘上。
如上所述,在本发明的印刷电路板制造方法中,在每个CCL1a,1b,1c和1d中形成宽度为0.2-3.2mm的狭槽17a。用墨填充到狭槽,从而形成墨层17,因此,在印刷电路板上镀敷金属时,防止了金属侵入到所说窗口中。如上所述,狭槽的宽度约为0.2-3.2mm,因而,可以用墨完全填充狭槽内部。另外,在120-130℃的温度下固化墨60-100分钟,因而墨不可能漏到外部。
不使用本发明的上述方法,还可以把带有形成于其中的窗口区的CCL耦合在一起,然后在窗口区中填入墨,然后再镀敷金属。然而,按这种不同方法,CCL1a,1b,1c和1d的半固化片(尽管具有高粘度)会漏到窗口区中,墨会与这些半固化片化学反应,因而强有力粘合在一起。因此,在去除墨时,不能完全去除,墨仍会保留在键合条上。结果半导体芯片和印刷电路板间的电连接会发生问题。因此,本发明的方法较好是在每个CCL中形成狭槽,这样便可以防止镀敷期间侵入金属,这是最有效方法。
根据上述本发明,在上层板上镀敷金属从而形成电路时,防止了用于与半导体芯片键合的键合条被电镀上金属。即,防止了金属侵入到多台阶窗口中。即,对CCL进行第一加工,从而形成狭槽,并在每个狭槽内形成墨层。以此方式,在镀敷印刷电路板的上表面时,可以防止金属侵入窗口区内。然后,对CCL进行第二加工,从而形成窗口。所以本发明的方法简单,降低了制造成本。
Claims (17)
1.一种制造印刷电路板的方法,包括以下步骤:
在多个板的每个上形成电路;
在所说多个板的每个中形成狭槽,以便限定具有不同尺寸的窗口区;
在所说狭槽中填充墨,形成墨层;
把所说多个板连接在一起,形成多层电路板;
穿过所说多层电路板形成通孔,在其中镀敷金属,并腐蚀所说金属;
去掉所说墨层;及
去掉所说多个板上窗口区内的未形成所说狭槽的区域,从而在所说多层印刷电路中形成多台阶窗口。
2.如权利要求1所述的方法,其中所说板是敷铜箔叠片。
3.如权利要求1所述的方法,其中所说狭槽宽约0.2-3.2mm。
4.如权利要求1所述的方法,其中所说狭槽利用槽刨形成。
5.如权利要求1所述的方法,其中所说板利用半固化片连接在一起。
6.如权利要求1所述的方法,其中形成所说墨层的步骤包括以下子步骤:
在所说狭槽中填充墨;及
固化该墨。
7.如权利要求6所述的方法,其中在120-130℃的温度下干燥该墨60-100分钟,使之固化。
8.如权利要求1所述的方法,其中利用包括氢氧化钠的处理液去除所说墨层。
9.一种制造具有多层的印刷电路板的方法,包括以下步骤:
在多个板的每个上形成电路;
在第一板上形成窗口;
在第二板中形成多个狭槽,以便限定大于前述窗口的窗口区;
在所说第二板的所说多个所说狭槽中形成墨层;
把所说第一板和所说第二板连接在一起;
穿过所说第一板和第二板形成通孔,在其中镀敷金属,并腐蚀所说金属;
去掉所说狭槽中的所说墨层;及
去掉所说第二板的窗口区内的未形成所说狭槽的部分,从而形成多台阶窗口。
10.如权利要求9所述的方法,其中所说第一和第二板是敷铜箔叠片。
11.如权利要求9所述的方法,其中所述第二板的所说狭槽宽约0.2-3.2mm。
12.如权利要求9所述的方法,其中所说狭槽利用槽刨形成。
13.如权利要求9所述的方法,其中所说第一和第二板利用半固化片连接在一起。
14.如权利要求9所述的方法,其中形成所说墨层的步骤包括以下子步骤:
在所说狭槽中填充墨;及
固化该墨。
15.如权利要求14所述的方法,其中在120-130℃的温度下干燥该墨60-100分钟,使之固化。
16.如权利要求9所述的方法,其中利用包括氢氧化钠的处理液去除所说墨层。
17.一种制造印刷电路板方法,包括以下步骤:
在多个板的每个上形成电路;
在所说多个板中形成多个狭槽,以便限定具有不同尺寸的各窗口区;
把多个所说板连接在一起,从而形成多层电路板;
在各所说板的多个所说狭槽中形成墨层;
在多个所说板的每个中形成通孔,在其中镀敷金属,并腐蚀所说金属;
从所说狭槽中去掉所说墨层;及
去掉所说多个板上窗口区内的未形成所说狭槽的部分,从而在所说多层印刷电路中形成多台阶窗口。
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KR57637/1998 | 1998-12-23 | ||
KR1019980057637A KR100298897B1 (ko) | 1998-12-23 | 1998-12-23 | 인쇄회로기판제조방법 |
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CN1203741C true CN1203741C (zh) | 2005-05-25 |
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US (1) | US6393696B1 (zh) |
JP (1) | JP2000196237A (zh) |
KR (1) | KR100298897B1 (zh) |
CN (1) | CN1203741C (zh) |
DE (1) | DE19962422C2 (zh) |
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US6564454B1 (en) * | 2000-12-28 | 2003-05-20 | Amkor Technology, Inc. | Method of making and stacking a semiconductor package |
KR20030010887A (ko) * | 2001-07-27 | 2003-02-06 | 삼성전기주식회사 | 비지에이 기판의 제조방법 |
KR100438612B1 (ko) * | 2001-12-07 | 2004-07-02 | 엘지전자 주식회사 | 유기물질 마스킹을 이용한 다층 인쇄회로기판의제조방법과 그 기판을 이용한 반도체 패키지의 제조방법 |
KR100430001B1 (ko) * | 2001-12-18 | 2004-05-03 | 엘지전자 주식회사 | 다층기판의 제조방법, 그 다층기판의 패드 형성방법 및 그다층기판을 이용한 반도체 패키지의 제조방법 |
JP2007205908A (ja) * | 2006-02-02 | 2007-08-16 | Matsushita Electric Ind Co Ltd | 重量センサ |
US9713258B2 (en) * | 2006-04-27 | 2017-07-18 | International Business Machines Corporation | Integrated circuit chip packaging |
KR100772113B1 (ko) * | 2006-09-28 | 2007-11-01 | 주식회사 하이닉스반도체 | 입체 인쇄회로 기판 |
CN101460018B (zh) * | 2007-12-14 | 2011-02-16 | 华为技术有限公司 | 一种印制电路板及其制造方法、射频装置 |
WO2009155794A1 (zh) * | 2008-06-23 | 2009-12-30 | 华为技术有限公司 | 一种多层电路板及其制作方法 |
CN102299081B (zh) * | 2011-08-30 | 2013-12-04 | 深南电路有限公司 | 一种封装基板制造方法及封装基板 |
CN103037638B (zh) * | 2011-09-30 | 2015-05-06 | 无锡江南计算技术研究所 | 带有芯片窗口的待压合多层板的压合方法 |
US9161461B2 (en) * | 2012-06-14 | 2015-10-13 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Multilayer electronic structure with stepped holes |
DE102013226683A1 (de) | 2013-12-19 | 2015-06-25 | Robert Bosch Gmbh | Verfahren zur Herstellung von Hohlräumen bzw. Hinterschnitten in einer mehrlagigen Leiterplatte |
CN103745932B (zh) * | 2014-01-23 | 2016-04-13 | 无锡江南计算技术研究所 | Wb型封装基板的制作方法 |
TWI572267B (zh) * | 2014-09-29 | 2017-02-21 | 旭德科技股份有限公司 | 具有凹槽的多層線路板與其製作方法 |
US9609746B1 (en) * | 2015-12-14 | 2017-03-28 | Unimicron Technology Corp. | Circuit board structure and manufacturing method thereof |
CN108834336B (zh) * | 2018-08-27 | 2019-11-29 | 生益电子股份有限公司 | 一种pcb的制作方法 |
CN110933872B (zh) * | 2019-11-19 | 2021-09-21 | 广州广合科技股份有限公司 | 一种基于阶梯镀金插头式pcb电路板的分段制板方法 |
CN114096059B (zh) * | 2020-08-25 | 2023-10-10 | 宏恒胜电子科技(淮安)有限公司 | 线路板及其制作方法 |
CN112672536A (zh) * | 2020-12-29 | 2021-04-16 | 江苏恒宝智能系统技术有限公司 | 一种指纹识别卡及其制备方法 |
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CN114286507B (zh) * | 2022-01-19 | 2024-03-29 | 瑞华高科技电子工业园(厦门)有限公司 | 一种双面fpc及其制作方法 |
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EP0831528A3 (en) * | 1996-09-10 | 1999-12-22 | Hitachi Chemical Company, Ltd. | Multilayer wiring board for mounting semiconductor device and method of producing the same |
-
1998
- 1998-12-23 KR KR1019980057637A patent/KR100298897B1/ko not_active IP Right Cessation
-
1999
- 1999-12-21 US US09/469,795 patent/US6393696B1/en not_active Expired - Lifetime
- 1999-12-22 DE DE19962422A patent/DE19962422C2/de not_active Expired - Fee Related
- 1999-12-23 CN CNB991266633A patent/CN1203741C/zh not_active Expired - Fee Related
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US6393696B1 (en) | 2002-05-28 |
JP2000196237A (ja) | 2000-07-14 |
KR20000041683A (ko) | 2000-07-15 |
KR100298897B1 (ko) | 2001-09-22 |
DE19962422A1 (de) | 2000-08-31 |
DE19962422C2 (de) | 2003-10-02 |
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