CN1112726C - 形成半导体器件槽隔离的方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000002955 isolation Methods 0.000 title abstract description 16
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- 239000000758 substrate Substances 0.000 claims abstract description 24
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- 238000000151 deposition Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 229910007991 Si-N Inorganic materials 0.000 claims description 3
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- 238000000137 annealing Methods 0.000 claims description 3
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Abstract
一种形成槽隔离的方法包括在半导体衬底上依次形成垫氧化层和有源氮化层。通过腐蚀氮化层和垫氧化层形成槽掩模层。通过使用槽掩模层作掩模腐蚀半导体衬底以形成槽。在槽的底和两侧壁上形成氮化层。在氧化层上形成氧化掩模层，例如氮化物衬垫。淀积槽隔离层足以填满槽。通过使用平面化腐蚀除去槽隔离层直到氮化物衬垫的上表面暴露为止。进行离子注入或等离子体处理以破坏有源氮化层但不破坏衬底。除去槽隔离层直到半导体衬底上表面暴露为止。
Description
本发明涉及制造半导体器件的方法，特别涉及形成槽隔离的方法。
随着促进高密度DRAM的增加，器件隔离的方法已从常规的LOCOS(局部硅氧化)技术变为STI(浅槽隔离(Shallow trench isolation))技术。但是，在STI方法时，槽内壁中的氧化层的膨胀在槽中和有源区中产生浅坑(pit)。结果，半导体衬底的有源区中的漏电流增加。
为解决上面问题，氮化物衬垫(liner)已用作氧化掩模层，用于防止槽内壁在后续工艺中被氧化。通过使用氮化物衬垫，可以防止浅坑。但是，在利用磷酸进行的有源氮化层的腐蚀过程中氮化物衬垫被腐蚀到半导体衬底表面下面的一点(即氮化物衬垫向下凹陷)。这样，凹陷的氮化物衬垫使在腐蚀栅极(gate poly)的后续工艺中产生纵梁式残余物(stringer residual)。
为解决上述问题，现有技术，例如US专利号5447884展示了带有小于50埃的衬垫厚度的氮化物衬垫的浅槽隔离。
上述方法包括以下步骤：在半导体衬底上沉积含有至少一层氮化物的保护层；腐蚀透保护层，以形成一组隔离掩模孔；穿过该组隔离掩模孔腐蚀，以形成一组隔离槽；淀积厚度小于50埃的氮化物保角(conformal)衬垫；淀积厚度足以填满该组隔离槽的氧化物CVD层；去掉隔离槽外面的氧化物CVD层部分，从而暴露至少一层氮化物；在磷酸中剥离至少一层氮化区。
根据上面的方法，通过使用很薄的氮化物衬垫作为氧化掩模层防止了保角氮化物衬垫的凹陷。
但是，保角氮化物衬垫太薄，不能防止槽内壁被氧化。
因此，需要一种方法，它不仅能防止氮化物衬垫凹陷，又能防止槽内壁被氧化。
本发明用于解决上述问题，本发明的目的是防止在腐蚀有源氮化层过程中氮化物衬垫凹陷。
本发明又一目的是缩短有源氮化层的剥离时间。
本发明另一目的是提供半导体衬底中的浅槽隔离。
根据本发明，形成槽隔离的方法包括：在半导体衬底上形成垫氧化层(pad Otide layer)和有源氮化层；通过腐蚀半导体衬底形成确定槽形成区域的槽掩模层；使用槽掩模层作为掩模腐蚀半导体衬底，以形成槽。在槽底和两侧壁上形成氧化层，以消除在腐蚀半导体衬底步骤过程中产生的衬底损坏；在包括有源氮化层的槽上形成氧化掩模层，例如，氮化物衬垫，以便防止槽的底和两侧壁被氧化；淀积槽隔离层足以充满槽；进行退火工艺以致密化槽隔离层；去掉槽隔离层，直到暴露氮化物衬垫的上表面为止；在有源氮化层上进行离子注入或等离子体工艺；使用磷酸平面腐蚀槽掩模层，直到暴露半导体衬底的上表面为止。
根据本发明，在剥离之前破坏有源氮化层，使有源氮化层的剥离时间缩短成为可能，由此防止氮化物衬垫凹陷。
参照附图可以理解本发明，并且对本领域技术人员来说其目的将更明显，其中：
图1-图7是根据本发明的优选实施例形成槽隔的新方法。
下面参照附图说明本发明优选实施例。
图1-图7是表示根据本发明优选实施例形成槽隔的新方法的各个阶段的剖面图。
如图1所示，根据本发明优选实施例，在半导体衬底200上依次形成垫氧化层202和有源氮化层202b。通过已知光刻方法形成确定槽形成区域的槽掩模层202。此后，利用槽掩模层202作为掩模腐蚀半导体衬底，以形成槽203。
参见图2，在槽203的底和两侧壁上形成氧化层204，以除去由腐蚀半导体衬底200的步骤引起的硅晶格中的缺陷。氧化层例如是二氧化硅(SiO2)。
参见图3，利用LPCVD在包括槽203的有源氮化层202b上形成氧化掩模层，例如氮化物衬垫205，以防止槽内壁被氧化。氮化物衬垫205是由，例如氮化硅(Si3N4)形成。所形成的氮化物衬垫205厚度约为300埃到600埃，足以防止氧化。
参见图4，淀积槽隔离层206，例如USG(O3TEOS)层，以填满槽203。此后，进行退火工艺以致密化槽隔离层206。
参见图5，使用平面化腐蚀，例如CMP工艺除去槽隔离层206，直到氮化物衬垫205的上表面暴露为止。
参见图6，为了削弱有源氮化层202b的Si-N键合力而不破坏半导体衬底200，在有源氮化层205上进行离子注入或等离子体工艺。由于此离子注入或等离子体工艺，缩短了有源氮化层202b的剥离时间。上面的离子注入是通过以剂量范围约从1×1010cm-2到1×1017cm-2、加速能范围约从10kev到100kev注入选自下列的一种离子进行的：P、As、B、Ar和Si。另一方面，上面的等离子体工艺是通过以功率范围约从10W到5000W、气压范围约从1×10-4乇到700乇使用选自下列的一种离子进行的：Xe、Kr和Ar。
如图7所示，通过使用磷酸腐蚀槽掩模层202直到半导体衬底200的表面暴露为止，从而形成槽隔离208。
根据本发明，在剥离有源氮化层之前在有源氮化层上进行破坏有源氮化层工艺，例如离子注入工艺或等离子体工艺。这样，由于削弱了有源氮化层中Si-N键合力而缩短了有源氮化层的剥离时间。因而，可以避免氮化物衬垫的凹陷现象，并提高了槽的隔离特性。
Claims (9)
1.一种在半导体器件中形成槽隔离的方法，包括以下步骤：
在半导体衬底上依次形成垫氧化层和有源氮化层；
通过腐蚀所述有源氮化层和垫氧化层形成槽掩模层，所述槽掩模层确定槽形成区域；
使用槽掩模层作为掩模，腐蚀所述半导体衬底以形成槽；
在所述槽的底和两侧壁上形成氧化层以除去在腐蚀所述半导体衬底的所述步骤过程中产生的衬底损坏；
在包括所述有源氮化物衬垫的所述槽上形成氮化物衬垫，以防止所述槽的底和两侧壁被氧化；
淀积槽隔离层以填满所述槽；
进行退火工艺以致密化所述槽隔离层；
通过平面腐蚀去掉所述槽隔离层，直到所述氮化物衬垫暴露为止；
通过离子注入或等离子体工艺破坏所述有源氮化层以消弱Si-N键合力；
剥离所述槽掩模层直到所述半导体衬底上表面暴露为止。
2.如权利要求1的方法，其中破坏所述有源氮化层的步骤是通过离子注入进行的。
3.如权利要求2的方法，其中所述离子注入是通过使用选自下列中的一种离子进行的：P、As、B、Ar和Si。
4.如权利要求2的方法，其中所述离子注入是以剂量范围约从10×1010cm-2到1×1017cm-2进行的。
5.如权利要求2的方法，其中所述离子注入是在加速能范围约从10kev到1000kev进行的。
6.如权利要求1的方法，其中破坏所述有源氮化层的步骤是通过等离子体工艺进行的。
7.如权利要求6的方法，其中所述等离子体工艺是通过使用选自下列中的一种离子进行的：Xe、Kr和Ar。
8.如权利要求6的方法，其中所述等离子体工艺是在功率范围从10W到5000W进行的。
9.如权利要求6的方法，其中所述等离子体工艺是在压力范围从1×10-4乇到700乇进行的。
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| KR22584/98 | 1998-06-16 | ||
| KR22584/1998 | 1998-06-16 | ||
| KR1019980022584A KR100286736B1 (ko) | 1998-06-16 | 1998-06-16 | 트렌치 격리 형성 방법 |
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| CN1239323A CN1239323A (zh) | 1999-12-22 |
| CN1112726C true CN1112726C (zh) | 2003-06-25 |
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| US (1) | US6329266B1 (zh) |
| JP (1) | JP2000031267A (zh) |
| KR (1) | KR100286736B1 (zh) |
| CN (1) | CN1112726C (zh) |
| TW (1) | TW452927B (zh) |
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| US5786262A (en) | 1997-04-09 | 1998-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-planarized gapfilling for shallow trench isolation |
| US5726090A (en) | 1997-05-01 | 1998-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gap-filling of O3 -TEOS for shallow trench isolation |
| US5741740A (en) | 1997-06-12 | 1998-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Shallow trench isolation (STI) method employing gap filling silicon oxide dielectric layer |
| US5837612A (en) | 1997-08-01 | 1998-11-17 | Motorola, Inc. | Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation |
| US5811345A (en) | 1997-09-18 | 1998-09-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Planarization of shallow- trench- isolation without chemical mechanical polishing |
| US6080637A (en) * | 1998-12-07 | 2000-06-27 | Taiwan Semiconductor Manufacturing Company | Shallow trench isolation technology to eliminate a kink effect |
| US6037238A (en) * | 1999-01-04 | 2000-03-14 | Vanguard International Semiconductor Corporation | Process to reduce defect formation occurring during shallow trench isolation formation |
-
1998
- 1998-06-16 KR KR1019980022584A patent/KR100286736B1/ko not_active IP Right Cessation
- 1998-07-24 TW TW087112098A patent/TW452927B/zh not_active IP Right Cessation
- 1998-12-11 CN CN98125264A patent/CN1112726C/zh not_active Expired - Fee Related
-
1999
- 1999-06-01 US US09/323,500 patent/US6329266B1/en not_active Expired - Fee Related
- 1999-06-15 JP JP11168057A patent/JP2000031267A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| TW452927B (en) | 2001-09-01 |
| CN1239323A (zh) | 1999-12-22 |
| US6329266B1 (en) | 2001-12-11 |
| KR100286736B1 (ko) | 2001-04-16 |
| JP2000031267A (ja) | 2000-01-28 |
| KR20000002040A (ko) | 2000-01-15 |
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