TW452927B - A method of forming a trench isolation of a semiconductor device - Google Patents
A method of forming a trench isolation of a semiconductor device Download PDFInfo
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- TW452927B TW452927B TW087112098A TW87112098A TW452927B TW 452927 B TW452927 B TW 452927B TW 087112098 A TW087112098 A TW 087112098A TW 87112098 A TW87112098 A TW 87112098A TW 452927 B TW452927 B TW 452927B
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- trench
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000002955 isolation Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 229910007991 Si-N Inorganic materials 0.000 claims description 3
- 229910006294 Si—N Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 238000005496 tempering Methods 0.000 claims description 3
- 230000001133 acceleration Effects 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 230000002079 cooperative effect Effects 0.000 claims 1
- 230000000873 masking effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 62
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 235000017166 Bambusa arundinacea Nutrition 0.000 description 1
- 235000017491 Bambusa tulda Nutrition 0.000 description 1
- 241001330002 Bambuseae Species 0.000 description 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- XLPNRFXSYBURJM-UHFFFAOYSA-H [U+6].[O-]P([O-])([O-])=O.[O-]P([O-])([O-])=O Chemical compound [U+6].[O-]P([O-])([O-])=O.[O-]P([O-])([O-])=O XLPNRFXSYBURJM-UHFFFAOYSA-H 0.000 description 1
- 239000011425 bamboo Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- -1 hafnium nitride Chemical class 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910000163 uranium phosphate Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Description
45292 3 623pif.doc/002 A7 B7 五、發明説明(ί ) 本發明是有關於一種半導體元件的製造方法,且特別 是有關於一種形成溝渠隔離的方法。 隨著高密度動態隨機存取記憶體(DRAMs)的提昇,元 件隔離之方法已從傳統區域氧化法(Local Oxidation of SiHcon; LOCOS)技術演變至淺溝渠隔離(Shallow Trench Isolation ; STI)技術。然而,若是STI的方法,由於溝渠內 壁之氧化層的擴張現象,將會在溝渠及主動區造成淺凹洞 的情形。因此,將會導致半導體基底之主動區的漏電流增 加。 爲了解決上述問題,在後續製程中,襯氮化層被用做 爲氧化罩幕層來防止溝渠內壁遭受到氧化。經由使用襯氮 化層,可避免淺凹洞現象產生。然而,在使用磷酸鈾刻主 動氮化層期間,襯氮化層會被蝕刻至低於半導體基底表面 的位置(亦即襯氮化層會有凹陷現象)。因此,在後續蝕刻 多晶閘製程時,此凹陷之襯氮化層將會造成一橫樑殘餘物 (stringer residue) ° 爲了解決以上問題,習知例如美國專利第5,447,884號 揭露出一種使用厚度小於5〇A之襯氮化層之淺溝渠隔離的 製造方法。 如上所述,其方法包括下列步驟:沉積一保護層包括 至少一層氮化層於半導體基底上;蝕刻保護層以形成隔離 罩幕凹洞;經由隔離罩幕凹洞蝕刻以形成一隔離溝渠;沉 積一層厚度小爲50A之襯氮化層;以化學氣相沉積法(CVD) 沉積一層氧化層塡滿隔離溝渠;去除隔離溝渠外之部分-氧 - - - - ^^^1 ί 1^1 lr ^. nn _ - 0¾-Mt (請先閱讀背面之注意事項再填寫本頁) 經米-部屮ίι:ί!:ϊν·局只工消於合竹私印y ^紙张尺度適in中國S家標冷(rNS ) Λ4現格(210X297公釐> 5292 7 3623pH'.doc/002 五、發明説明(久) 化層,直到暴露出至少一氮化層爲止;以及,以磷酸剝除 上述至少一氮化層。 綜土所述,經由使用一很薄的襯氮化層來當作氧化罩 幕層,可防止襯氮化層發生凹陷現象。 然而,由於櫬氮化層太薄,導致無法防止溝渠內壁遭 受到氧化。 因此,必須要有一種方法,其不僅要能防止襯氮化層 發生凹陷現象,而且要能防止溝渠內壁遭受到氧化。 有鑒於此,本發明的目的就是在提供一種形成半導體 元件之溝渠隔離的方法,以防止襯氮化層在蝕刻主動氮化 層期間發生凹陷現象。 本發明的另一目的,提出一種形成半導體元件之溝渠 隔離的方法,以縮短主動氮化層的剝除時間。 本發明的再一目的,在於提出一種半導體基底之淺溝 渠隔離的製造方法。 爲達成本發明之上述和其他目的,一種形成溝渠隔離 的方法,包括依序形成一墊氧化層與一主動氮化層於一半 導體基底上。形成一溝渠罩幕層,並經由蝕刻半導體基底 以定義出一溝渠形成區。以溝渠罩幕層爲罩幕,蝕刻半導 體基底以形成一溝渠。形成一氧化層於溝渠底部及其側 壁,以去除蝕刻半導體基底之步驟期間所造成之基底損 害。形成一氧化罩幕層例如襯氮化層覆蓋主動氮化層與溝 渠,以防止溝渠底部及其內壁遭受氧化。沉積一溝渠隔離 層塡滿溝渠。進行一回火製程以硬化溝渠隔離層。去歐溝 (誚先閱讀背面之注意事項再填寫本頁) 裝- 訂 本纸张尺度进用屮國國家標?M rNS ) Λ4規格(210X297公釐) A7 B7 452927 3023pit\d〇c/002 五、發明説明() 渠隔離層直到暴露出襯氮化層之上表面爲止。於主動氮化 層上進行離子植入或電漿製程。使用磷酸蝕刻溝渠罩幕 層,直到暴露出半導體基底之上表面爲止。 依照本發明之較佳實施例,在剝除主動氮化層之前先 加以損壞,如此可縮短主動氮化層之剝除時間,並且可避 免襯氮化層發生凹陷現象。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉一較佳實施例,並配合所附圖式,作詳 細說明如下: 圖式之簡單說明: 第1圖至第7圖繪示的是依照本發明一較佳實施例之 一種形成溝渠隔離之方法的流程剖面圖。 竇施例 第1圖至第7圖繪不的是依照本發明一較佳實施例之 一種形成溝渠隔離之方法的流程剖面圖。 依照本發明一較佳實施例,首先請參照第1圖,依序 形成一墊氧化層202a與一主動氮化層202b於一半導體基 底200上。接著,使用傳統微影製程定義溝渠罩幕層202 以形成一溝渠形成區。之後,以溝渠罩幕層202爲罩幕’ 蝕刻半導體基底200以形成一溝渠203。 接著請參照第2圖’形成一氧化層》(Μ於溝渠2〇3底 部及其側壁上,並經由蝕刻半導體基底200的步驟,以去 除矽晶格上之缺陷,其中氧化層204之材質例如是二氧化 矽(Si〇2)。 - (銪先閲讀背而之注意事項再填寫本頁) 裝· 訂 經请部t #'^τ-·ν-^β Ί,消处合竹.社印裝 本紙張尺度进川中國國家標唪(('NS ) Λ4規格(2丨0X297公釐) ά^ 292 7 3623pii.doc/0 02 A7 B7 五、發明説明(ί) 再來請參照第3圖,使用低壓化學氣相沉積法 (LPCVD),形成一氧化罩幕層例如襯氮化層205覆蓋主動 氮化層2〇2b與溝渠203,以防止溝渠內壁遭受氧化,其中 襯氮化層205之材質例如是氮化矽(Si3N4)。上述中,襯氮 化層205之形成厚度約在300A至600A之間,以避免氧化 作用。 接著請參照第4圖,沉積一層溝渠隔離層206例如是 一 USG(03 TEOS)層塡滿覆蓋溝渠2〇3。之後,進行一回火 製程,以硬化溝渠隔離層206。 之後請參照第5圖,進行平坦化-蝕刻製程例如化學機 械硏磨法(CMP),去除溝渠隔離層2〇6直到暴露出襯氮化 層205之上表面爲止。 接著請參照第6圖,於主動氮化層202b上進行一離子 植入或電漿製程,以減弱主動氮化層2〇2b之Si-N接合力, 並且不傷害到半導體基底200。由於此離子植入或電漿製 程的因素,將使得主動氮化層202b的剝除時間縮短。經由 植入一劑量範圍約在lXlO'm·2至lxl0l7cm·2間之選擇 離子包括P,As,B,Ar與Si,且其加速能量範圍約在l〇keV 至lOOOkeV間,來完成上述離子植入製程。另一方面,可 經由使用選擇離子包括Xe,Kr及Ar,其功率能量範圍約在 10W至1000W間,且其壓力範圍約在丨X 10_4Torr至700 Τοιτ間,來完成上述電漿製程。 再來請參照第7圖,使用磷酸蝕刻溝渠罩幕層202, 直到暴露出半導體基底200表面爲止,以形成溝渠隔離 (誚先閱讀背面之注意事項再填寫本頁) -6 本紙张尺度適州中國囤家標肀((、NS ) Λ4规格{ 210X 297公雜) 452927 302 3pii'.doc/002 B7 五、發明説明(女) 206 ° 依照上述本發明之毀損主動氮化層製程,例如可在剝 除主勤氮化層之前,先於主動氮化層上進行離子植入或電 漿製程。如此,由於主動氮化層之Si-N接合力減弱,使得 主動氮化層之剝除時間縮短。因此,可避免溝渠之襯氮化 層的凹陷現象產生,並且改善了溝渠之隔離特性。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍內,當可作各種之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 -----I m : ; I _ CV·κ------ - II___I 丁 - -5 («先閱讀背面之注意事項再填寫本頁) 8 本紙张尺度適州中國國家標卒((’NS } Λ4規格(2ίΟΧ297公釐)
Claims (1)
- 4 經濟部中央標率局員工消費合作社印裝 g 2 q 2 7 —— — - A8 BS C8 3623 pif.doc/002 〇8六、申請專利範圍 1. 一種形成半導體元件之溝渠隔離的方法,包括下列步 驟: 依序形成一墊氧化層與一主動氮化層於一半導體基底 上; 蝕刻該墊氧化層與該主動氮化層以形成一溝渠罩幕 層,該溝渠罩幕層定義出一溝渠形成區; 以該溝渠罩幕層爲一罩幕,蝕刻該半導體基底以形成 一溝渠; 形成一氧化層於該溝渠底部及其側壁,以去除蝕刻該 半導體基底之該步驟期間所造成之一基底損害; 形成一襯氮化層覆蓋該主動氮化層與該溝渠,以防止 該溝渠底部及其內壁遭受氧化; 沉積一溝渠隔離層塡滿該溝渠; 進行一回火製程,以硬化該溝渠隔離層; 進行一平坦化-蝕刻製程,以去除該溝渠隔離層直到暴 露出該襯氮化層之上表面爲止; 損害該主動氮化層,以減弱該主動氮化層之一 Si-N接 合力;以及 剝除該溝渠罩幕層,直到暴露出該半導體基底之上表 面爲止。 2. 如申請專利範圍第ί項所述之方法,其中損害該主動 氮化層的步驟係使用離子植入製程。 3. 如申請專利範圍第2項所述之方法,其中該離子植入 製程所使用之一選擇離子,包括P,As,B,Ar與Si。 * (請先閲讀背面之注意事項再填寫本頁) ,-Λ衣. 、\ηβ 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 4 5292 7 A8 B8 C8 3623pit'.doc/Cl02 〇8 六、申請專利範圍 4. 如申請專利範圍第2項所述之方法,其中該離子植入 製程之一劑量範圍約在lXlO^m·2至lX10l7cm·2間。 5. 如申請專利範圍第2項所述之方法,其中該離子植入 製程之一加速能量範圍約在lOlceV至lOOOkeV間。 6. 如申請專利範圍第1項所述之方法,其中損害該主動 氮化層的步驟係使用電漿製程。 7. 如申請專利範圍第6項所述之方法,其中該電漿製程 所使用之一選擇離子,包括Xe,Kr及Ar。 8. 如申請專利範圍第6項所述之方法,其中該電漿製程 之一功率範圍約在10W至1000W間。 9. 如申請專利範圍第6項所述之方法,其中該電漿製程 之一壓力範圍約在1 X ΙΟΊοπ·至700 Torr間。 (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央標率局員工消費合作社印策 本紙張尺度通用中國國家榡準(CNS ) A4说格(210X297公釐)
Applications Claiming Priority (1)
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KR1019980022584A KR100286736B1 (ko) | 1998-06-16 | 1998-06-16 | 트렌치 격리 형성 방법 |
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US (1) | US6329266B1 (zh) |
JP (1) | JP2000031267A (zh) |
KR (1) | KR100286736B1 (zh) |
CN (1) | CN1112726C (zh) |
TW (1) | TW452927B (zh) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7157385B2 (en) * | 2003-09-05 | 2007-01-02 | Micron Technology, Inc. | Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry |
US6300219B1 (en) * | 1999-08-30 | 2001-10-09 | Micron Technology, Inc. | Method of forming trench isolation regions |
DE19947539B4 (de) * | 1999-10-02 | 2006-04-20 | Bruker Biospin Gmbh | Gradientenspulenanordnung mit Dämpfung innerer mechanischer Schwingungen |
JP2001118919A (ja) * | 1999-10-15 | 2001-04-27 | Seiko Epson Corp | 半導体装置およびその製造方法 |
KR100308793B1 (ko) * | 1999-10-18 | 2001-11-02 | 윤종용 | 반도체 소자 제조방법 |
KR100557943B1 (ko) * | 2000-06-30 | 2006-03-10 | 주식회사 하이닉스반도체 | 플라즈마공정에 의한 에스티아이 공정의 특성개선방법 |
JP4346228B2 (ja) * | 2000-09-21 | 2009-10-21 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
US6537917B2 (en) * | 2001-03-13 | 2003-03-25 | Macronix International Co., Ltd. | Method for fabricating electrically insulating layers |
US20020197823A1 (en) * | 2001-05-18 | 2002-12-26 | Yoo Jae-Yoon | Isolation method for semiconductor device |
JP2003017555A (ja) | 2001-06-29 | 2003-01-17 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2003273206A (ja) | 2002-03-18 | 2003-09-26 | Fujitsu Ltd | 半導体装置とその製造方法 |
US6746924B1 (en) * | 2003-02-27 | 2004-06-08 | International Business Machines Corporation | Method of forming asymmetric extension mosfet using a drain side spacer |
US7125815B2 (en) * | 2003-07-07 | 2006-10-24 | Micron Technology, Inc. | Methods of forming a phosphorous doped silicon dioxide comprising layer |
KR100509846B1 (ko) * | 2003-08-02 | 2005-08-23 | 동부아남반도체 주식회사 | 반도체 소자를 위한 아이솔레이션 방법 |
US7053010B2 (en) * | 2004-03-22 | 2006-05-30 | Micron Technology, Inc. | Methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming arrays of memory cells |
KR100600055B1 (ko) * | 2004-06-30 | 2006-07-13 | 주식회사 하이닉스반도체 | 리프팅을 방지한 반도체소자의 소자분리 방법 |
US7235459B2 (en) * | 2004-08-31 | 2007-06-26 | Micron Technology, Inc. | Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry |
JP2006108629A (ja) | 2004-09-10 | 2006-04-20 | Toshiba Corp | 半導体装置の製造方法 |
US7217634B2 (en) * | 2005-02-17 | 2007-05-15 | Micron Technology, Inc. | Methods of forming integrated circuitry |
US7510966B2 (en) * | 2005-03-07 | 2009-03-31 | Micron Technology, Inc. | Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines |
US8012847B2 (en) | 2005-04-01 | 2011-09-06 | Micron Technology, Inc. | Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry |
JP5130677B2 (ja) * | 2006-08-16 | 2013-01-30 | ヤマハ株式会社 | 半導体装置の製法 |
JP2010027904A (ja) * | 2008-07-22 | 2010-02-04 | Elpida Memory Inc | 半導体装置の製造方法 |
US7998832B2 (en) * | 2008-08-27 | 2011-08-16 | Advanced Micro Devices, Inc. | Semiconductor device with isolation trench liner, and related fabrication methods |
US8105956B2 (en) | 2009-10-20 | 2012-01-31 | Micron Technology, Inc. | Methods of forming silicon oxides and methods of forming interlevel dielectrics |
US9318370B2 (en) | 2011-08-04 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-k dielectric liners in shallow trench isolations |
CN103367226B (zh) * | 2012-03-29 | 2016-06-08 | 中国科学院微电子研究所 | 半导体器件制造方法 |
CN103515234B (zh) * | 2012-06-25 | 2016-12-21 | 中芯国际集成电路制造(上海)有限公司 | 形成FinFET的方法 |
US20160079034A1 (en) * | 2014-09-12 | 2016-03-17 | Applied Materials Inc. | Flowable film properties tuning using implantation |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2566179B1 (fr) | 1984-06-14 | 1986-08-22 | Commissariat Energie Atomique | Procede d'autopositionnement d'un oxyde de champ localise par rapport a une tranchee d'isolement |
KR920022380A (ko) | 1991-05-18 | 1992-12-19 | 김광호 | 반도체장치의 소자분리방법 |
KR960008518B1 (en) | 1991-10-02 | 1996-06-26 | Samsung Electronics Co Ltd | Manufacturing method and apparatus of semiconductor device |
US5447884A (en) | 1994-06-29 | 1995-09-05 | International Business Machines Corporation | Shallow trench isolation with thin nitride liner |
KR0147630B1 (ko) | 1995-04-21 | 1998-11-02 | 김광호 | 반도체 장치의 소자분리방법 |
US5679599A (en) | 1995-06-22 | 1997-10-21 | Advanced Micro Devices, Inc. | Isolation using self-aligned trench formation and conventional LOCOS |
KR100214068B1 (ko) | 1995-11-21 | 1999-08-02 | 김영환 | 반도체 장치의 소자분리막 형성방법 |
KR0179554B1 (ko) | 1995-11-30 | 1999-04-15 | 김주용 | 반도체 소자의 소자분리절연막 형성방법 |
JPH10144785A (ja) | 1996-11-06 | 1998-05-29 | Samsung Electron Co Ltd | 半導体装置及びその素子分離方法 |
US5763315A (en) * | 1997-01-28 | 1998-06-09 | International Business Machines Corporation | Shallow trench isolation with oxide-nitride/oxynitride liner |
US5817566A (en) | 1997-03-03 | 1998-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Trench filling method employing oxygen densified gap filling silicon oxide layer formed with low ozone concentration |
US5786262A (en) | 1997-04-09 | 1998-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-planarized gapfilling for shallow trench isolation |
US5726090A (en) | 1997-05-01 | 1998-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gap-filling of O3 -TEOS for shallow trench isolation |
US5741740A (en) | 1997-06-12 | 1998-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Shallow trench isolation (STI) method employing gap filling silicon oxide dielectric layer |
US5837612A (en) | 1997-08-01 | 1998-11-17 | Motorola, Inc. | Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation |
US5811345A (en) | 1997-09-18 | 1998-09-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Planarization of shallow- trench- isolation without chemical mechanical polishing |
US6080637A (en) * | 1998-12-07 | 2000-06-27 | Taiwan Semiconductor Manufacturing Company | Shallow trench isolation technology to eliminate a kink effect |
US6037238A (en) * | 1999-01-04 | 2000-03-14 | Vanguard International Semiconductor Corporation | Process to reduce defect formation occurring during shallow trench isolation formation |
-
1998
- 1998-06-16 KR KR1019980022584A patent/KR100286736B1/ko not_active IP Right Cessation
- 1998-07-24 TW TW087112098A patent/TW452927B/zh not_active IP Right Cessation
- 1998-12-11 CN CN98125264A patent/CN1112726C/zh not_active Expired - Fee Related
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1999
- 1999-06-01 US US09/323,500 patent/US6329266B1/en not_active Expired - Fee Related
- 1999-06-15 JP JP11168057A patent/JP2000031267A/ja active Pending
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CN1112726C (zh) | 2003-06-25 |
US6329266B1 (en) | 2001-12-11 |
KR100286736B1 (ko) | 2001-04-16 |
JP2000031267A (ja) | 2000-01-28 |
CN1239323A (zh) | 1999-12-22 |
KR20000002040A (ko) | 2000-01-15 |
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