558793 6075twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（I ) 本發明是有關於一種積體電路元件（integrated circuits，1C)隔離（isolation)的製造方法，且特別是有 關於一種淺溝渠隔離（shallow trench isolation, STI) 的製造方法。 一完整的積體電路，通常是由成千上萬個金氣半導 體（Metal Oxide Semiconductor，M0S)電晶體（Transistor) 所組成，爲防止這些相鄰的電晶體間發生短路的現象，因 此必須在相鄰的電晶體間加入用以電性隔絕的隔離結構。 傳統半導體製程所使用的隔離結構爲場氧化層 (field oxide，FOX)，其形成方法係使用區域氧化法（local oxidation，LOCOS)，然而，由於區域氧化法所形成之場 氧化層存在著多項缺點，包括應力產生之相關問題，以及 隔離結構周圍鳥嘴區（bird’s beak)之形成等，特別是鳥 嘴區的形成，導致在尺寸逐漸縮小的元件製造上，此種場 氧化層隔離結構已不能提供有效的隔離效果。 淺溝渠隔離法是一種利用非等向性鈾刻方法在半導體 基底中形成溝渠，然後在此溝渠中塡入氧化矽，以形成元 件之隔離區的技術。由於淺溝渠隔離法所形成之元件隔離 區可避免局部區域氧化法隔離技術中鳥嘴侵蝕（bi rcTs beak encroachment)的缺點，因此，爲了因應兀件臨界尺 寸（critical dimension，CD)逐漸縮小的趨勢’在微小尺 寸下具有良好隔離效果的淺溝渠隔離結構，成了深次微米 製程主要的隔離結構。 第1A圖至第1C圖繪示爲傳統的一種淺溝渠隔離製程 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂---------線 <請先閱讀背面之注意事項再填寫本頁) 558793 A7 B7 6075twf . doc/006 五、發明說明（zo 的製造流程剖面示意圖。 請參照第1A圖，典型的方法係在基底1〇〇上形成一層 墊氧化層102與圖案化氮化矽層104,再以氮化矽層1〇4 爲蝕刻罩幕，在基底100中蝕刻出溝渠106。接著，在溝 渠106所裸露之基底1〇〇的表面上形成一層襯氧化層108。 其後，於基底1〇〇上覆蓋一層氧化矽層110，以覆蓋氮化 矽層104，並將溝渠106塡滿。 其後，請參照第1B圖，以氮化矽層104作爲硏磨終 止層，利用化學機械硏磨法去除多餘的氧化矽層110，留 下溝渠106之中的氧化矽層110。 之後，請參照第1C圖，去除氮化矽層104，並以氫氟 酸溶液去除墊氧化層102，以使留下之氧化矽層110在基 底100中形成兀件隔離區。 隨著積體電路元件高密度的需求，元件與淺溝渠隔離 結構必須隨之縮小，以使元件能夠高密度積集化’爲了確 保隔離效果，淺溝渠隔離結構必須達一固定深度才行，然 而積集度提昇將會縮小溝渠106的面積’如此會增加溝榘 106的高寬比（aspect ratio)，而導致介電層塡入溝榘的 困難度增加，介電材質無法順利塡入將會在淺溝渠隔離結 構中產生空隙。 有鑑於此，本發明提供一種淺溝渠隔離的製造方法， 可以降低溝渠的高寬比，降低介電層塡入溝渠的困難度， 而且還可以使淺溝渠隔離結構的隔離效果不會因爲溝橥的 高寬比降低而受到影響。 4 ------------裝--------訂---------線^^· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 558793 A7 6〇75tWf.doc/006558793 6075twf.doc / 006 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (I) The present invention relates to a method for manufacturing integrated circuits (1C) isolation, and In particular, it relates to a method for manufacturing shallow trench isolation (STI). A complete integrated circuit is usually composed of thousands of Metal Oxide Semiconductor (MOS) transistors. In order to prevent short circuits between these adjacent transistors, it is necessary to An isolation structure is added between adjacent transistors for electrical isolation. The isolation structure used in traditional semiconductor processes is field oxide (FOX). The formation method uses local oxidation (LOCOS). However, the field oxide layer formed by the area oxidation method has many disadvantages. , Including problems related to stress generation, and the formation of the bird's beak area around the isolation structure, especially the formation of the bird's beak area, which has led to the reduction in size of component manufacturing, such field oxide isolation structures can no longer be used. Provide effective isolation. Shallow trench isolation is a technique that uses a non-isotropic uranium engraving method to form a trench in a semiconductor substrate, and then injects silicon oxide into the trench to form an isolation region for the element. Because the element isolation area formed by the shallow trench isolation method can avoid the shortcomings of bircTs beak encroachment in the isolation technology of local area oxidation, in order to respond to the trend of the critical dimension (CD) of components gradually shrinking 'The shallow trench isolation structure with good isolation effect in the small size has become the main isolation structure for deep sub-micron processes. Figures 1A to 1C show a traditional shallow trench isolation process. 3 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------- pack- ------- Order --------- line < Please read the notes on the back before filling this page) 558793 A7 B7 6075twf .doc / 006 V. Description of the invention (Zo's manufacturing process profile Please refer to FIG. 1A, a typical method is to form a pad oxide layer 102 and a patterned silicon nitride layer 104 on the substrate 100, and then use the silicon nitride layer 104 as an etching mask on the substrate 100. The trench 106 is etched in the middle. Then, a liner oxide layer 108 is formed on the surface of the substrate 100 exposed by the trench 106. Thereafter, a silicon oxide layer 110 is covered on the substrate 100 to cover the silicon nitride layer. 104, and fill the trench 106. Thereafter, referring to FIG. 1B, the silicon nitride layer 104 is used as a honing stop layer, and the excess silicon oxide layer 110 is removed by chemical mechanical honing, leaving the trench 106 The silicon oxide layer 110. After that, referring to FIG. 1C, the silicon nitride layer 104 is removed, and the pad oxide layer 102 is removed with a hydrofluoric acid solution so that the remaining The underlying silicon oxide layer 110 forms an element isolation region in the substrate 100. With the demand for high-density integrated circuit components, the isolation structure between the element and the shallow trench must be reduced in order to enable the element to be densely integrated. Isolation effect, the shallow trench isolation structure must reach a fixed depth. However, the increase of the accumulation will reduce the area of the trench 106. This will increase the aspect ratio of the trench 106 and cause the dielectric layer to penetrate. Increasing the difficulty of trenches, the failure of the dielectric material to penetrate smoothly will create voids in the shallow trench isolation structure. In view of this, the present invention provides a manufacturing method for shallow trench isolation, which can reduce the aspect ratio of trenches and reduce the dielectric. Difficulty of the electric layer to penetrate the trench, and the isolation effect of the shallow trench isolation structure will not be affected by the reduction of the aspect ratio of the trench. 4 ------------ Installation- ------ Order --------- line ^^ · (Please read the notes on the back before filling out this page) Printed on paper standards for employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, this paper applies Chinese national standards (CNS) A4 specifications (210 X 297 public love 558793 A7 6〇75tWf.doc / 006
本發明提供一種淺溝渠隔離的製造方法，包括提供一 個半導體基底，其上依序形成有一層墊氧化層與一層罩幕 層’進行微影與蝕刻製程去除部分的罩幕層、墊氧化層與 基底，以在基底中形成溝渠。進行氧化步驟，使暴露在溝 渠中的基底氧化形成一層襯氧化層，然後去除溝渠底部的 襯氧化層’以暴露出溝渠底部的基底。全面沈積一層多晶 矽靥於罩幕層上，並塡入溝渠中，再利用等向性蝕刻步驟 去除罩幕層上方以及溝渠中部分的多晶矽層，剩餘的多晶 石夕在溝渠中形成一個多晶砂插塞。全面沈積一薄且共形的 阻擋靥，再於阻擋層上沈積一層絕緣材料，利用化學機械 硏磨法去除罩幕層上方以及溝渠以外的絕緣材料與阻擋 Μ ’再將罩幕層剝除即完成淺溝渠隔離的製作。 以本發明提供之淺溝渠隔離的製造方法，可以降低介 電材料塡充入溝渠的高寬比，因此可以降低介電材料塡入 的困難度，但是隔離效果可由形成於溝渠側壁的襯氧化層 來提供，因此無須擔心隔離效果因爲溝渠變淺而降低。 塡充於溝渠中的多晶矽很可能在後續製程中氧化，氧 化开^成的二氧化砂具有較大的體積，體積的改變會對製作 出的元件產生很大的應力，元件的效能會因而受到影響， 而本發明提供一層阻擋層覆蓋於多晶矽上，之後再塡入介 電材料，如此可避免多晶矽進一步的氧化。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下·· 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ▼裝--------訂---------線赢 經濟部智慧財產局員工消費合作社印製 558793 6075twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（+) 圖式之簡單說明： 第1A圖至第1C圖繪示爲傳統的一種淺溝渠隔離製程 的製造流程剖面示意圖；以及 第2A圖至第2F繪示依照本發明一較佳實施例的一種 淺溝渠隔離的製造流程剖面圖。 圖示標記說明： 100，200 基底 102, 202 墊氧化層 104，204 氮化砂層 106，206 溝渠 108，208，208A 襯氧化層 110 氧化砂層 210 多晶矽層 210a 多晶矽插塞 212，212a 阻擋層 214, 214a 介電層 實施例 第2A圖至第2F繪示依照本發明一較佳實施例的一種 淺溝渠隔離的製造流程剖面圖。 請參照第2A圖，提供半導體基底200，在基底200上 依序覆蓋一層墊氧化層202與一層罩幕層204，其中罩幕 層204之材質較佳爲氮化矽。進行微影與蝕刻製程，去除 部分的罩幕層204、墊氧化層202與基底200,以在基底200 中形成溝渠206 ;再形成溝渠206以後，進行一道濕蝕刻 6 -----------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 558793 6075twf.d〇c/006 A7 B7 五、發明說明（艾） 步驟，此步驟會去除部分暴露在溝渠206中的墊氧化層 202，因此墊氧化層202會呈現些許的凹陷。 (請先閱讀背面之注意事項再填寫本頁) 請參照第2B圖，對暴露於溝渠206中的基底200進行 氧化，藉以在基底200表面形成一層襯氧化層208。 接著，如第2C圖所示，去除溝渠206底部的襯氧化層 208,藉以暴露出溝渠206底部的基底200,此時在溝渠206 側壁仍有襯氧化層208存在，其中去除襯氧化層208的步 驟是以非等向性的蝕刻法達成，比如爲反應性離子蝕刻 (RIE)，在暴露出溝渠206底部的基底200以後，在罩幕 層204上與溝渠206中沈積一層多晶矽層210，沈積的多 晶矽層210厚度以不會在溝渠206中形成空隙爲限。 請參照第2D圖，去除部分的多晶矽層210，去除的方 法比如爲乾蝕刻或濕蝕刻，藉以去除位於罩幕層204上方 的多晶矽層210，在蝕刻進行時，溝渠206上方的多晶矽 210也會一倂被移除，利用此蝕刻步驟在溝渠206中形成 一個多晶矽插塞210a，此多晶矽插塞210a與基底200直 接相接。 經濟部智慧財產局員工消費合作社印製 請參照第2E圖，在上述的結構上全面覆蓋一層薄的阻 擋層212，其材質較佳爲氮化矽，厚度約爲30- 100A，接 著在阻擋層212上沈積一層介電層214，介電層214之厚 度必須可以塡滿整個溝渠206，其材質較佳爲二氧化矽， 形成方法比如爲高密度電漿化學氣相沈積法（HDPCVD)。 其中，阻擋層212係用以保護位於其下方的多晶矽插 塞210a，避免在後續的製程中氧氣擴散進入多晶矽而產生 7 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） A7 558793 6 0 7 5 twf . doc / Ο Ο 6 五、發明說明（$ ) 氧化反應，多晶矽氧化形成氧化矽將會使體積膨脹，體積 變化會造成元件效能受到影響，因此阻擋層212的存在是 必要的，但是氮化矽之阻擋層212與矽以及二氧化矽也會 有應力的差異，故阻擋層212不能太厚。 接著，請參照第2F圖，先去除位於罩幕層204上方與 溝渠206以外的介電層214與阻檔層212，僅留下塡充在 溝渠206中的介電層214a，去除的方法較佳爲化學機械硏 磨法。 之後，再將罩幕層204剝除，由於罩幕層2〇4之材質 爲氮化矽，可行的剝除方法比如以熱磷酸進行濕蝕刻，且 由於阻擋層212之材質與罩幕層204相同，因此暴露於介 電層214a側壁的阻擋層212也會一倂被去除。 本發明提供之淺溝渠隔離的製造方法，在溝渠底部塡 充有多晶矽插塞，因此可以降低介電材料塡充入溝渠的高 寬比，所以介電材料塡入溝渠的困難度會因此降低。但是 由於溝渠側壁形成有襯氧化層，隔離效果可由襯氧化層來 提供，因此無須擔心隔離效果因爲塡充於溝渠中的介電層 變淺而降低。 此外，本發明在形成襯氧化層於溝渠中以後，必須進 行一道蝕刻步驟去除溝渠底部的襯氧化層，其目的在於使 塡充在溝渠中的多晶矽插塞與基底直接相接，當進行電性 操作基底接地時’多晶矽插塞會與基底處於相同的電壓狀 態，不會有浮置的現象產生。 再者，本發明利用阻擋層形成於多晶矽插塞與介電層 8 丨本紙張尺度適用中國準（CNS)A4規格（21G x 297公髮） --- -----------^裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 558793 6075twf.doc/006 五、發明說明（7 ) 之間，用保護位於阻擋層下方的多晶矽插塞，避免在後 續的製程中氧氣擴散進入多晶矽而產生氧化反應，多晶砂 氧化形成氧化矽將會使體積膨脹，體積變化會造成元件效 能受到影響，因此阻擋層的存在可以避免多晶矽氧化而使 元件承受過大的應力。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）The invention provides a method for manufacturing a shallow trench isolation, which includes providing a semiconductor substrate on which a pad oxide layer and a mask layer are sequentially formed, and the mask layer, the pad oxide layer and A substrate to form a trench in the substrate. An oxidation step is performed to oxidize the substrate exposed in the trench to form a liner oxide layer, and then remove the liner oxide layer at the bottom of the trench to expose the substrate at the bottom of the trench. Fully deposit a layer of polycrystalline silicon on the mask layer and pour it into the trench, and then use an isotropic etching step to remove the polycrystalline silicon layer above the mask layer and in the trench. The remaining polycrystals form a polycrystal in the trench. Sand plug. Fully deposit a thin and conformal barrier rib, then deposit a layer of insulating material on the barrier layer, and use chemical mechanical honing to remove the insulating material above the mask layer and outside the trench and the barrier M ′, and then strip the mask layer Complete the production of shallow trench isolation. The manufacturing method of shallow trench isolation provided by the present invention can reduce the aspect ratio of the dielectric material filled into the trench, so the difficulty of the dielectric material penetration can be reduced, but the isolation effect can be formed by the lining oxide layer formed on the sidewall of the trench. To provide, so there is no need to worry about the isolation effect being reduced due to shallow trenches. The polycrystalline silicon filled in the trench is likely to be oxidized in the subsequent processes. The oxidized sand dioxide has a large volume. The change in volume will cause a great stress on the fabricated components, and the performance of the components will be affected by this. The invention provides a barrier layer to cover the polycrystalline silicon, and then insert a dielectric material, so as to avoid further oxidation of the polycrystalline silicon. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, in conjunction with the accompanying drawings, and described in detail as follows. 5 This paper size applies to the Chinese National Standard (CNS ) A4 size (210 X 297 mm) (Please read the precautions on the back before filling out this page) ▼ Packing -------- Order --------- Smart Property Bureau of Ministry of Economic Affairs Printed by the employee consumer cooperative 558793 6075twf.doc / 006 A7 B7 Printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (+) Brief description of the drawings: Figures 1A to 1C are traditional A schematic cross-sectional view of the manufacturing process of the trench isolation process; and FIGS. 2A to 2F are cross-sectional views of the manufacturing process of a shallow trench isolation according to a preferred embodiment of the present invention. Description of icons: 100, 200 substrate 102, 202 pad oxide layer 104, 204 nitrided sand layer 106, 206 trench 108, 208, 208A liner oxide layer 110 sand oxide layer 210 polycrystalline silicon layer 210a polycrystalline silicon plug 212, 212a barrier layer 214, Figures 2A to 2F of a 214a dielectric layer embodiment show cross-sectional views of a manufacturing process for shallow trench isolation according to a preferred embodiment of the present invention. Referring to FIG. 2A, a semiconductor substrate 200 is provided, and a pad oxide layer 202 and a mask layer 204 are sequentially covered on the substrate 200, and the material of the mask layer 204 is preferably silicon nitride. Perform lithography and etching processes to remove part of the mask layer 204, pad oxide layer 202, and substrate 200 to form a trench 206 in the substrate 200; after the trench 206 is formed, a wet etching is performed 6 ------- ---- Loading -------- Order --------- line (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 specifications ( (210 X 297 mm) 558793 6075twf.doc / 006 A7 B7 5. Description of the invention (Ai) This step will remove the pad oxide layer 202 partially exposed in the trench 206, so the pad oxide layer 202 will show a little Sunken. (Please read the precautions on the back before filling this page.) Please refer to Figure 2B to oxidize the substrate 200 exposed in the trench 206 to form a liner oxide layer 208 on the surface of the substrate 200. Next, as shown in FIG. 2C, the liner oxide layer 208 at the bottom of the trench 206 is removed, thereby exposing the substrate 200 at the bottom of the trench 206. At this time, a liner oxide layer 208 still exists on the sidewall of the trench 206, and the liner oxide layer 208 is removed. The step is achieved by anisotropic etching, such as reactive ion etching (RIE). After the substrate 200 at the bottom of the trench 206 is exposed, a polycrystalline silicon layer 210 is deposited on the mask layer 204 and the trench 206. The thickness of the polycrystalline silicon layer 210 is limited so as not to form a void in the trench 206. Referring to FIG. 2D, a part of the polycrystalline silicon layer 210 is removed. The removal method is, for example, dry etching or wet etching, so as to remove the polycrystalline silicon layer 210 above the mask layer 204. During the etching, the polycrystalline silicon 210 above the trench 206 will also be removed. Once removed, a polycrystalline silicon plug 210a is formed in the trench 206 by this etching step, and the polycrystalline silicon plug 210a is directly connected to the substrate 200. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 2E. The above structure is fully covered with a thin barrier layer 212. Its material is preferably silicon nitride, with a thickness of about 30-100A, and then on the barrier layer. A dielectric layer 214 is deposited on 212. The thickness of the dielectric layer 214 must be able to fill the entire trench 206. The material is preferably silicon dioxide. The formation method is, for example, high-density plasma chemical vapor deposition (HDPCVD). Among them, the barrier layer 212 is used to protect the polycrystalline silicon plug 210a located below it, to prevent oxygen from diffusing into the polycrystalline silicon in the subsequent process to generate 7 paper standards applicable to the Chinese National Standard (CNS) A4 specification (21〇 × 297 mm). ) A7 558793 6 0 7 5 twf. Doc / Ο Ο 6 V. Description of the invention ($) Oxidation reaction, the oxidation of polycrystalline silicon to form silicon oxide will expand the volume, and the change in volume will affect the efficiency of the device, so the existence of the barrier layer 212 It is necessary, but the barrier layer 212 of silicon nitride is different from silicon and silicon dioxide in stress, so the barrier layer 212 cannot be too thick. Next, referring to FIG. 2F, the dielectric layer 214 and the barrier layer 212 located above the mask layer 204 and outside the trench 206 are removed first, leaving only the dielectric layer 214a filled in the trench 206. Chemical mechanical honing is preferred. After that, the mask layer 204 is peeled off. Since the material of the mask layer 204 is silicon nitride, a feasible stripping method such as wet etching with hot phosphoric acid, and because of the material of the barrier layer 212 and the mask layer 204 Similarly, the barrier layer 212 exposed to the sidewall of the dielectric layer 214a is also removed at once. In the manufacturing method of shallow trench isolation provided by the present invention, polycrystalline silicon plugs are filled at the bottom of the trench, so the aspect ratio of the dielectric material and the trench can be reduced, so the difficulty of the dielectric material entering the trench will be reduced. However, since a trench oxide layer is formed on the sidewall of the trench, the isolation effect can be provided by the liner oxide layer, so there is no need to worry about the isolation effect being reduced because the dielectric layer filled in the trench becomes shallower. In addition, after the liner oxide layer is formed in the trench, the present invention must perform an etching step to remove the liner oxide layer at the bottom of the trench. The purpose is to directly connect the polycrystalline silicon plug filled in the trench with the substrate. When the substrate is grounded, the 'polycrystalline silicon plug' will be at the same voltage state as the substrate, and there will be no floating phenomenon. In addition, the present invention utilizes a barrier layer formed on the polycrystalline silicon plug and the dielectric layer 8 丨 This paper size is applicable to China Standard (CNS) A4 specification (21G x 297 public hair) --- ---------- -^ Pack -------- Order --------- line (please read the precautions on the back before filling this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 558793 6075twf.doc / 006 V. Description of the invention (7), the polycrystalline silicon plug under the barrier layer is protected to prevent the oxygen from diffusing into the polycrystalline silicon in the subsequent process to produce an oxidation reaction. The oxidation of polycrystalline sand to form silicon oxide will expand the volume. The volume change will affect the performance of the device, so the existence of the barrier layer can prevent the polycrystalline silicon from oxidizing and causing the device to undergo excessive stress. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 9 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)