經濟部中央標準局員工消費合作社印裝 530373 A7 8593pif.doc/008 B7 五、發明説明（ί ) 本發明是有關於一種具有淺溝渠隔離結構(STI)之半導體元 件，以及其製造方法。 半導體元件速度及隻體度的增加已有了相當大的改進，隨 著這些改進，高密度圖案及尺寸的減小逐漸顯得重要，而寬隔 離區域亦成爲半導體元件中，高密度圖案及尺寸減小的要件。 矽的區域氧化層(LOCOS)主要應用在傳統半導體元件之隔 離層，然而，利用區域氧化法引起在隔離層邊緣形成的鳥嘴結 構使得主動區域減小，並產生洩漏電流。 近來，發展出具有窄寬度及極佳隔離特性的淺溝渠隔離層， 具有淺溝渠結構之半導體元件將參考第1圖敘述如下。 參考第1圖，在一半導體基底10上形成一阻擋層圖案(未 顯示），以曝露出一隔離區域。該半導體基底10上可以定義成 一胞區域，一核心區域，及一周邊區域。此外，該阻擋圖案可 以是一氧化層及氮化矽的堆疊。利用阻擋圖案作罩幕，將曝露 出的半導體基底10被蝕刻一預定深度，以在其中形成溝渠I 及t2。溝渠形成於胞區域中，而溝渠t2則在核心或周邊區域 中定義出一 P型場效電晶體區域。任何一種利用電漿之乾式蝕 刻都可以在此實施以形成溝渠Μ及t2。 然而，形成溝渠及t2之乾式蝕刻可能造成溝渠I及t2表 面矽晶格的缺陷及損壞，習知利用熱氧化法在溝渠q及t2內表 面形成一側壁氧化層12於，以減低矽晶格缺陷及損壞。還有， 側壁氧化層12的形成使得溝渠^及12的尖銳角落圓滑。 之後，形成一氮化矽底襯層14於側壁氧化層12的表面上， 眾所皆知的，此一氮化矽底襯層14防止因由矽形成之半導體基 4 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) :訂_ 經濟部中央標準局員工消費合作社印裝 530373 8593pif.doc/008 五、發明説明（勹） 底10以及塡充溝渠ti及t2之矽氧化層之間熱脹膨係數不同所 產生的應力。 一介電;材料，例如是高密度電漿介電層在半導體基底10上 沈積形成’以完成塡充溝渠tl及t2。接著，對高密度電漿介電 層及阻檔圖案實施化學機械硏磨法(CMP)，以曝露出半導體基 底10之表面，以完成淺溝渠隔離層16的形成。 然而’具有傳統淺溝渠結構之半導體元件有以下問題。參 考第2A及2B圖，由於具高積極度之半導體金氧半電晶體的熱 電子通常具有高能量，其會跳躍至薄閘極氧化層22，或輕易地 穿越側壁氧化層12而進入淺溝渠隔離層16。此穿越至淺溝渠 隔離層16之熱電子通常具有負電荷，亦即電子30，很容易會 被捕捉於淺溝渠隔離層16之氮化層14中以及氮化矽底襯層14 及側壁氧化層12之界面上。此時，因爲如以上所述，側壁氧化 層12相當薄，所以電子30在附近被捕捉。如此，在淺溝渠隔 離層16邊緣之電子30濃度高，而金氧半電晶體在其上形成之 半導體基底10之正電荷，亦即電洞32，則被感應至淺溝渠隔 離層16的周圍。此時，由於電子30在氮化矽底襯層14附近， 以及氮化矽底襯層14及側壁氧化層12之界面上被捕捉，半導 體基底10之電洞則濃密地聚集在一起。 如第2A圖所示，由於在N-通道場效電晶體中主要載子爲 電子30，在N-型界面區26a及26b形成一路徑，其中雖然在 淺溝渠隔離層16周圍的電洞32濃密，電子30仍爲主要載子。 已知於P型場效電晶體之主要載子爲電洞，如第2B圖所 示，在淺溝渠隔離層16周圍濃密的電洞32形成一電流路徑， (請先閲讀背面之注意事項再填寫本頁) •裝· :訂. 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） 經濟部中央榡準局貝工消費合作社印袋 530373 A7 8593pif.doc/008 B7 五、發明説明（>1 ) 而與被淺溝渠隔離層16隔離的P型界面區域28a及28b連接。 於是，雖然P型界面區域28a及28b被淺溝渠隔離層16所隔 離，此一電流路徑I使得相鄰的P型場效電晶體之間產生洩漏 流，例如是老化之後異常增加的預備電流，而使P型場效電晶 體之特性惡化。在此，標號24係一金氧半電晶體之閘電極。 再者，如果P型場效電晶體(未顯示)是在淺溝渠隔離層16 及一主動區之間的界面上形成，P型場效電晶體之通道區與藉 薄側壁氧化層12有電子陷入的氮化矽底襯層14相接。於是， 陷入氮化矽底襯層14的電子很容易將界面中P型場效電晶體之 電洞感應。因此，開啓P型場效電晶體所感應的電洞很難被移 除而在P型場效電晶體關閉時仍保留原處。所以，界面上P型 場效電晶體的通道長度逐漸變短’而減低了起始電壓及崩潰電 壓。結果，P型場電晶體的特性非所希望地被改變。 爲解決以上之問題，本發明之一目的在於提供一種具有淺 溝渠隔離結構的半導體元件，其將淺溝渠隔離層周圍’半導體 元件的洩漏電流減小。 本發明之目的亦提供一^種製造具有淺溝渠隔離結構之半導 體元件的方法。 基於本發明之第一實施例，一具有一淺溝渠隔離結構之半 導體基底包括一半導體基底，其具有複數個溝渠，以提供隔離 在爲形成記憶元件之一胞區域，以及在非胞區域之區域，例如 是核心或周邊區域，其中形成了 P型場效電晶體或其他元件。 一第一側壁氧化層在溝渠的內表面上形成，一第二側 壁氧化層僅在非胞區之一*個或多個溝渠的內表面上見/成，弟 6 本紙張尺度適用中國國家標隼（CNS ) Μ規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) ·1_ 裝- 經濟部中央標準局員工消費合作社印製 530373 8593pif.doc/008 A7 ------- B7 五、發明説明（V) -舒解底襯則域細職_多讎渠_—{p腫氧化 層上’ 一第一舒解底襯層形成在第一舒解底襯層及第二側壁氧 化層上，溝渠再被一介電材料塡滿。 基於本發明之第二實施例，具有淺溝渠隔離結構之半導體 元件包括一半導體基底，其具有複數個溝渠，以隔離形成記憶 兀件之胞區域’及形成P型場效電晶體及其他電路元件之核心 或周邊區域。溝渠內表面上形成一第一側壁氧化層，核心或周 邊區域中’用以隔離p型場效電晶體之一個或多個溝渠的第一 側壁氧化層上則又形成一第二側壁氧化層，一第一舒解底襯層 在包區域中記憶元件之間以及核心或周邊區域中其他電路之間 一個或多個溝渠中的第一側壁氧化層上形成，一第二舒解底襯 層在第一舒解底襯層以及第二側壁氧化層上形成，然後複數個 溝渠以介電材料塡充。第一側壁氧化層具有大約20至50埃的 厚度，第二側壁氧化層具有大約50至100埃的厚度，第一及 第二舒解底襯層由氮化矽或氮氧化矽所形成，介電材料係一高 密度電漿層或TEOS氧化層。 基於本發明之另一特徵，具有淺溝渠隔離結構之半導體元 件的製方法如以下所述。提供一半導體基底，其包括形成有記 憶元件之胞區域以及形成有P型場效電晶體或其他電路元件之 非胞區域，例如是核心或周邊區域。在半導體基底上形成一阻 擋圖案，並曝露出預定義胞區域，核心區域或周邊區域以及在 各區域中用以隔離元件部分的半導體基底。利用阻擋圖案爲罩 幕，對曝露半導體基底的預隔離區蝕刻預定厚度，以形成複數 個溝渠。在溝渠的內表面上形成一第一側壁氧化層，形成一第 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） Λ3- (請先閲讀背面之注意事項再填寫本頁) r f 經濟部中央標準局員工消費合作社印繁 530373 A7 8593pif.doc/008 B7 五、發明説明（< ) 一舒解底襯層於第一側壁氧化層上方，藉著移除部分的第一舒 解底襯層，使得第一側壁氧化層的部分區域曝露出來，被移除 的部分包括隔離p型場效電晶體之溝渠，選擇性地形成一第二 側壁氧化層於曝露的第一側壁氧化層上，形成一第二舒解底襯 層於第一舒解底襯層及第二側壁氧化層上，然後，再形成一介 電材料以塡充溝渠。利用將介電層，舒解底襯以及阻擋圖案平 坦化以形成淺溝渠隔離層。 其中第一及第二側壁氧化層是利用熱氧化層形成的，第一 及第二舒解底襯層是用氮化矽或氮氧化矽形成，而第一舒解底 襯層是利用等向性蝕方法移除。 第一舒解底襯層被選擇移除的區域包括核心或周邊區域p 型場效電晶體之間的溝渠。 阻擋圖案的形成包括形成一墊氧化層於半導體基底上，形 成一氮化砂層在墊氧化層上，以及定義氮化砂層及墊氧化層以 曝露出預定區域。 基於本發明，提供核心或周邊區域中，隔離P型場效電晶 體之淺溝渠隔離層具有相對較厚的側壁氧化層，而在胞區域的 淺溝渠隔離層之厚度相對較薄。 因爲隔離核心或周邊區域P型場效電晶體之淺溝渠隔離層 的側壁氧化層相對較厚，陷入底襯層及側壁氧化層之間界面的 電子分佈廣泛，而受電子感應的電洞亦廣泛分佈在外表面上。 因此，電流路徑不會形成，而相鄰p型場效電晶體之間的洩漏 電流不會產生。還有，界面上p型場效電晶體的起始電壓和崩 潰電壓特性不會惡化。 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------_裝-- (請先閲讀背面之注意事項再填寫本頁) 今 經濟部中央標準局員工消費合作社印裝 530373 A7 8593pif.doc/008 B7 五、發明説明（（） 此外，由於形成於胞區域淺溝渠隔離層的舒解底襯層相對 較厚，可防止在胞區域產生之缺陷穿越至淺溝渠隔離層中，因 此，淺溝渠隔離層可提供較佳的介電特性。 圖式之簡單說明： 爲讓本發明之上述和其他目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： 第1圖係一剖面圖，繪示一種具有傳統淺溝渠隔離結構之 半導體元件； 第2A圖係一剖面圖，繪示出利用傳統淺溝渠隔離結構隔 離之N-型場效電晶體； 第2B圖係一剖面圖，利用傳統淺溝渠隔離結構隔離之P 型場效電晶體； 第3A至3E圖係剖面圖，繪示出本發明之第一實施例中， 製造具有淺溝渠隔離結構之一半導體元件； 第4A圖係剖面圖，繪示出本發明之第一實施例中，以淺 溝渠隔離結構隔離的P型場效電晶體的一部分： 第4B圖係剖面圖，繪示出本發明之第一實施例中，以淺 溝渠隔離結構隔離的N-型場效電晶體的一部分： 第5圖係剖面圖，繪示出本發明之第二實施例中，具有淺 溝渠隔離結構之一半導體元件；以及 第6圖係剖面圖，繪示出本發明之第三實施例中，具有淺 溝渠隔離結構之一半導體元件。 圖式之標記說明： 10 :半導體基底 9 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) £ :、ΤΓ 530373 A7 8593pif.doc/008 R7 經濟部中央標準局貝工消費合作社印裝 五、發明説明ο ) 12 :側壁氧化層 14 :氮化矽層 16 :淺溝渠隔離層 22 :閘極氧化層 24 :閘電極 26a/26b : N-型界面區 28a/28b : P型界面區 30 :電子 32 :電洞 100 :半導體基底 102 :墊氧化層 104 :氮化矽層 106a/106b :第一7第_*溝渠 108 :第一側壁氧化層 110 :舒解底襯層 112 :光阻圖案 114 :第二側壁氧化層 116 :舒解底襯層 120a/120b :第一/第二淺溝渠隔離層 200 :電子 202 :電洞 2〇4 : P型場效電晶體界面 208 : N-型場效電晶體界面 250 :抗反射層 (請先閲讀背面之注意事項再填寫本頁) 【裝· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印裝 530373 A7 8593pif.doc/008 B7 五、發明説明（2 ) 實施例 本發明之較佳實施例將參考附圖，於以下詳細敘述之，然 而，本發明之實施例可修改成各種其他形式，而本發明之範圍 並不受這些實施例所限制。以下實施例的提供是爲了更完全地 將本發明解釋給習知此技藝者。在圖式中，各層及各區域的厚 度誇張地繪示以求淸楚，在圖式中使用相同的標示標示相同元 件，此外，當描述一層在另外一層或基底上形成時，可代表該 層直接形成在另一層或基底上，亦可代表其他層可能在其間形 成。 第一實施例 首先，參考第3圖，一墊氧化層102及一氮化矽層1〇4堆 疊依序在一半導體基底100上形成，半導體基底100可以是摻 雜有選擇雜質的矽基底，其包括一欲形成記憶元件之胞區域， 以及欲形成P型場效電晶體或其他電路元件之核心或周邊區 域。A1代表胞區域，而A2代表非胞區域，例如是核心或周邊 區域。墊氧化層102的厚度大約是70至160埃，而氮化矽層104 厚度大約介於1300至1600埃。接著，氮化砍層104及墊氧化 層102被一傳統微影製程蝕刻，以曝露出半導體基底100之預 隔離區域，藉此形成一阻擋圖案。在此，預隔離區域是指用來 定義胞區域，核心區域或周邊區域，以及在各區域隔離元件的 區域。之後，利用阻擋圖案爲罩幕，半導體基底100被蝕刻約 0.1至1.5微米的深度，以形成第一溝渠l〇6a及第二溝渠106b。 第一及第二溝渠106a及106b係用以形成淺溝渠隔離結構的淺 溝渠，還有，第一二溝渠l〇6a提供胞區域A1中元件之隔離， --------裝------Tctr----- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印裝 530373 A7 8593pif.d〇c/〇〇8 B7 五、發明説明（q) 而第二溝渠l〇6b提供非胞區域A2中元件之間的隔離。還有， 第一溝渠106a是在元件密度較高在胞區域A1中形成的，因此 第一溝渠106a較在核心或周邊區域A2中形成之第二溝渠106b 爲窄。形成第一及第二溝渠106a及i〇6b的方法包括利用電漿 的乾式蝕刻製程，其導致第一及第二溝渠l〇6a及106b表面矽 晶格的缺陷及損害而洩漏電流。還有，還可能形成第一及第二 溝渠106a及106b的尖銳角落。 接著，如第3B圖所示，將第一及第二溝渠106a及106b 之內表面熱氧化，形成第一側壁氧化層108於第一及第二溝渠 l〇6a及l〇6b之內表面上，以補救第一及第二溝渠l〇6a及106b 中產生的矽晶格缺陷及損害，並移除尖銳角落。在此，第一側 壁氧化層108之厚度約爲20至240埃，考慮高積集度半導體 元件時最好是20至50埃。之後，一第一舒解底襯層110在形 成有第一側壁氧化層108之半導體元件100上形成。第一舒解 底襯層110舒解了因矽半導體基底100及用以塡充第一及第二 溝渠l〇6a及106b之氧化層之間熱膨脹係數不同而引起的應 力，並阻擋產生於主動區之缺陷穿越至第一及第二溝渠l〇6a及 106b中。舒解底襯層11〇可由氮化層或氮氧化層形成，而其厚 度約爲50至100埃。 參考第3C圖，利用傳統的微影製程形成一光阻圖II2覆 蓋胞區域A1，而曝露出核心或周邊區域A2。之後，移除在曝 露之核心或周邊區域A2的第一舒解底襯層110，以曝露核心 或周邊區域A2的第一側壁氧化層1〇8。在此，第一舒解底襯 層110可以用磷酸溶液作爲蝕刻劑’利用濕式蝕刻將其等向飩 本紙張尺度適用中國國家標準（CNS ) Α4規格（21〇χ297公楚） --------••裝-- (請先閲讀背面之注意事項再填寫本頁) 一訂 530373 A7 B7 8593pif.doc/008 五、發明説明（ι。） 亥[J。第一舒解底襯層no亦可以利用等向性乾式蝕刻予以蝕刻。 (請先閱讀背面之注意事項再填寫本頁) 之後，如第3D圖所示，用已知方法移除光阻112。接著， 熱氧化半導體基底100以在核心或周邊區域A2中的第一側壁 氧化層108上形成一第二側壁氧化層114。胞區域A1被氮化 矽或氮氧化矽層所形成之第一舒解底襯層110所覆蓋，因此， 雖然整個半導體基底100被氧化，氧化層只會在曝露的第一側 壁氧化層108上形成，而不會在第一舒解底襯層110表面上形 成。在此，第二側壁氧化層114的厚度約爲50至150埃。之 後，一厚約50至150埃的第二舒解底襯層116在半導體基底1〇〇 上形成，結果，在胞區域A1中，側壁氧化層108係一厚約50 至150埃之單層，而舒解底襯層110及116構成一厚約100-200 埃之雙層結構。在核心或周邊區域A2中，側壁氧化層108及 114係一厚約70至200埃之雙層結構，而舒解底襯層116係一 厚約5(M00埃之單層結構。在胞區域A1中，舒解底襯層較其 他區域相對爲厚，而在核心或周邊區域A2中，側壁氧化層較 胞區域相對爲厚。 經濟部中央標準局貝工消費合作社印装 接著，參考第3E圖，在半導體基底100上形成一厚約5000 至7000埃的介電層，以塡滿第一及第二溝渠106a及106b。 此時，具有優良層間塡充特性的高密度電漿層或TEOS層皆可 作爲介電層。接著，對介電層，第一及第二舒解底襯層110及 116，氮化矽層104，以及墊氧化層102實施一平坦化製程，例 如是化學機械硏磨法，直到曝露出半導體基底1〇〇的表面爲止。 結果，第一及第二溝渠106a及l〇6b塡滿了介電層而完成了淺 溝渠隔離層120a及120b的製造。在此，在實施化學機械硏磨 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 530373 8593pif.doc/008 A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（（1) 法之前，可以實施一溫度高約900°c之熱製程，以防止在第一 及第二淺溝渠隔離層120a及120b形成凹陷。結果，介電層因 爲高溫熱處理變得較爲緻密’而不易在化學機械硏磨製程中損 失。 基於本實施例，在核心或周邊區域A2之第二淺溝渠隔離層 之第二側壁氧化層較在胞區域中的相對爲厚，結果如第4A圖 所示，電子200隨機地陷入底襯層116中及底襯層116及側壁 氧化層108及114界面上’而被電子200感應之電洞202則在 淺溝渠隔離層102b隨機分佈’因此’不會形成一串接之電流 路徑。結果，在相接的p型場效電晶體界面中不會產生洩漏電 流。 還有，基於本發明’胞區域A1之第一淺溝渠隔離層l〇2a 相對較厚，結果如第4B圖所示，厚舒解底襯層110及116防 止在N-型場效電晶體中之缺陷滲透至淺溝渠隔離層120a中。 此時，在製程中可能產生p型場效電晶體之缺陷’然而，在元 件稀疏分佈的核心或周邊區域是形成此P型場效電晶體之區 域，所以，雖然P型場效電晶體中可能產生缺陷，其不會穿越至 淺溝渠隔離層12〇b。 第二實施例 除了淺溝渠隔層之位置之外，本實施例之製造方法基本上 與第一實施例相同。 亦即，如第5圖所示，其中具有相對較厚之側壁氧化層的 第二淺溝渠隔離層120b僅形成於核心或周邊區域之P型場效 電晶體之間。此外，在其上方具有相對較厚之舒解底襯層之第 (請先閲讀背面之注意事項再填寫本頁) -裝· *fr 本紙張尺度適用中國國家榡隼（CNS ) A4規格（210X297公釐〉 530373 石一 經濟部中央標準局員工消費合作社印裝 8593pif.doc/008 gy 發明説明（^) 一淺溝渠隔離層120a，則同時形成於胞區域及除了核心或周邊 區域之P型場效電晶體之外，用以隔離其他電路元件的區域。 在此，本發明之此一實施例主要部分可以與第一實施例相 同，然而，用以移除第一舒解底襯層之光阻層的圖案僅將定義 P -型場效電晶體之溝渠予以曝露。本實施例的其他製程則與 第一實施例相同。在此，標記A3代表除了胞區域及核心區域 或周邊區域中之P型場效電晶體以外，形成其他電路的一區域。 還有，標記A4則代表一隔離P型場效電晶體的區域。 本實施例具有與上述第一實施例相同之效果。 第三實施例 除了溝渠形成之前的程製之外，本實施例在溝渠形成之後 的製程與上述第一實施例相同。相同的標號將代表相同的元件。 參考第6圖，一墊氧化層102及一氮化矽層104依序在半 導體基底100上堆疊。之後，抗反射薄膜250沈積於氮化矽層 104上，以防止在後續微影製程中來自氮化矽104的反射。此 時，氮氧化矽可以用來形成抗反射層250，而其厚度約爲600 至700埃。 接著，抗反射層250，氮化矽層104及墊氧化層102被已 知之微影製程蝕刻以曝露出半導體基底1〇〇之預隔離區域。之 後，半導體基底100以氮化矽層104爲罩幕被蝕刻約0」至0.5 微米之深度，而形成第一及第二溝渠l〇6a及106b。在此，第 一溝渠l〇6a是形成於胞區域A1或除了核心或周邊區域P型場 效電晶體之間的隔離區域的區域A3，而第二溝渠106b則形成 於核心或周邊區域a2或在核心或周邊區域中隔離於P型場效電 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 五 ____ 經濟部中央標準局員工消費合作社印装 530373 A7 8593pif.doc/008 B7 發明説明（ο ) 晶體之間的區域A4。 在氮化砂層104上形成抗反射層250 ’可在定義溝渠時防 止微影製程中凹陷結構的形成。 如以上所述，基於本發明，提供核心或周邊區域之間電性 隔離或核心或周邊區域p型場效電晶體之隔離的淺溝渠隔離層 具有相對較厚的側壁氧化層，而在胞區域中形成之淺溝渠隔離 層具有相對較厚的舒解底襯層。 因爲隔離核心或周邊區域P型場效電晶體之淺溝渠隔離層 的側壁氧化層較厚，陷入舒解底襯層以及底襯層及側壁氧化層 之界面上的電子廣泛地分佈於外表面上。結果，不會形成電流 路徑，而在相鄰P型場效電晶之間的洩漏電流路徑不會產生， 因此，界面上P型場效電晶體之起始電流及崩潰電壓特性不會 惡化。 此外，由於在胞區域中形成之淺溝渠隔離層的舒解底襯層 較厚，可防止產生於胞區域之缺陷穿越至淺溝渠隔離層中，結 果，淺溝渠隔離層具有優良的介電特性。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內， 當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之 申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填寫本頁) •裝· :訂- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 530373 A7 8593pif.doc / 008 B7 V. Description of the Invention The invention relates to a semiconductor device with a shallow trench isolation structure (STI) and a method for manufacturing the same. The increase in the speed and volume of semiconductor elements has been considerably improved. With these improvements, the reduction of high-density patterns and sizes has gradually become important, and the wide isolation region has also become a semiconductor element. Small requirements. The LOCOS of silicon is mainly used in the isolation layer of traditional semiconductor devices. However, the bird's beak structure formed on the edge of the isolation layer using the region oxidation method reduces the active area and generates leakage current. Recently, a shallow trench isolation layer having a narrow width and excellent isolation characteristics has been developed. A semiconductor device having a shallow trench structure will be described with reference to FIG. 1 as follows. Referring to FIG. 1, a barrier layer pattern (not shown) is formed on a semiconductor substrate 10 to expose an isolation region. The semiconductor substrate 10 can be defined as a cell region, a core region, and a peripheral region. In addition, the blocking pattern may be a stack of an oxide layer and silicon nitride. Using the barrier pattern as a mask, the exposed semiconductor substrate 10 is etched to a predetermined depth to form trenches I and t2 therein. The trench is formed in the cell region, and the trench t2 defines a P-type field effect transistor region in the core or peripheral region. Any type of dry etching using plasma can be performed here to form trenches M and t2. However, the dry etching of the trenches and t2 may cause defects and damage to the silicon lattice on the surface of trenches I and t2. It is known to use thermal oxidation to form a sidewall oxide layer 12 on the inner surfaces of trenches q and t2 to reduce the silicon lattice Defects and damage. In addition, the formation of the sidewall oxide layer 12 makes the sharp corners of the trenches 12 and 12 smooth. After that, a silicon nitride underlayer 14 is formed on the surface of the side wall oxide layer 12. It is well known that this silicon nitride underlayer 14 prevents semiconductor substrates formed from silicon. CN (CNS) A4 specification (210X297 mm) (Please read the notes on the back before filling out this page): Order _ Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 530373 8593pif.doc / 008 5. Description of the invention (勹) The stress caused by the different thermal expansion coefficients between the bottom 10 and the silicon oxide layer of the ti-fill trenches ti and t2. A dielectric; material, such as a high-density plasma dielectric layer, is deposited on the semiconductor substrate 10 'to complete the trenches t1 and t2. Then, a chemical mechanical honing method (CMP) is performed on the high-density plasma dielectric layer and the barrier pattern to expose the surface of the semiconductor substrate 10 to complete the formation of the shallow trench isolation layer 16. However, a semiconductor device having a conventional shallow trench structure has the following problems. Referring to Figures 2A and 2B, since the hot electrons of highly active semiconductor metal-oxide semiconductors usually have high energy, they will jump to the thin gate oxide layer 22 or easily pass through the sidewall oxide layer 12 and enter the shallow trench. Isolation layer 16. The hot electrons passing through the shallow trench isolation layer 16 usually have a negative charge, that is, the electrons 30, are easily captured in the nitride layer 14 of the shallow trench isolation layer 16 and the silicon nitride underlayer 14 and the sidewall oxide layer. 12 interface. At this time, since the sidewall oxide layer 12 is relatively thin as described above, the electrons 30 are captured in the vicinity. In this way, the concentration of electrons 30 at the edge of the shallow trench isolation layer 16 is high, and the positive charge of the semiconductor substrate 10 formed on the gold-oxygen semi-transistor, ie, the hole 32, is induced around the shallow trench isolation layer 16. . At this time, since the electrons 30 are captured near the silicon nitride underlayer 14 and the interface between the silicon nitride underlayer 14 and the sidewall oxide layer 12, the holes of the semiconductor substrate 10 are densely gathered together. As shown in FIG. 2A, since the main carrier in the N-channel field effect transistor is electrons 30, a path is formed in the N-type interface regions 26a and 26b, although the hole 32 around the shallow trench isolation layer 16 Dense, electron 30 remains the main carrier. It is known that the main carrier of a P-type field effect transistor is a hole. As shown in FIG. 2B, a dense hole 32 forms a current path around the shallow trench isolation layer 16. (Please read the precautions on the back before (Fill in this page) • Packing ·: Ordering. This paper size is applicable to China National Standard (CNS) A4 (210X297 mm). Printed bags of Beige Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs 530373 A7 8593pif.doc / 008 B7 V. DESCRIPTION OF THE INVENTION (> 1) It is connected to the P-type interface regions 28a and 28b isolated by the shallow trench isolation layer 16. Therefore, although the P-type interface regions 28a and 28b are isolated by the shallow trench isolation layer 16, this current path I causes a leakage current between adjacent P-type field effect transistors, such as an abnormally increased preparatory current after aging. As a result, the characteristics of the P-type field effect transistor are deteriorated. Here, reference numeral 24 is a gate electrode of a metal-oxide semiconductor transistor. Furthermore, if a P-type field effect transistor (not shown) is formed on the interface between the shallow trench isolation layer 16 and an active region, the channel region of the P-type field effect transistor and the thin sidewall oxide layer 12 have electrons. The immersed silicon nitride underlayer 14 is in contact. Thus, the electrons trapped in the silicon nitride underlayer 14 can easily induce holes in the P-type field effect transistor in the interface. Therefore, the holes induced by turning on the P-type field-effect transistor are difficult to remove and remain in place when the P-type field-effect transistor is turned off. Therefore, the channel length of the P-type field effect transistor at the interface is gradually shortened ', which reduces the starting voltage and the breakdown voltage. As a result, the characteristics of the P-type field transistor are undesirably changed. In order to solve the above problems, an object of the present invention is to provide a semiconductor device having a shallow trench isolation structure, which reduces the leakage current of the semiconductor device around the shallow trench isolation layer. An object of the present invention is also to provide a method for manufacturing a semiconductor element having a shallow trench isolation structure. Based on the first embodiment of the present invention, a semiconductor substrate having a shallow trench isolation structure includes a semiconductor substrate having a plurality of trenches to provide isolation in a cell region forming a memory element and in a non-cell region. For example, it is a core or a peripheral region in which a P-type field effect transistor or other element is formed. A first sidewall oxide layer is formed on the inner surface of the trench, and a second sidewall oxide layer is only seen / formed on the inner surface of one or more trenches in the non-cellular region. Brother 6隼 （CNS） M specifications (210X297 mm) (Please read the notes on the back before filling this page) · 1_ Pack-Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 530373 8593pif.doc / 008 A7 ----- -B7 V. Description of the invention (V)-Relief underlayment rules _ 多 雠 Channel __ {p swollen oxide layer '-a first relief underlayment is formed on the first relief underlayment and On the second sidewall oxide layer, the trench is filled with a dielectric material. Based on the second embodiment of the present invention, a semiconductor device having a shallow trench isolation structure includes a semiconductor substrate having a plurality of trenches to isolate the cell region forming a memory element and to form a P-type field effect transistor and other circuit elements. The core or surrounding area. A first sidewall oxide layer is formed on the inner surface of the trench, and a second sidewall oxide layer is formed on the first sidewall oxide layer of one or more trenches used to isolate the p-type field effect transistor in the core or peripheral area. A first relief substrate is formed on the first sidewall oxide layer in one or more trenches between the memory elements in the package region and between other circuits in the core or peripheral region. A second relief substrate is formed on The first relief substrate layer and the second sidewall oxide layer are formed, and then a plurality of trenches are filled with a dielectric material. The first sidewall oxide layer has a thickness of about 20 to 50 Angstroms, the second sidewall oxide layer has a thickness of about 50 to 100 Angstroms, and the first and second relief substrates are formed of silicon nitride or silicon oxynitride. The electrical material is a high-density plasma layer or a TEOS oxide layer. Based on another feature of the present invention, a method for manufacturing a semiconductor device having a shallow trench isolation structure is as follows. A semiconductor substrate is provided, which includes a cell region where a memory element is formed and a non-cell region where a P-type field effect transistor or other circuit element is formed, such as a core or peripheral region. A barrier pattern is formed on the semiconductor substrate, and a predefined cell region, a core region or a peripheral region, and a semiconductor substrate for isolating a component portion in each region are exposed. The barrier pattern is used as a mask to etch a predetermined thickness of the pre-isolated region exposing the semiconductor substrate to form a plurality of trenches. A first side wall oxide layer is formed on the inner surface of the trench to form a seventh paper size applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) Λ3- (Please read the precautions on the back before filling this page) rf Staff Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs, India 530373 A7 8593pif.doc / 008 B7 V. Description of the invention (<) A relief substrate is above the oxide layer on the first side wall. The bottom lining layer is disassembled, so that a part of the first sidewall oxide layer is exposed. The removed part includes a trench for isolating the p-type field effect transistor, and a second sidewall oxide layer is selectively formed to oxidize the exposed first sidewall. On the layer, a second relief substrate is formed on the first relief substrate and the second sidewall oxide layer, and then a dielectric material is formed to fill the trench. The dielectric layer, the relief substrate, and the barrier pattern are flattened to form a shallow trench isolation layer. The first and second sidewall oxide layers are formed using a thermal oxide layer. The first and second relief substrates are formed using silicon nitride or silicon oxynitride, and the first relief substrates are formed using an isotropic layer. Erosive removal. The area where the first relief substrate is selectively removed includes trenches between p-type field effect transistors in the core or peripheral areas. The formation of the barrier pattern includes forming a pad oxide layer on the semiconductor substrate, forming a nitrided sand layer on the pad oxide layer, and defining the nitrided sand layer and the pad oxide layer to expose a predetermined area. Based on the present invention, in the core or peripheral region, the shallow trench isolation layer for isolating the P-type field effect transistor has a relatively thick sidewall oxide layer, and the thickness of the shallow trench isolation layer in the cell region is relatively thin. Because the sidewall oxide layer of the shallow trench isolation layer of the P-type field effect transistor that isolates the core or the surrounding area is relatively thick, the electrons trapped at the interface between the underlayer and the sidewall oxide layer are widely distributed, and the electron-induced holes are also widely distributed. Distributed on the outer surface. Therefore, a current path is not formed, and a leakage current between adjacent p-type field effect transistors is not generated. In addition, the initial voltage and collapse voltage characteristics of the p-type field effect transistor at the interface will not deteriorate. 8 This paper size applies to China National Standard (CNS) A4 (210X297 mm) ---------_ installed-(Please read the precautions on the back before filling this page) The Central Bureau of Standards, Ministry of Economic Affairs Printed by the employee consumer cooperative 530373 A7 8593pif.doc / 008 B7 V. Description of the invention (() In addition, since the relief bottom lining formed in the shallow trench isolation layer in the cell area is relatively thick, it can prevent defects generated in the cell area from passing through To the shallow trench isolation layer, therefore, the shallow trench isolation layer can provide better dielectric characteristics. Brief description of the drawing: In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following special features The preferred embodiment is described in detail with the accompanying drawings as follows: FIG. 1 is a cross-sectional view showing a semiconductor element having a conventional shallow trench isolation structure; FIG. 2A is a cross-sectional view showing the N-type field-effect transistor isolated using traditional shallow trench isolation structure; Figure 2B is a cross-sectional view, P-type field-effect transistor isolated using traditional shallow trench isolation structure; Figures 3A to 3E are cross-sectional views, showing The first In the embodiment, a semiconductor device having a shallow trench isolation structure is manufactured; FIG. 4A is a cross-sectional view illustrating a part of a P-type field effect transistor isolated by the shallow trench isolation structure in the first embodiment of the present invention: FIG. 4B is a cross-sectional view showing a part of an N-type field effect transistor isolated by a shallow trench isolation structure in the first embodiment of the present invention: FIG. 5 is a cross-sectional view showing the first part of the present invention In the second embodiment, a semiconductor element having a shallow trench isolation structure; and FIG. 6 is a sectional view showing a semiconductor element having a shallow trench isolation structure in a third embodiment of the present invention. : 10: Semiconductor substrate 9 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) £ :, ΤΓ 530373 A7 8593pif.doc / 008 R7 Economy Printed by the Central Standards Bureau, Shellfish Consumer Cooperative, V. Description of the invention ο) 12: sidewall oxide layer 14: silicon nitride layer 16: shallow trench isolation layer 22: gate oxide layer 24: gate electrode 26a / 26b: N-type Interface area 28a / 28 b: P-type interface region 30: electrons 32: holes 100: semiconductor substrate 102: pad oxide layer 104: silicon nitride layer 106a / 106b: first 7th _ * trench 108: first sidewall oxide layer 110: relaxation Backing layer 112: Photoresist pattern 114: Second sidewall oxide layer 116: Relaxation backing layer 120a / 120b: First / second shallow trench isolation layer 200: Electronics 202: Holes 204: P-type field effect Transistor interface 208: N-type field effect transistor interface 250: Anti-reflection layer (please read the precautions on the back before filling this page) [Packing · This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) ) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 530373 A7 8593pif.doc / 008 B7 V. Description of the Invention (2) Examples The preferred embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention The embodiments can be modified into various other forms, and the scope of the present invention is not limited by these embodiments. The following examples are provided to more fully explain the invention to those skilled in the art. In the drawings, the thickness of each layer and each area is exaggerated for illustration. The same symbols are used in the drawings to identify the same elements. In addition, when describing a layer formed on another layer or on the substrate, it can represent the layer. Formed directly on another layer or substrate can also mean that other layers may be formed in between. First Embodiment First, referring to FIG. 3, a pad oxide layer 102 and a silicon nitride layer 104 are sequentially stacked on a semiconductor substrate 100. The semiconductor substrate 100 may be a silicon substrate doped with selective impurities. It includes a cell region where a memory element is to be formed, and a core or peripheral region where a P-type field effect transistor or other circuit element is to be formed. A1 represents the cellular region and A2 represents the non-cellular region, such as the core or peripheral region. The thickness of the pad oxide layer 102 is approximately 70 to 160 angstroms, and the thickness of the silicon nitride layer 104 is approximately 1300 to 1600 angstroms. Next, the nitride cutting layer 104 and the pad oxide layer 102 are etched by a conventional lithography process to expose the pre-isolated region of the semiconductor substrate 100, thereby forming a blocking pattern. Here, the pre-isolated region refers to a region used to define a cell region, a core region or a peripheral region, and a region for isolating elements in each region. After that, using the blocking pattern as a mask, the semiconductor substrate 100 is etched to a depth of about 0.1 to 1.5 micrometers to form a first trench 106a and a second trench 106b. The first and second trenches 106a and 106b are shallow trenches for forming a shallow trench isolation structure. In addition, the first and second trenches 106a provide isolation of components in the cell area A1. ----- Tctr ----- (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Device 530373 A7 8593pif.doc / 〇〇8 B7 V. Description of the invention (q) The second trench 106b provides isolation between components in the non-cellular area A2. Also, the first trench 106a is formed in the cell region A1 with a high element density, so the first trench 106a is narrower than the second trench 106b formed in the core or peripheral region A2. The method of forming the first and second trenches 106a and 106b includes a dry etching process using a plasma, which causes defects and damage to the silicon lattice on the surface of the first and second trenches 106a and 106b to leak current. Also, it is possible to form sharp corners of the first and second trenches 106a and 106b. Next, as shown in FIG. 3B, the inner surfaces of the first and second trenches 106a and 106b are thermally oxidized to form a first sidewall oxide layer 108 on the inner surfaces of the first and second trenches 106a and 106b. In order to remedy the defects and damages of the silicon lattice in the first and second trenches 106a and 106b, and remove the sharp corners. Here, the thickness of the first sidewall oxide layer 108 is about 20 to 240 angstroms, and it is preferably 20 to 50 angstroms when considering a semiconductor element having a high accumulation degree. After that, a first relief substrate layer 110 is formed on the semiconductor device 100 having the first sidewall oxide layer 108 formed thereon. The first relief underlayer 110 relieves stress caused by the difference in thermal expansion coefficients between the silicon semiconductor substrate 100 and the oxide layers used to fill the first and second trenches 106a and 106b, and prevents active Defects in the area cross into the first and second trenches 106a and 106b. The relief base layer 110 may be formed of a nitride layer or an oxynitride layer and has a thickness of about 50 to 100 angstroms. Referring to FIG. 3C, a conventional photolithography process is used to form a photoresist pattern II2 to cover the cell area A1, and the core or peripheral area A2 is exposed. Thereafter, the first relief base liner 110 in the exposed core or peripheral area A2 is removed to expose the first sidewall oxide layer 108 in the core or peripheral area A2. Here, the first relief substrate layer 110 can use a phosphoric acid solution as an etchant 'by isotropic wet etching. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇297297) --- ----- •• Installation-- (Please read the notes on the back before filling this page) Order 530373 A7 B7 8593pif.doc / 008 V. Description of the invention (ι.) Hai [J. The first relief base liner no can also be etched by isotropic dry etching. (Please read the precautions on the back before filling this page.) Then, as shown in Figure 3D, remove the photoresist 112 by a known method. Next, the semiconductor substrate 100 is thermally oxidized to form a second sidewall oxide layer 114 on the first sidewall oxide layer 108 in the core or peripheral region A2. The cell area A1 is covered by the first relief base layer 110 formed by a silicon nitride or silicon oxynitride layer. Therefore, although the entire semiconductor substrate 100 is oxidized, the oxide layer will only be on the exposed first sidewall oxide layer 108 Is formed without being formed on the surface of the first relief base liner 110. Here, the thickness of the second sidewall oxide layer 114 is about 50 to 150 Angstroms. Thereafter, a second relief base layer 116 having a thickness of about 50 to 150 Angstroms is formed on the semiconductor substrate 100. As a result, in the cell region A1, the sidewall oxide layer 108 is a single layer having a thickness of about 50 to 150 Angstroms. The relief substrates 110 and 116 form a double-layer structure with a thickness of about 100-200 Angstroms. In the core or peripheral region A2, the sidewall oxide layers 108 and 114 have a double-layered structure with a thickness of about 70 to 200 angstroms, and the relief underlayer 116 has a single-layered structure with a thickness of about 5 angstroms. In the cell region In A1, the relief substrate is relatively thicker than in other areas, and in the core or peripheral area A2, the sidewall oxide layer is relatively thicker than in the cell area. Printed by the Shelling Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. In the figure, a dielectric layer having a thickness of about 5000 to 7000 angstroms is formed on the semiconductor substrate 100 to fill the first and second trenches 106a and 106b. At this time, a high-density plasma layer or TEOS having excellent interlayer charge characteristics All layers can be used as a dielectric layer. Next, a planarization process is performed on the dielectric layer, the first and second relief substrate layers 110 and 116, the silicon nitride layer 104, and the pad oxide layer 102, such as chemical mechanical Honing until the surface of the semiconductor substrate 100 is exposed. As a result, the first and second trenches 106a and 106b are filled with a dielectric layer to complete the manufacture of the shallow trench isolation layers 120a and 120b. Here In the implementation of chemical mechanical honing, this paper is applicable to China Standard (CNS) A4 specification (210X297 mm) 530373 8593pif.doc / 008 A7 B7 Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention ((1) Before the method, a temperature higher than about 900 ° c can be implemented Thermal process to prevent the formation of depressions in the first and second shallow trench isolation layers 120a and 120b. As a result, the dielectric layer becomes denser due to high temperature heat treatment, and is not easily lost in the chemical mechanical honing process. Based on this implementation For example, the second sidewall oxide layer of the second shallow trench isolation layer in the core or peripheral area A2 is relatively thicker than that in the cell area. As shown in FIG. 4A, the electrons 200 are randomly trapped in the underlayer 116 and The holes 202 on the interface of the underlayer 116 and the side wall oxide layers 108 and 114, and the holes 202 induced by the electrons 200 are randomly distributed on the shallow trench isolation layer 102b, and therefore, a series of current paths will not be formed. As a result, No leakage current will be generated at the interface of the p-type field effect transistor. In addition, the first shallow trench isolation layer 102a based on the cell region A1 of the present invention is relatively thick. The result is shown in FIG. Underlayer 110 and 116 prevent Defects in the N-type field-effect transistor penetrate into the shallow trench isolation layer 120a. At this time, defects of the p-type field-effect transistor may be generated in the process. However, this is formed in the sparsely distributed core or peripheral area of the device. The area of the P-type field effect transistor, so although the P-type field effect transistor may have defects, it will not pass through the shallow trench isolation layer 12b. In the second embodiment, except for the location of the shallow trench isolation layer, The manufacturing method of this embodiment is basically the same as that of the first embodiment. That is, as shown in FIG. 5, the second shallow trench isolation layer 120b having a relatively thick sidewall oxide layer is formed only in the core or the peripheral area. Between P-type field effect transistors. In addition, there is a relatively thick relief substrate at the top (please read the precautions on the back before filling this page) -Packing * * This paper size is applicable to China National Standard (CNS) A4 (210X297 Mm> 530373 Shi Yiyi Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 8591pif.doc / 008 gy Description of the invention (^) A shallow trench isolation layer 120a is formed in both the cell area and the P-type field except the core or surrounding areas In addition to the effect transistor, it is used to isolate the area of other circuit elements. Here, the main part of this embodiment of the present invention may be the same as the first embodiment, however, it is used to remove the light of the first relief base liner. The pattern of the resist layer only exposes the trenches that define the P-type field effect transistor. The other processes of this embodiment are the same as those of the first embodiment. Here, the mark A3 represents the area except the cell area and the core area or the surrounding area. In addition to the P-type field-effect transistor, a region of other circuits is formed. In addition, the mark A4 represents a region that isolates the P-type field-effect transistor. This embodiment has the same effect as the first embodiment described above. Except for the process before the trench is formed, the process of this embodiment after the trench is formed is the same as the first embodiment described above. The same reference numerals represent the same components. Referring to FIG. 6, a pad oxide layer 102 and a The silicon nitride layer 104 is sequentially stacked on the semiconductor substrate 100. Then, an anti-reflection film 250 is deposited on the silicon nitride layer 104 to prevent reflection from the silicon nitride 104 in the subsequent lithography process. At this time, the nitrogen oxide is oxidized. Silicon can be used to form the anti-reflection layer 250 with a thickness of about 600 to 700 angstroms. Next, the anti-reflection layer 250, the silicon nitride layer 104, and the pad oxide layer 102 are etched by a known lithography process to expose the semiconductor substrate 1 〇〇 pre-isolated region. After that, the semiconductor substrate 100 is etched to a depth of about 0 ″ to 0.5 micrometers with the silicon nitride layer 104 as a mask to form first and second trenches 106a and 106b. Here, the first A trench 106a is formed in the cell area A1 or the area A3 except for the isolation region between the P-type field effect transistor in the core or the peripheral area, and the second trench 106b is formed in the core or the peripheral area a2 or in the core or the periphery. Area is isolated from P type Xiaodian (please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 5 ____ Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 530373 A7 8593pif.doc / 008 B7 Description of the invention (ο) The area A4 between the crystals. The formation of an anti-reflection layer 250 'on the nitrided sand layer 104 can prevent the formation of a recessed structure in the lithography process when defining a trench. As described above, based on the present invention A shallow trench isolation layer that provides electrical isolation between cores or peripheral regions or isolation of a p-type field effect transistor in the core or peripheral regions has a relatively thick sidewall oxide layer, while a shallow trench isolation layer formed in a cell region has Relatively thick release layer. Because the sidewall oxide layer of the shallow trench isolation layer of the P-type field effect transistor that isolates the core or surrounding area is thick, the electrons trapped at the interface of the relief substrate and the interface between the substrate layer and the sidewall oxide are widely distributed on the outer surface. . As a result, a current path is not formed, and a leakage current path between adjacent P-type field effect transistors is not generated. Therefore, the initial current and breakdown voltage characteristics of the P-type field effect transistor at the interface are not deteriorated. In addition, the shallow trench isolation layer formed in the cell region has a thicker relief base liner, which can prevent defects generated in the cell region from penetrating into the shallow trench isolation layer. As a result, the shallow trench isolation layer has excellent dielectric properties. . Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) • Packing ·: Order-This paper size is applicable to China National Standard (CNS) A4 (210X297 mm)