A7 B7 3450twf.doc/006 五、發明説明（/ ) 本發明是有關於一種積體電路的製造方法，且特別是 有關於一種淺溝渠隔離（Shallow Trench Isolation ; STI)區的製造方法。 元件隔離區係用以防止載子（Carrier)通過基底而 在相鄰的元件間移動之用。典型的元件隔離區係形成於稠 密的半導體電路，比如是動態隨機存取記憶體（DRAM)中 相鄰的場效電晶體（Field Effect Transistor ; FET)之 間’藉以減少由場效電晶體產生的漏電流（Current Leakage)現象。典型形成元件隔離區的方法係採用局部 區域氧化技術（LOCOS )。由於局部區域氧化技術的日趨 成熟，因此可藉此技術，以較低的成本獲得信賴度高且有 效之元件隔離結構。然而，採用局部區域氧化的方式具有 應力產生的問題與場隔離結構周圍鳥嘴區（Bird’s Beak) 的形成等缺點。其中，特別是鳥嘴區的形成，使得在小型 的元件上，以LOCOS方式所形成之場隔離結構並不能做有 效地隔離，所以在高密度（High Density)元件中，必須 以較易於調整大小的淺溝渠隔離方式所形成之元件隔離 結構來取代。 淺溝渠隔離法是一種利用非等向性蝕刻方法在半導 體基底中形成溝渠，然後在溝渠中塡入氧化物，以形成元 件之場隔離區的技術。由'於淺溝渠隔離法所形成之場隔離 區具有可調整大小（Scaleable)的優點，並且可避免傳 統區域氧化法隔離技術中鳥嘴侵蝕（Bi r(Ts Beak Encroachment)的缺點，因此’對於次微米（Sub-Micron) 3 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） (讀先閱讀背面之注意事項再填耗本頁) -裝. 訂 A7 B7 3450twf.doc/006 五、發明説明（l) 的互補式金氧半導體（CMOS)製程而言，是一種較爲理想 與的隔離技術。 第1A圖至第1F圖是習知一種淺溝渠隔離區製造流程 之剖面圖。 請參照第1A圖，首先，以熱氧化（Thermal Oxidat ion) 法在砂基底100上形成一層墊氧化層（Pad Oxide) 102， 此墊氧化層102係用以在製程中保護矽基底100的表面。 接著，在墊氧化層102上，以低壓化學氣相沉積法（Low Pressure Chemically Vapor Deposition; LPCVD)形成 一層氮化砂罩幕層104。 然後，請參照第1B圖，以習知的方法在氮化矽罩幕層 104表面上形成一層光阻層（圖中未顯示），並依序飩刻 氮化矽罩幕層104、墊氧化層102與矽基底100，以在矽 基底100中形成溝渠106。其後，再將光阻層去除。 請參照第1C圖，以高溫熱氧化法，在溝渠106所暴露 出的砂基底100表面，形成襯氧化（Liner Oxide )層108， 其中襯氧化層108會延伸至與位於溝渠106之頂端邊角處 (Top Corner) 120的墊氧化層102接觸。 請參照第1D圖，在溝渠106中塡入絕緣層110，例如 是利用常壓化學氣相沉積法（APCVD)形成的氧化矽層。 接著，再於高溫下，執行密實化（Dens i f i ca t i on )步驟， 以形成氧化矽材質之絕緣層110。 在絕緣層110進行密實化步驟時，由於氧化砂材質的 絕緣層110會對矽基底100產生機械應力（Mechanical 4 本紙張尺度通州中囤國家摇^ ( CNS ) A4規格（210X297公釐） '—"· --------1裝------訂-------旅 ί1-/,.ί— (諳先閲讀背面之注意事項再填寫本頁) · 經^‘部中决^牟而員工消贽合作牡印？水 3450twf.doc/006 A7 B7 經沪‘部中央榀準杓只工消费合作社印製 五、發明説明（>) Stress)，進而h成兀件的失效（Devjce Faiiure)。 其後，請參照第1E圖，以氮化矽罩幕層1〇4作爲硏磨 終止層，利用化學機械硏磨法去除氮化矽罩幕層104上之 多餘的絕緣層110 ’而在溝渠1〇6中殘餘著絕緣層ii〇a。 請參照第1F圖，去除氮化矽罩幕層丨〇4，露出墊氧化 層102。其後’利用氫氟酸（HF)溶液浸蝕，以去除墊氧 化層102，在基底1〇〇中形成場隔離區11〇b。 上述方法在形成襯氧化層108的高溫熱氧化過程中， 由於所通入的氧氣在溝渠106之頂端邊角處120與溝渠 106所裸露之基底100的內表面，其擴散行爲並不相同， 因此’在溝渠106之頂端邊角處120所形成的襯氧化層1〇8 其厚度較薄。另外’由於以化學氣相沈積法（CVD)所形 成之氧化矽材質之絕緣層110與熱氧化法所形成之襯氧化 層108密度有所差異，因此，在利用氫氟酸溶液浸蝕，以 去除墊氧化層102的蝕刻製程中，會因爲絕緣層ll〇a的 蝕刻率較高於襯氧化層，以及蝕刻的等向性或過度蝕刻 (Over Etch)，而造成絕緣層11〇與矽基底1〇〇表面之 鄰接處發生凹陷區130的情況，進而導致頸結效應（Kmk Effect)。而頸結效應除了會降低臨限電壓（Threshold Voltage)外，亦因相對於主元件區角落寄生（Corner Parasitic)MOSFET之形成，而導致元件漏電的情況發生。 另一方面，絕緣層ll〇b與矽基底100表面之鄰接處的 凹陷情況，亦會使後續沈積於其之上的閘極氧化層厚度較 薄，而較薄的閘極氧化層不僅降低閘極的可靠度，亦因在 5 (諳先閲讀背面之注意事項再填寫本頁} •-φ-裝· -訂·A7 B7 3450twf.doc / 006 V. Description of the Invention (/) The present invention relates to a method for manufacturing an integrated circuit, and more particularly, to a method for manufacturing a shallow trench isolation (STI) region. The element isolation area is used to prevent carriers from moving between adjacent elements through the substrate. A typical device isolation region is formed in a dense semiconductor circuit, such as between field effect transistors (FETs) adjacent to each other in a dynamic random access memory (DRAM) to reduce the generation of field effect transistors. Leakage (Current Leakage) phenomenon. A typical method of forming an element isolation region is to use a local area oxidation technique (LOCOS). As the local area oxidation technology becomes more mature, this technology can be used to obtain a reliable and effective component isolation structure at a lower cost. However, the use of localized area oxidation has the disadvantages of stress generation and the formation of Bird's Beak around the field isolation structure. Among them, the formation of the bird's beak area makes the field isolation structure formed by the LOCOS method on small components not effective for isolation. Therefore, in high density (High Density) components, it must be easier to adjust the size. Element isolation structure formed by the shallow trench isolation method. Shallow trench isolation is a technique that uses a non-isotropic etching method to form a trench in a semiconductor substrate, and then implants an oxide into the trench to form a field isolation region for the device. The field isolation area formed by the shallow trench isolation method has the advantages of being scalable, and can avoid the disadvantages of Bis (Ts Beak Encroachment) in the traditional area oxidation isolation technology, so 'for Sub-Micron 3 This paper size applies to Chinese national standards (CNS > A4 size (210X297 mm) (read the precautions on the back before filling this page)-binding. Order A7 B7 3450twf.doc / 006 5. Description of the Invention (l) The complementary metal-oxide-semiconductor (CMOS) process is an ideal isolation technology. Figures 1A to 1F are cross-sections of a conventional shallow trench isolation manufacturing process. Please refer to FIG. 1A. First, a pad oxidation layer 102 is formed on the sand substrate 100 by a thermal oxidation method. The pad oxidation layer 102 is used to protect the silicon substrate 100 during the manufacturing process. Next, on the pad oxide layer 102, a layer of nitrided sand mask curtain layer 104 is formed by Low Pressure Chemically Vapor Deposition (LPCVD). Then, please refer to FIG. 1B for a conventional method. square A photoresist layer (not shown) is formed on the surface of the silicon nitride mask layer 104, and the silicon nitride mask layer 104, the pad oxide layer 102, and the silicon substrate 100 are sequentially etched in the silicon substrate 100. A trench 106 is formed. Then, the photoresist layer is removed. Referring to FIG. 1C, a high-temperature thermal oxidation method is used to form a liner oxide layer 108 on the surface of the sand substrate 100 exposed by the trench 106, where The lining oxide layer 108 will extend to contact the pad oxide layer 102 located at the top corner 120 of the trench 106. Please refer to FIG. 1D, and insert the insulating layer 110 in the trench 106, for example, using atmospheric pressure chemistry A silicon oxide layer formed by a vapor deposition method (APCVD). Then, a densification step is performed at a high temperature to form an insulating layer 110 made of silicon oxide. The densification step is performed on the insulating layer 110. At the time, the insulating layer 110 made of oxidized sand will cause mechanical stress on the silicon substrate 100 (Mechanical 4 paper size Tongzhou National Store ^ (CNS) A4 specification (210X297 mm) '— " · ----- --- 1 pack ------ order ------- brid 1-/ ,. ί- (谙 先(Please read the notes on the back and fill in this page again.) · After the Ministry of Justice and the employees eliminated the cooperation seal? Water 3450twf.doc / 006 A7 B7 (≫) Stress), and then h failure (Devjce Faiiure). Thereafter, referring to FIG. 1E, the silicon nitride masking layer 10 is used as a honing stop layer, and a chemical mechanical honing method is used to remove the excess insulating layer 110 'on the silicon nitride masking layer 104 to form a trench in the trench. In 106, an insulating layer II0a remains. Referring to FIG. 1F, the silicon nitride mask layer is removed, and the pad oxide layer 102 is exposed. Thereafter, it is etched with a hydrofluoric acid (HF) solution to remove the pad oxidation layer 102, and a field isolation region 11b is formed in the substrate 100. During the high-temperature thermal oxidation process of forming the lining oxide layer 108 described above, the diffusion behavior of the oxygen introduced at the top corner 120 of the trench 106 and the inner surface of the substrate 100 exposed by the trench 106 is different. Therefore, the thickness of the liner oxide layer 108 formed at 120 on the top corner of the trench 106 is thin. In addition, because the density of the silicon oxide insulating layer 110 formed by the chemical vapor deposition (CVD) method and the liner oxide layer 108 formed by the thermal oxidation method are different, the hydrofluoric acid solution is used to remove the During the etching process of the pad oxide layer 102, the insulating layer 11a and the silicon substrate 1 will be caused because the etching rate of the insulating layer 110a is higher than that of the liner oxide layer, and the isotropic or over-etching of the etching (Over Etch). The depression 130 occurs at the adjoining surface of the surface, which leads to the Kmk Effect. In addition to reducing the threshold voltage, the neck-junction effect also causes leakage of components due to the formation of Corner Parasitic MOSFETs relative to the main component area. On the other hand, the depression of the insulation layer 110b adjacent to the surface of the silicon substrate 100 will also make the thickness of the gate oxide layer subsequently deposited on it thinner, and the thinner gate oxide layer not only reduces the gate Extremely reliable, also because of 5 (谙 read the precautions on the back before filling in this page} • -φ- 装 · -Order ·
If 本紙張尺度適Λ]中國國家標準（CNS ) A4規格（210X297公釐) 345〇twf.doc/006 A 7 B7 五、發明説明（y) 溝渠頂端角落累積電荷，導致電場增加，而使上述寄生元 件之問題更加惡化。 因此本發明的目的就是在提供一種淺溝渠隔離區的製 造方法’在淺溝渠的表面上形成氮化矽的緩衝層，且覆蓋 襯氧化層，此緩衝層在製程中可以有效地抵銷淺溝渠中之 絕緣層對矽基底產生的機械應力，因而可以避免元件的失 效。 因此本發明的另一目的就是在提供一種淺溝渠隔離區 的製造方法，在淺溝渠的表面上形成氮化矽的緩衝層，且 覆蓋襯氧化層和淺溝渠之頂端邊角處，以避免習知方法中 由於絕緣層與基底鄰接處凹陷現象所造成的頸結效應，並 減少次臨限電流及寄生元件所造成的元件漏電問題，以進 一步提昇元件的效能。 根據本發明之上述目的與其他目的，提出一種淺溝渠 隔離區的製造方法，包括：在基底上形成一墊氧化餍，並 在墊氧化層上形成一層罩幕層。之後’定義罩幕靥與塾氧 化層’並在基底中形成溝渠後，續在溝渠所裸露的基底表 面形成一層襯氧化層。接著，在溝渠表面上形成〜層緩衝 層，同時覆蓋襯氧化層，並且在溝渠中形成一層絕緣餍。 然後’去除部份的緩衝層、罩幕層和墊氧化層，以形成淺 溝渠隔離區。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： n _ 6 本紙張尺度通;时關家)从胁 〇χ297公逢） —__ ---------^ 裳------訂--------線 丨 / (諳先聞讀背面之注意事項再填寫本頁〕 經沪_部中央"'^而0工消费合作^印製 3450twf.doc/006 A 7 B7 五、發明説明（彡） 圖式之簡單說明： 第1A圖至第1F圖係繪示傳統式淺溝渠隔離區之製造 流程的剖面圖；以及 第2A圖至第2G圖係繪示根據本發明之一實施例，一 種淺溝渠隔離區之製造流程的剖面圖。 圖式之標記說明： 100, 200 基底 102, 202 墊氧化層 104, 204 罩幕層 106, 206 溝渠 108, 208 襯氧化層 110, 110a, 212, 212a 絕緣層 110b, 212b 場隔離區 120，220 頂端邊角處 130 凹陷區 210 緩衝層 實施例 第2A圖至第2G圖係繪示根據本發明之一較佳實施 例，一種淺溝渠隔離區之製造流程的剖面圖。 請參照第2A圖，首先，在矽基底200上形成一層墊氧 化層202，例如以熱氧化法，此墊氧化層202係用以在製 程中保護該矽基底200的表面。接著，在墊氧化層202上， 例如以低壓化學氣相沉積法（LPCVD)形成一層氮化矽罩 幕層204。 7 (#先閱讀背面之注意事項再填寫本頁) -裝· ,隸_ 本紙張尺度適用中國國家操準（CNS ) A4規格（210X297公釐) 3450twf.doc/006 A7 3450twf.doc/006 A7 經沪·部中夾"·準而Ά工消贽合作妇印^ B7 _ 五、發明説明（6 ) 然後，請參照第2B圖，以習知的方法在氮化矽罩 204表面上形成一層光阻層（圖中未顯示），並依序蝕刻 氮化矽罩幕層204、墊氧化層202與矽基底200，例如以 非等向性蝕刻法，用以在矽基底200中形成溝渠206，而 溝渠206的深度約爲0.2〜0.8 μιη。其後，再將光阻層去除。 請參照第2C圖，以高溫熱氧化法，例如於約 900〜1100°C的溫度下，在溝渠206所暴露出的矽基底200 表面，形成襯氧化層208，其厚度約爲100埃〜500埃，其 中襯氧化層208會延伸至與位於溝渠206之頂端邊角處 220的墊氧化層202接觸。 請參照第2D圖，於基底200上形成一層共形的 (Conformal )緩衝層210，例如使用化學氣相沉積法 (CVD)形成的氮化矽層，以覆蓋溝渠206的表面，其厚 度約爲100埃〜1000埃，且覆蓋襯氧化層208。 緩衝層210可以做爲應力釋放緩衝層（Stress Release Buffer)，亦即在後續的製程中，氮化矽的緩衝層210所 產生伸張應力（Tensile Stress)與溝渠206中絕緣層（氧 化矽層）所產生之壓縮應力（Compressive Stress)兩相 抵銷，可以有效地釋放溝渠206中之絕緣層對矽基底產生 的機械應力，因而可以避免元件的失效。 其後，請參照第2E圖，在基底200上形成絕緣層212， 例如是利用化學氣相沉積法（CVD)形成的氧化矽層，絕 '緣層212的厚度約爲5000埃~10000埃，並且塡滿溝渠 206 〇 s (諳先閱讀背面之注意事項再填寫本頁) 'T 裝. 訂 -.卑 本紙張尺度^準（CNS ) A4^#· ( 210X297公釐) " ~ 3450twf.doc/006 A7 B7 經"'·部中央樣準而只-χ消处合作社印聲 五、發明説明（7) 接著’再於高溫下，例如約700~1150°C的溫度卞 行密實化步驟’以形成質地較爲密實之氧化矽材實的執 層 212。 ’、’緣 請參照第2F圖，以氮化矽緩衝層210作爲硏磨終止 層’去除氮化矽緩衝層210上之多餘的絕緣層212，例^口 利用化學機械硏磨法（CMP)，而在溝渠206中殘餘著絕 緣層 212a。 ,、 請參照第2G圖，依序去除部份的緩衝層21〇、罩幕層 204與墊氧化層202’以在基底200中形成場隔離區2l2b。 典型的方法係以濕式蝕刻法，例如磷酸溶液去除墊氧化層 202以上之氮化矽材質的部份的緩衝層21〇和罩幕層 204，裸露出墊氧化層202。其後，再利用濕式蝕刻法，例 如氫氟酸（HF)溶液浸触，以去除塾氧化層202，且暴露 出基底200的表面’進而在基底200中形成場隔離區 212b。 綜上所述，本發明的特徵在於： 1.本發明在淺溝渠的表面上形成氮化矽的緩衝層，且 覆蓋襯氧化層和淺溝渠之頂端邊角處，此緩衝層在製程中 可以有效地抵銷淺溝渠中之絕緣層對较基底產生的機械 應力，因而可以避免元件的失效。 另外’此緩衝層可以避免習知方法中由於絕緣層與基 底鄰接處凹陷現象所造成的頸結效應，並減少次臨限電流 及寄生元件所造成的元件漏電問題，以進一步提昇元件的 效能。 本紙張尺度適州中國國家標準（CNS > A4規格（210X29*7公釐） 衣— f讀先聞讀背面之注意事項再填寫本頁) ΐτ 3450twf.doc/006 A7 B7 五、發明説明（分） 2.本發明的製程均與現有的製程相容，極適合廠商的 生產安排。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (讀先閱讀背面之注意事項再填寫本頁) .裝.If the size of this paper is suitable] Chinese National Standard (CNS) A4 specification (210X297 mm) 345〇twf.doc / 006 A 7 B7 V. Description of the invention (y) The electric charge accumulates at the top corners of the trench, leading to an increase in the electric field, which makes the above The problem of parasitic elements is exacerbated. Therefore, the purpose of the present invention is to provide a method for manufacturing a shallow trench isolation region. 'A buffer layer of silicon nitride is formed on the surface of the shallow trench and the oxide layer is covered. This buffer layer can effectively offset the shallow trench during the manufacturing process. The mechanical stress of the insulating layer on the silicon substrate can prevent the failure of the device. Therefore, another object of the present invention is to provide a method for manufacturing a shallow trench isolation region. A buffer layer of silicon nitride is formed on the surface of the shallow trench, and the oxide layer and the top corners of the shallow trench are covered to avoid habit. In the method, the neck-knot effect caused by the depression at the abutment of the insulating layer and the substrate is reduced, and the problem of component leakage caused by the sub-threshold current and parasitic components is reduced to further improve the performance of the component. According to the above and other objects of the present invention, a method for manufacturing a shallow trench isolation area is provided. The method includes: forming a pad of hafnium oxide on a substrate, and forming a mask layer on the pad oxide layer. After ‘defining the mask 靥 and the 塾 oxide layer’ and forming a trench in the substrate, a layer of lining oxide is formed on the surface of the substrate exposed by the trench. Next, a ~ buffer layer is formed on the surface of the trench, and at the same time, it is covered with an oxide layer, and a layer of insulation is formed in the trench. Then, a portion of the buffer layer, the mask layer, and the pad oxide layer are removed to form a shallow trench isolation area. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: Guan Family) From the threat 〇χ297 公 逢) —__ --------- ^ 衣 -------- Order -------- line 丨 / (谙 First read the notes on the back (Fill in this page again.) After Shanghai_Ministry Central " 'and 0 industry and consumer cooperation ^ printed 3450twf.doc / 006 A 7 B7 V. Description of the invention (彡) Brief description of the drawings: Figures 1A to 1F FIG. 2A to FIG. 2G are cross-sectional views illustrating a manufacturing process of a shallow trench isolation area according to an embodiment of the present invention. Marking description: 100, 200 substrate 102, 202 pad oxide layer 104, 204 mask layer 106, 206 trench 108, 208 liner oxide layer 110, 110a, 212, 212a insulating layer 110b, 212b top corners of field isolation area 120, 220 At 130, the recessed area 210, the buffer layer embodiment, FIGS. 2A to 2G are diagrams illustrating a system of a shallow trench isolation area according to a preferred embodiment of the present invention. A cross-sectional view of the process. Please refer to FIG. 2A. First, a pad oxide layer 202 is formed on the silicon substrate 200, for example, by thermal oxidation, the pad oxide layer 202 is used to protect the surface of the silicon substrate 200 during the manufacturing process. Next, a silicon nitride mask layer 204 is formed on the pad oxide layer 202 by, for example, low pressure chemical vapor deposition (LPCVD). 7 (#Read the precautions on the back before filling this page) This paper size is applicable to China National Standards (CNS) A4 specifications (210X297 mm) 3450twf.doc / 006 A7 3450twf.doc / 006 A7 _ V. Description of the invention (6) Then, referring to FIG. 2B, a photoresist layer (not shown in the figure) is formed on the surface of the silicon nitride mask 204 by a conventional method, and the silicon nitride mask is sequentially etched. The layer 204, the pad oxide layer 202, and the silicon substrate 200, for example, are formed by anisotropic etching to form a trench 206 in the silicon substrate 200, and the depth of the trench 206 is about 0.2 to 0.8 μm. Remove the resist layer. Please refer to Figure 2C, using high temperature thermal oxidation method, such as about 900 ~ 1100 ° C At the temperature, a lining oxide layer 208 is formed on the surface of the silicon substrate 200 exposed by the trench 206, and the thickness is about 100 angstroms to 500 angstroms. The lining oxide layer 208 extends to a distance from the top corner 220 of the trench 206. The pad oxide layer 202 is in contact. Referring to FIG. 2D, a conformal buffer layer 210 is formed on the substrate 200, for example, a silicon nitride layer formed using a chemical vapor deposition (CVD) method to cover the surface of the trench 206, and the thickness is about 100 angstroms to 1000 angstroms, and covers the lining oxide layer 208. The buffer layer 210 can be used as a Stress Release Buffer layer, that is, in subsequent processes, the tensile stress generated by the buffer layer 210 of silicon nitride and the insulating layer (silicon oxide layer) in the trench 206 The two phases of the generated compressive stress (Compressive Stress) can effectively release the mechanical stress of the silicon substrate on the silicon substrate caused by the insulating layer in the trench 206, so that the failure of the component can be avoided. Thereafter, referring to FIG. 2E, an insulating layer 212 is formed on the substrate 200, for example, a silicon oxide layer formed by a chemical vapor deposition (CVD) method. The thickness of the insulating layer 212 is about 5000 angstroms to 10,000 angstroms. And it ’s over 206 s (please read the notes on the back before filling in this page) 'T Pack. Order-. Standard paper size ^ standard (CNS) A4 ^ # · (210X297 mm) " ~ 3450twf. doc / 006 A7 B7 "Quality of the central part of the sample, but only-χ eradication of the cooperative cooperative seal V. Description of the invention (7) Then 'under the high temperature, for example, about 700 ~ 1150 ° C temperature compaction Step 'to form a solid layer 212 of denser silicon oxide material. Please refer to FIG. 2F for the “,” margin, and use the silicon nitride buffer layer 210 as a honing stop layer. 'Remove the excess insulating layer 212 on the silicon nitride buffer layer 210. And an insulating layer 212a remains in the trench 206. Referring to FIG. 2G, a part of the buffer layer 21, the mask layer 204, and the pad oxide layer 202 'are sequentially removed to form a field isolation region 2112b in the substrate 200. A typical method is to use a wet etching method, such as a phosphoric acid solution, to remove the buffer layer 21 and the mask layer 204 of the silicon nitride material above the pad oxide layer 202, and expose the pad oxide layer 202. Thereafter, a wet etching method, such as immersion in a hydrofluoric acid (HF) solution, is used to remove the hafnium oxide layer 202 and expose the surface of the substrate 200 'to form a field isolation region 212b in the substrate 200. In summary, the present invention is characterized by: 1. The present invention forms a buffer layer of silicon nitride on the surface of a shallow trench, and covers the lining oxide layer and the top corners of the shallow trench. This buffer layer can be used in the manufacturing process. Effectively offset the mechanical stress of the insulating layer in the shallow trench on the substrate, so that component failure can be avoided. In addition, this buffer layer can avoid the neck-knot effect caused by the depression phenomenon at the abutment of the insulating layer and the substrate in the conventional method, and reduce the component leakage problem caused by the sub-threshold current and parasitic components, so as to further improve the component performance. This paper is in accordance with China's national standard (CNS > A4 size (210X29 * 7mm). Clothing — f Read first and read the notes on the back before filling out this page) Points) 2. The manufacturing process of the present invention is compatible with the existing manufacturing process, which is very suitable for the production arrangement of the manufacturer. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Read the precautions on the back before filling this page).
、1T -線· 經淤部中央榀準而只η消贽合作社印製 10 本紙張尺度適川中國國家標準（CNS ) Α4規格（210X297公釐）、 1T-line · Printed by the central government of the sedimentation department and printed only by the η elimination cooperative. 10 paper sizes are in accordance with China National Standard (CNS) Α4 size (210X297 mm).