451399 A7 61Q2twf.doc/00S B7 五、發明說明（I ) 本發明是有關於一種半導體元件之淺溝渠隔離結構的 製造方法，且特別是有關於一種於溝渠氧化層與基底鄰接 處形成間隙壁（Spacer)以保護淺溝渠隔離結構的製造方 法β 元件之隔離結構係用以防止載子（Carrier)通過基底 在相鄰元件之間移動。傳統上，元件隔離結構形成於稠密 的半導體電路比如是動態隨機存取記憶體（DRAM)中相 鄰的場效電晶體（Field Effect Transistor, FET)間，藉以 減少場效電晶體產生的電荷遺漏（Charge Leakage)。其中 最傳統且普遍的技術爲砂局部氧化技術（Local Oxidation of Silicon，LOCOS)。由於LOCOS技術之曰趨成熟，因此可 藉此技術，以較低的成本獲得信賴度高且有效之元件隔離 結構。然而，LOCOS具有多項缺點，特別是鳥嘴區(Bird’s Beak)所造成的問題，使得在VLSI的元件製作上’ LOCOS 的場隔離結構已不能做有效地隔離。 有鑒於此，已有其他元件隔離方法持續被發展出來’ 其中以淺溝渠隔離（Shallow Trench Isolation’ STI)最被廣 泛應用，尤其應用於次0.25微米（Sub_0.25 Micron)的積體 電路製程中" 第1A圖至第1E圖爲習知之淺溝渠隔離結構之製造流 程剖面圖。 請參照第1A圖，在半導體基底100上形成一墊氧化 層(Pad Oxide) 102。接著，在墊氧化層102上形成一罩幕 層104。經由微影製程定義罩幕層圖案’再非等向性 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ------------r- „^i I (請先閲讀背面之注意事項再填寫本頁) 線- 經濟部智慧財產局員工消費合作社印製 B7 ^ 4513 99 6102twf.doc/008 五、發明說明（·> ) 蝕刻罩幕層104、墊氧化層102及半導體基底1〇〇，以在 該基底100中形成一溝渠106。 請參照第1B圖，形成一絕緣層108覆蓋罩幕層1〇1， 並塡滿溝渠106。 請參照第1C圖，去除罩幕層104上方之絕緣層208 ’ 去除的方法是化學機械硏磨法（Chemical Mechanical Polishing, CMP)，以在溝渠106中形成絕緣插塞l〇8a。 請參照第1D圖，依序去除罩幕層104及墊氧化層102， 裸露出部分絕緣插塞108a。在去除的過程中會先利用熱磷 酸(HsPO1)溶液去除罩幕層104，再以氫氟酸(HF)溶液或是 緩衝氧化砂触刻劑(Buffered Oxide Etch，B0E)去除墊氧化 層102，接著進行形成閘極氧化層前的淸洗步驟。上述之 蝕刻及淸洗步驟，皆是以等向性蝕刻的方式進行，因此絕 緣插塞208a會有少量的氧化物被去除，特別是在絕緣插 塞108a與基底1〇〇的鄰接處，會因蝕刻率的差異而產生 凹陷107，並使溝渠開口轉角105露出。 請參照第1E圖，後續在基底100上形成閘極氧化層 110，並定義形成多晶矽閘極112。在沉積並定義出多晶矽 閘極112時，將會有殘餘的多晶矽113累積在凹陷107中， 因此容易造成元件漏電以及不正常的電性連接。 在上述習知的淺溝渠隔離結構之製程中，凹陷107與 露出之開口轉角105產生的原因，是因爲以氫氟酸溶液或 是緩衝氧化矽蝕刻劑去除墊氧化層102時，由於溶液等向 性蝕刻的緣故，使絕緣插塞108a與基底100的鄰接處容 (請先閲讀背面之法$項再填窝本頁> -ί-β. --線_ 經濟部智慧財產局員工消費合作社印製 1 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 6102twf.doc/008 五、發明說明（乃） 易產生凹陷107，並使溝渠開口轉角105露出。當半導體 元件完成後，裸露之開口轉角105附近將容易累積電荷， 進而降低兀件的臨限電壓.(Threshold Voltage)，產生另一不 正常的次臨限電流（Sub-Threshold Current)，此即爲所謂的 雙峰値效應(Double Hump Effect)。再者，於沉積並定義出 多晶矽閘極112時，由於有殘餘的多晶矽113累積在凹陷 107中，容易造成元件漏電，如此將會降低元件的品質， 降低製程的良率。 因此，本發明的目的就是在提供一種淺溝渠隔離結構 的製造方法，乃是在溝渠中形成絕緣插塞並去除罩幕層之 後，於絕緣插塞突出的側壁上形成間隙壁，用以防止後續 去除墊氧化層時，因蝕刻使溝渠氧化層發生凹陷，以避免 後續製程中的多晶矽殘留在該凹陷處，防止元件漏電。 本發明的另一目的是提供一種淺溝渠隔離結構的製造 方法，使絕緣插塞與基底連接處受到間隙避之保護，因此 溝渠開口轉角處不會露出，將可防止電荷在此累積，避免 元件之雙峰値效應。 根據上述之目的，本發明在於提出一種淺溝渠隔離結 構的製造方法，此方法係在基底上依序形成墊氧化層、罩 幕層’之後定義並蝕刻罩幕層、墊氧化層，並於基底中形 成溝渠。在溝渠中形成襯氧化層，之後形成絕緣層覆蓋在 罩幕層上並塡入溝渠中。去除罩幕層上的絕緣層並形成絕 緣插塞，再去除用以定義溝渠的罩幕層，裸露出部分絕緣 插塞及墊氧化層。接著，形成一薄膜層覆蓋在絕緣插塞及 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） —I—- i······訂·—----！線—-VV (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 3 99 A7 _61Q2twf.doc/008_B7_ 五、發明說明（ψ) 墊氧化層上，然後，去除部分的薄膜層及墊氧化層，以在 絕緣插塞突出的側壁上形成間隙壁。 <諝先閱讀背面之生$項再填寫本頁) 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式簡單說明= 第1A圖至第1E圖爲習知淺溝渠隔離結構之製造流程剖面 圖；以及 第2A圖至第2F圖爲本發明一較隹實施例之淺溝渠隔離結 構之製造流程剖面圖。 圖式之標記說明++ 經濟部智慧財產局員工消費合作社印製 100, 200 :半導體基底 102, 202 :墊氧化層 104, 204 :罩幕層 106, 206 :溝渠 105 :溝渠開口轉角 107 :絕緣插塞之凹陷 108, 208 :絕緣層 108a, 208a :絕緣插塞 209 :薄膜層 110, 210 :閘極氧化層 211 :間隙壁 112, 212 :閘極 113 :多晶矽殘留物 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 13 99 A7 _6102twf.doc/008 B7 五、發明說明（< ) 實施例 第2A圖至第2F圖爲本發明一較佳實施例之淺溝渠隔 (請先閲讀背面之注意事項再填寫本頁) 離結構之製造流程剖面圖。 請參照第2A圖，在半導體基底200上形成墊氧化層 202 >形成方法比如爲熱氧化法。接著’形成罩幕層204 覆蓋在墊氧化層202上，其材質比如是氮化矽，形成方法 比如爲常壓化學氣相沉積法（Atmospheric Pressure CVD, APCVD)。以微影製程定義罩幕層204之圖案，接著非等 向性蝕刻罩幕層204、墊氧化層202及半導體基底200， 以在半導體基底200中形成溝渠206。 請參照第2B圖，形成絕緣層2〇8覆蓋在罩幕層204 之上，並塡滿溝渠206，其材質比如是二氧化矽，形成方 法比如爲常壓化學氣相沉積法。 請參照第2C圖，以罩幕層204爲硏磨終止層，利用 化學機械硏磨法移除罩幕層204以上的絕緣層208，使留 在溝渠206中絕緣層208形成絕緣插塞20Sa。 經濟部智慧財產局員工消費合作社印製 請參照第2D圖，去除罩幕層204，露出絕緣插塞208a 及墊氧化層202，去除的方法比如是溼蝕刻法°此時，絕 緣插塞208a之上表面略高於墊氧化層202之上表面，之 後，形成薄膜層209覆蓋於墊氧化層202及絕緣插塞208a 上。薄膜層209的材質比如是氧化矽或是氮化矽’形成的 方法包括化學氣相沉積法。 請參照第2E圖，去除部分的薄膜層209，以在絕緣插 塞208a突出基底200的側壁形成間隙壁211，去除的方法 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） B7 4 513 9 9 6I02twf.doc/008 五、發明說明（6 ) 包括非等向性蝕刻法，比如是乾蝕刻法。 請參照第2F圖，去除基底200上殘留的墊氧化層2〇2 並進行淸洗步驟，使基底2〇〇露出。之後在基底2〇〇上形 成閘極氧化層210與閘極212，此閘極212係在閘極氧化 層210上沉積並定義一層多晶砂層而形成。 接著’於閘極之兩側行成閘極之間隙壁（未圖示），再 進行自行對準金屬矽化物的製程，在主動區和閘極的表面 形成金屬矽化物層，以降低半導體元件的阻値^ 本發明於絕緣插塞凸出基底的側壁上形成間隙壁之目 的是要在絕緣插塞與半導體基底的鄰接處形成一保護層， 以避免在去除基底上墊氧化層的步驟中，在該鄰接處开多成 凹陷。因爲凹陷的形成將會使後續沉積的多晶矽或自動對 準金屬矽化物殘留其中，而導致元件的漏電。再者，凹陷 的形成會使溝渠開口轉角露出，致使溝渠開口轉角附近容 易累積電荷，進而降低元件的臨限電壓（Threshold Voltage)，出現另一不正常的次臨限電流（Sub_Threshold Current)，產生元件的雙峰値效應（Double Hump Effect)。 雖然本發明已以一較佳實施例掲露如上，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍內，當可作各種之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者爲準。 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐了 -----------I--v-i------訂 --------線-- (諳先閱婧背面之迮意事項再填窝本頁) 經濟部智慧財產局員工消費合作社印製451399 A7 61Q2twf.doc / 00S B7 V. Description of the Invention (I) The present invention relates to a method for manufacturing a shallow trench isolation structure for a semiconductor device, and in particular to a method for forming a partition wall adjacent to a trench oxide layer and a substrate ( (Spacer) Manufacturing method for protecting shallow trench isolation structure β The isolation structure of the element is used to prevent carriers from moving between adjacent elements through the substrate. Traditionally, element isolation structures are formed in dense semiconductor circuits such as field effect transistors (FETs) adjacent to each other in dynamic random access memory (DRAM) to reduce charge leakage from field effect transistors. (Charge Leakage). The most traditional and common technology is the Local Oxidation of Silicon (LOCOS) technology. As LOCOS technology is becoming more mature, it can be used to obtain a reliable and effective component isolation structure at a lower cost. However, LOCOS has a number of disadvantages, especially the problems caused by the bird's beak area, which makes the field isolation structure of 'LOCOS no longer effective for VLSI device fabrication. In view of this, other component isolation methods have been continuously developed. Among them, Shallow Trench Isolation (STI) is the most widely used, especially in the sub-0.25 micron integrated circuit manufacturing process. " Figures 1A to 1E are cross-sectional views of the manufacturing process of a conventional shallow trench isolation structure. Referring to FIG. 1A, a pad oxide layer 102 is formed on the semiconductor substrate 100. Next, a mask layer 104 is formed on the pad oxide layer 102. Defining the pattern of the mask layer through the lithographic process 're-isotropic 3' This paper size is applicable to China National Standard (CNS) A4 (210 X 297 public love) ------------ r- „ ^ i I (Please read the notes on the back before filling this page) Line-Printed B7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 4513 99 6102twf.doc / 008 V. Description of the invention (· >) Etching the curtain layer 104. An oxide layer 102 and a semiconductor substrate 100 are formed to form a trench 106 in the substrate 100. Referring to FIG. 1B, an insulating layer 108 is formed to cover the mask layer 101 and fill the trench 106. Please Referring to FIG. 1C, a method of removing the insulating layer 208 ′ above the mask layer 104 is a chemical mechanical polishing (CMP) method to form an insulating plug 108a in the trench 106. Please refer to FIG. 1D In the figure, the mask layer 104 and the pad oxide layer 102 are sequentially removed, and a part of the insulating plug 108a is exposed. During the removal process, the mask layer 104 is first removed with a hot phosphoric acid (HsPO1) solution, and then hydrofluoric acid (HF ) Solution or Buffered Oxide Etch (B0E) to remove the pad oxide layer 102, then The cleaning step before forming the gate oxide layer is performed. The above-mentioned etching and cleaning steps are performed by isotropic etching, so a small amount of oxide is removed from the insulating plug 208a, especially in the insulation. The abutment between the plug 108a and the substrate 100 will cause a recess 107 due to the difference in etching rate, and expose the trench opening corner 105. Referring to FIG. 1E, a gate oxide layer 110 is subsequently formed on the substrate 100, and It is defined that the polycrystalline silicon gate 112 is formed. When the polycrystalline silicon gate 112 is deposited and defined, residual polycrystalline silicon 113 will accumulate in the recess 107, so it is easy to cause component leakage and abnormal electrical connection. In the process of trench isolation structure, the reason for the depression 107 and the exposed opening corner 105 is that when the pad oxide layer 102 is removed by a hydrofluoric acid solution or a buffered silicon oxide etchant, the solution is isotropically etched. Adjacent content of the insulating plug 108a and the substrate 100 (please read the method on the back of the page, and then fill in the nest page> -ί-β. --LINE_Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 B7 6102twf.doc / 008 5. Description of the invention (Yes) It is easy to generate a depression 107 and expose the trench opening corner 105. When the semiconductor device is completed, Near the corner 105 of the exposed opening, it is easy to accumulate electric charges, thereby reducing the threshold voltage of the component (Threshold Voltage) and generating another abnormal Sub-Threshold Current, which is the so-called double peak Double Hump Effect. Furthermore, when the polycrystalline silicon gate 112 is deposited and defined, the residual polycrystalline silicon 113 accumulates in the recess 107, which may easily cause leakage of the device, which will reduce the quality of the device and reduce the yield of the process. Therefore, the purpose of the present invention is to provide a method for manufacturing a shallow trench isolation structure. After forming an insulating plug in a trench and removing a cover layer, a gap wall is formed on a protruding side wall of the insulating plug to prevent subsequent When the pad oxide layer is removed, the trench oxide layer is recessed due to etching, so that polycrystalline silicon in subsequent processes is not left in the recess, and the device is prevented from leaking electricity. Another object of the present invention is to provide a method for manufacturing a shallow trench isolation structure, so that the connection between the insulating plug and the substrate is protected by a gap, so the corners of the trench opening will not be exposed, which will prevent the charge from accumulating here and avoid components The double-peak chirp effect. According to the above object, the present invention is to provide a method for manufacturing a shallow trench isolation structure. This method is to define and etch a mask layer and a pad oxide layer after sequentially forming a pad oxide layer and a mask layer on the substrate. Form a ditch in. An oxide layer is formed in the trench, and then an insulating layer is formed to cover the mask layer and penetrate into the trench. Remove the insulating layer on the mask layer and form an insulating plug, and then remove the mask layer used to define the trench, exposing part of the insulating plug and pad oxide layer. Next, a thin film layer was formed to cover the insulating plug and 5 paper sizes applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) —I—- i ········ ———— !! Line—-VV (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 99 A7 _61Q2twf.doc / 008_B7_ V. Description of the Invention (ψ) on the oxide layer, then, remove Part of the thin film layer and the pad oxide layer to form a gap wall on the protruding side wall of the insulating plug. < 谞 Read the first $ on the back and then fill out this page) To make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings The detailed description is as follows: Figures 1A to 1E are sectional views of the manufacturing process of the conventional shallow trench isolation structure; and Figures 2A to 2F are shallow trenches according to a comparative embodiment of the present invention. Cross-sectional view of the manufacturing process of the isolation structure. Explanation of the marks on the drawings ++ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 100, 200: semiconductor substrate 102, 202: pad oxide layer 104, 204: cover layer 106, 206: trench 105: trench opening corner 107: insulation Depressions 108, 208: Insulating layers 108a, 208a: Insulating plugs 209: Thin film layers 110, 210: Gate oxide layer 211: Spacer walls 112, 212: Gate 113: Polycrystalline silicon residue 6 National Standard (CNS) A4 Specification (210 X 297 mm) 4 13 99 A7 _6102twf.doc / 008 B7 V. Description of the Invention (<) Embodiments Figures 2A to 2F are a preferred embodiment of the present invention. Shallow trench (please read the precautions on the back before filling this page). Referring to FIG. 2A, a pad oxide layer 202 is formed on the semiconductor substrate 200 > The forming method is, for example, a thermal oxidation method. Next, a mask layer 204 is formed to cover the pad oxide layer 202, and the material is, for example, silicon nitride, and the forming method is, for example, Atmospheric Pressure CVD (APCVD). The pattern of the mask layer 204 is defined by a lithography process, and then the mask layer 204, the pad oxide layer 202, and the semiconductor substrate 200 are anisotropically etched to form a trench 206 in the semiconductor substrate 200. Referring to FIG. 2B, an insulating layer 208 is formed to cover the mask layer 204 and fill the trench 206. The material is, for example, silicon dioxide, and the forming method is, for example, atmospheric pressure chemical vapor deposition. Referring to FIG. 2C, using the mask layer 204 as a honing stop layer, the insulating layer 208 above the mask layer 204 is removed by chemical mechanical honing, so that the insulating layer 208 remaining in the trench 206 forms an insulating plug 20Sa. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 2D. Remove the cover layer 204 to expose the insulating plug 208a and the pad oxide layer 202. The removal method is, for example, wet etching. At this time, the insulating plug 208a The upper surface is slightly higher than the upper surface of the pad oxide layer 202, and then, a thin film layer 209 is formed to cover the pad oxide layer 202 and the insulating plug 208a. The method of forming the material of the thin film layer 209, such as silicon oxide or silicon nitride, includes a chemical vapor deposition method. Please refer to FIG. 2E, remove a part of the thin film layer 209 to form a partition wall 211 on the side wall of the substrate 200 protruding from the insulating plug 208a. The removal method 7 This paper size is applicable to China National Standard (CNS) A4 (210 X 297) (B) B7 4 513 9 9 6I02twf.doc / 008 5. Description of the invention (6) includes anisotropic etching, such as dry etching. Referring to FIG. 2F, the pad oxide layer 200 remaining on the substrate 200 is removed and a cleaning step is performed to expose the substrate 200. A gate oxide layer 210 and a gate electrode 212 are then formed on the substrate 200. The gate electrode 212 is formed by depositing and defining a polycrystalline sand layer on the gate oxide layer 210. Next, a gate spacer (not shown) is formed on both sides of the gate, and then a process of self-aligning the metal silicide is performed to form a metal silicide layer on the surface of the active region and the gate to reduce the semiconductor element. The purpose of the present invention to form a gap wall on the side wall of the insulating plug protruding from the substrate is to form a protective layer adjacent to the insulating plug and the semiconductor substrate, so as to avoid the step of removing the oxide layer on the substrate. , More than a depression in the abutment. The formation of the depression will cause subsequent deposition of polycrystalline silicon or automatic alignment metal silicide to remain in it, resulting in leakage of components. In addition, the formation of the recess will expose the corner of the trench opening, which makes it easy to accumulate charges near the corner of the trench opening, thereby reducing the threshold voltage of the device, and causing another abnormal Sub-Threshold Current to occur. Element's Double Hump Effect. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. 8 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ----------- I--vi ------ order -------- Line-(I read the intentions on the back of Jing before filling in this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs