436974 A7 ____________B7 五、發明説明（） 發明領域： 本發明係關於製程淺溝渠隔離（shallow trench isolation，STI)的方法，特别是關於淺溝渠隔離（STI)之轉 角變圓的方法。 發明背景： 在今日的積體電路工業中，在單一晶片上通常可以 建立數以十萬計的半導體元件。晶片上的每個元件都必 需在電性上加以隔離以確保它們操作之獨立性而不會 影響其它元件。於是’分隔不同元件或不同功能區域之 半導想元件隔離方法就成為現代金屬氧化物半導體 (MOS)積想電路製程中的一個重要技術。對於高積集度 之半導體積體電路來說’元件間不適當之隔離會產生漏 電流，且漏電流會消乾大量的功率。不適當之隔離也會 加重閉鎖現象，並會造成暫時性或永久性的電路損壞。 另外’不適當之隔離會產生雜訊容限（n〇ise margin)退 化，電壓遷移以及串擾訊號（crosstalk；)。 區域氧化隔離法（LOCOS)乃最為人所熟知的隔離 技術。LOCOS藉由氧化矽底材的方式在主動式元件或 功能區域之間產生二氧化矽而提供了隔離。由於矽底材 报容易氧化成二氧化矽’ LOCOS具有方法簡單及成本 低廉之優點，而在超大型積體電路（VLSI)中成為廣泛使 用之隔離技術，然而’由於半導體積體電路之製造趨向 高封裝密度，LOCOS遭遇到尺寸難以隨之調降的瓶 頸。 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X^81釐） ~ ' (請先閲讀背面之注意事項再填寫本頁；> .I11 經濟部智慧財產局工消費合作社印製 43697 4 A7 B7 五、發明説明（） 淺溝渠隔離法（shallow trench isolation, STI)，為另 一個特別適用於高整合積集度之半導體晶片隔離技 術。此方法係在半導體底材中形成溝渠區域，並將絕緣 材料填入溝渠區域中以提供主動元件間或不同的丼區 之間的絕緣瞒離。一般而言，溝渠隔離法較區域氧化隔 離法更容易調整其尺寸之大小。 1994年A .Bryant等人在IEDM技術刊物的671-674 頁上發表其論文”Characteristics of CMOS Device Isolation for the UL SI Age”，其中回顧了區域氡化隔離 法與渠溝隔離法兩種不同的隔離技術的特點。在隔離深 度、隔離平坦性以及主動區域與隔離區域間的轉換各方 面’作者討論了 LOCOS與STI如何加以改進以符合其 調降尺寸之需求。對於深次微米CMOS之製程來說，傳 統的LOCOS隔離遭遇到許多困難，例如烏喙效應的側 向延伸過大’平坦性不足，區域場氧化層稀薄效應，及 應力產生之基板缺陷等。對於LOCOS調降尺寸主要的 挑戰在其尺寸縮小時絕緣體變薄，烏喙結構，以及場植 入侵害。對於未來的CMOS技術而言，最有效的元件隔 離方法不但要能提供主動區域與隔離區域間的轉換，對 元件特性或形態所產生的衝擊也必須最小。所以，由溝 渠回填以及平坦化的成本上來考量，STI以其平坦化之 優勢而能更直接符合上述需求。 一傳统淺溝渠隔離區的製程方法敘述如下。參考第 一圖，一塾氧化層105覆蓋於基材1〇〇上，以及一氮化 矽層110形成於墊氧化層105上，氮化矽層11〇及墊氧 本紙張尺度適用中國國家標準（CMS ) A4現格（2丨0X297公釐） (請先閣讀背面之注意事項再填寫本頁)436974 A7 ____________B7 V. Description of the invention () Field of the invention: The present invention relates to a method for manufacturing shallow trench isolation (STI), especially a method for rounding the corner of shallow trench isolation (STI). BACKGROUND OF THE INVENTION: In today's integrated circuit industry, hundreds of thousands of semiconductor components can usually be built on a single wafer. Each component on the wafer must be electrically isolated to ensure that they operate independently without affecting other components. Therefore, the semiconducting device isolation method that separates different components or different functional areas has become an important technology in the process of modern metal oxide semiconductor (MOS) integrated circuit manufacturing. For a semiconductor integrated circuit with a high accumulation degree, improper isolation between the components will cause leakage current, and the leakage current will drain a large amount of power. Improper isolation can also exacerbate latch-up and cause temporary or permanent circuit damage. In addition, 'inappropriate isolation will cause degradation of noise margin, voltage migration, and crosstalk;'. Local oxidation isolation (LOCOS) is the most well-known isolation technique. LOCOS provides isolation by producing silicon dioxide between active components or functional areas by means of a silicon oxide substrate. Because silicon substrates are easily oxidized to silicon dioxide, LOCOS has the advantages of simple methods and low cost, and has become a widely used isolation technology in very large-scale integrated circuit (VLSI). However, because of the trend of semiconductor integrated circuit manufacturing With high packing density, LOCOS encountered a bottleneck that was difficult to reduce the size. This paper size uses Chinese National Standard (CNS) A4 specification (210X ^ 81%) ~ '(Please read the precautions on the back before filling out this page; > .I11 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperatives, 43697 4 A7 B7 5. Description of the invention () Shallow trench isolation (STI) is another semiconductor wafer isolation technology especially suitable for high integration density. This method forms a trench region in a semiconductor substrate, and Insulation material is filled into the trench area to provide insulation between active components or between different ridges. Generally speaking, trench isolation method is easier to adjust its size than regional oxidation isolation method. 1994 A.Bryant Et al. Published their paper "Characteristics of CMOS Device Isolation for the UL SI Age" on pages 671-674 of the IEDM technical journal, which reviewed the characteristics of two different isolation technologies, namely, the regional tritium isolation method and the trench isolation method. In terms of isolation depth, isolation flatness, and transitions between active and isolated regions', the author discusses how LOCOS and STI can be improved to fit their The need for size reduction. For deep sub-micron CMOS processes, traditional LOCOS isolation encounters many difficulties, such as the lateral extension of the black beak effect is too large, the lack of flatness, the thinning effect of the regional field oxide layer, and the substrate caused by stress. Defects, etc. The main challenge for LOCOS to reduce the size is the thinning of the insulator, the beak structure, and the field invasion when the size is reduced. For the future CMOS technology, the most effective component isolation method must not only provide the active area The transition from the isolation area must also have a minimum impact on the characteristics or shape of the component. Therefore, considering the cost of trench backfill and planarization, STI can more directly meet the above requirements with its planarization advantages. A tradition The manufacturing method of the shallow trench isolation area is described as follows. Referring to the first figure, an oxide layer 105 covers the substrate 100, and a silicon nitride layer 110 is formed on the pad oxide layer 105, and the silicon nitride layer 11 is formed. The paper size is applicable to the Chinese National Standard (CMS) A4 (2 丨 0X297 mm) (please read the precautions on the back before filling in this paper) )
41T 經濟部智慧財產局員工消費合作社印製 A7 436974 B7 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁) 化層105定義了基材100的主動區域其溝渠圊案，然 後，以氮化矽層1 1 0為遮罩，蝕刻基材1 0 0以形成溝渠 112。 參考第二圖，位於溝渠112轉角125的墊氧化層105 以濕蝕刻回蝕，然後，一薄的襯氧化層1 1 5藉著熱氧化 法形成於溝渠的表面，利用電漿增強化學沈積法 (PECVD)沈積一氧化層120於基材上並填滿溝渠112， 最後，對基材實施高溫的熱氧化法，並以化學機械研磨 法（CMP)平坦化該基材，其結果如第三圖所示。 由於在尺寸調整性，平坦化，以及隔離深度上之優 點，溝渠隔離法為深次微求CMOS製程中較佳的隔離技 術。然而溝渠隔離法仍會遭遇到許多問題，例如由於蝕 刻所產生的矽材損壞以及邊角效應，由於在靠近溝渠邊 角的區域閘極電場會有增強的現象，因此容易產生寄生 漏電流路徑。更有甚者，閘極導體會包圍住溝渠邊角。 因此，為了改善上述情形，有必要提出一方法以解決邊 角寄生漏電流以及閘極包圍（gate wrap-around)的問 題。 經濟部智慧財產局員工消費合作社印製 發明目的及概述： 本發明係提供一製程方法，使得淺溝渠隔離區具有更 圓滑的轉角。 本發明的另一目的係提供一兩步驟的製程方法以形 成淺溝渠隔離區的墊氧化層。 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 436974 A7 B7 五、發明説明（） 本發明的再一目的係提供—方法以減少具有淺溝渠 隔離區之元件的漏電流（leakage current)問題。 本發明首先係蝕刻一位於基材上的氮化矽層及一墊 氧化層，以形成具有主動區域的圖案，接著，以氮化矽層 與墊氧化層為遮罩’非等向性地乾蝕刻基材以形成溝渠， 然後’漁餘刻位於溝渠轉角的塾氧化廣，並利用熱氧化法 形成一襯氧化層於溝渠的表面上，然後，沈積一氧化層於 基材上並填滿其溝渠，以濕姓刻製程回姓其乳化層直至位 於溝渠轉角的槻氧化層暴露為止 利用熱氧化法氧化基材，使暴露的概氧化層變厚及變 圊’其厚度約為50至500埃之間，最後，平坦化基材 以形成淺溝渠隔離（STI)區域。 圖式簡單說明： 參考下列的細部說明及附圖，本發明之物件、特徵及 優點，將更顯而易見。 經濟部智丛財產局員工消費合作社印製 (锖先閲讀背面之注意事項再填寫本頁) 第一圈為半導體基材的載面圖’圖中顯示習知技術中 形成溝渠的情形； 第—圖為半導體基材的截面圖，圖中顯示習知技術中 沈積一氧化層並填滿溝渠的情形； 第二圖為半導艘基材的載面圖’圖中顯示習知技術中 形成淺溝渠隔離的情形； 第四圊為半導體基材的截面圖’圖中顯示本發明中形 成溝渠的情形； 本紙浪尺度適用中國國家標準（C^S ) Α4規格（210:¾¾羡） ' --- 436974 A7 B7 五、發明説明（） 第五園為半導體基材的截面圖’圖中顯示本發明中沈 積一氧化層於基材上並填滿溝渠的情形； 第六圖為半導想基材的截面圖，圖中顯示本發明中回 蝕其氡化層的情形； 第七圖為半導想基材的截面圖，圖中顯示本發明中實 施熱氧化法使得溝渠轉角之襯氧化層變厚的情形； 第八圖為半導艘基材的截面圖，圖中顯示本發明中平 坦化基材的情形； 第九圖為半導體基材的截面圈，圖中顯示本發明中形 成CMOS元件於基材之主動區域的情形。 發明詳細說明： 自此，本發明之較佳實施例將與參考的附圖一同敘 述，其中相同的部份將分別以相同的號碼標示》 參考第四圖，利用一具有< 1 〇〇>結晶面之單晶基材 200，一厚度約為50至 500埃的墊氧化層205，藉著傳 統的熱氧化法形成於基材200之上，熱氧化法的溫度約 為700至1150°C，一氮化矽層210藉由 SiH2Cl2及 NH3 為反應物，以LPCVD或PECVD沈積於墊氧化層205上》 然後，蝕刻墊氧化層205及氮化矽層2 10，以形成主 動元件區域的圖案，此蝕刻製程離子以反應蝕刻完成，其 電漿源為含氟的氣體，例如CF4、CHF3、C2F6或C3Fp 以墊氧化層205及氮化矽層210為遮罩，非等向性地乾蝕 刻基材以形成溝渠212，蝕刻電漿源可為Ch、BCi3、HBr ' SF6 或 SiCl4。 -mm---— 本紙張尺度適用中國國家標準（CNS)八4洗格（2!0Χ297公釐） (讀先鬩讀背面之注意事項再填寫本頁} 訂 經濟部智慧財產局員工消費合作社印製 4 3 6 9 7 4 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 參考第五圊，位於溝渠212轉角22 5的墊氧化層2 05 以濕蝕刻製程回蝕，接著，以溫度700至1 1 50°C之間的 熱氧化法形成一襯氧化層215於溝渠的表面上。然後，利 用 LPCVD、PECVD 或 HDPCVD(high density plasma CVD) 厚度介於1000至 10000埃的氧化層220沈積於基材 上，並填滿溝渠 212，氧化層 22 0 的材料可為 TEOS(tetra-tethyl-ortho-silicate)、BPSG、PSG、BSG 或 USG(undoped silicate glass) 〇 參考第六圖，以緩衝氧化蚀刻（buffer oxide etching, B0E)或氫化氟稀釋溶液為蝕刻劑，濕蝕刻氧化層220，蝕 刻進行至位於溝渠212轉角225的襯氧化層215暴露或略 高為止》 經濟部智慧財產局員工消費合作社印製 當位於轉角225的襯氧化層215暴露後，《溫度介於 700至1 150°C，對基材實施熱氧化法，其位於轉角225 的襯氧化層215變厚，厚度約介於50至500埃之間，如 第七圖所示。此熱氧化法會使襯氧化層215的轉角225變 得®滑1並釋放一些基材的應力，以改善應力誘發漏電流 (Stress-Induced Leakage Current, SILC)，及邊緣寄生漏電 流（edge parasitic leakage current)的問題 〇 參考第八圊，實施平坦化該基材。因為氧化層220的 性質與CMP與主動區域的圖案密度有關，以一較佳實施 例而言，需要阻障光阻之RIE與RIE-CMP的平坦化製程， 可以避免盤化/薄化Cdishing/thinning)現象。 參考第九圊’ 一閘極氧化層230、一摻雜多晶矽層240 (CNS ) ( 210¾¾¾ ) ' ί ' 4369 74 Α7 _____Β7_______ __ 五、發明說明（） 及一矽化金屬層250被圖案轉移於主動區域上，摻雜多晶 矽層240及矽化金屬層250是CMOS的閘極，然後，利用 以矽化金屬層250為罩幕，基材以LDD技術處理。氧化 層250沈積於基材上’並圖案轉移於閘極氧化層230、摻 雜多晶矽層240及矽化金屬層250的側壁.最後，基材以 重摻雜技術處理，而形成CMOS的源極與汲極區域。 於本發明中的方法，可以使溝渠212轉角225附近的 襯氧化層215變厚及變圓，並且本發明的改良有以下優 點=一方面，此種轉角的改良可以釋放存在於基材中的應 力，並減少發生應力誘導的漏電流（Stress-Induced Leakage Current，SILC) ’另一方面，亦可降低邊緣寄圭漏電流發生 的機會。所以，轉角225附近之襯氧化層215的處理，可 以大大地改善元件的品質。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之精 神下所完成之等效改變或修飾，均應包含在下述之申請專利 範圍内。 i I I I I ------I--- -------I · ----I--，線：> (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消f合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱）41T Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 436974 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) The chemical layer 105 defines the active area of the substrate 100 and its trenches, and then Using the silicon nitride layer 110 as a mask, the substrate 100 is etched to form the trench 112. Referring to the second figure, the pad oxide layer 105 at the corner 125 of the trench 112 is etched back by wet etching. Then, a thin liner oxide layer 1 1 5 is formed on the surface of the trench by a thermal oxidation method, and a plasma enhanced chemical deposition method is used. (PECVD) An oxide layer 120 is deposited on the substrate and fills the trenches 112. Finally, the substrate is subjected to a high-temperature thermal oxidation method, and the substrate is planarized by chemical mechanical polishing (CMP). As shown. Due to its advantages in sizing, planarization, and isolation depth, trench isolation is a better isolation technique for deep sub-micron CMOS processes. However, the trench isolation method still encounters many problems, such as silicon damage due to etching and corner effects. Since the gate electric field will increase in the area near the corner of the trench, it is easy to produce parasitic leakage current paths. What's more, the gate conductor surrounds the corners of the trench. Therefore, in order to improve the above situation, it is necessary to propose a method to solve the problems of corner parasitic leakage current and gate wrap-around. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics Purpose and summary of the invention: The present invention provides a process method to make the shallow trench isolation zone have a smoother corner. Another object of the present invention is to provide a two-step process method to form a pad oxide layer in a shallow trench isolation region. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 436974 A7 B7 V. Description of the invention () Another object of the present invention is to provide-methods to reduce leakage current of components with shallow trench isolation area (Leakage current) problem. The invention firstly etches a silicon nitride layer and a pad oxide layer on a substrate to form a pattern having an active area, and then uses the silicon nitride layer and the pad oxide layer as a mask to dry anisotropically. The substrate is etched to form a trench, and then the substrate is oxidized at the corner of the trench, and a liner oxide layer is formed on the surface of the trench by thermal oxidation. Then, an oxide layer is deposited on the substrate and fills it. Ditch, use the wet lasting process to return the last name to its emulsified layer until the osmium oxide layer at the corner of the ditch is exposed. The substrate is oxidized by thermal oxidation to make the exposed oxide layer thicker and thicker. Between, and finally, the substrate is planarized to form a shallow trench isolation (STI) region. Brief description of the drawings: With reference to the following detailed description and drawings, the objects, features and advantages of the present invention will be more apparent. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (锖 Read the precautions on the back before filling this page) The first circle is a side view of a semiconductor substrate. The picture shows the situation of the formation of trenches in conventional technologies; The figure is a cross-sectional view of a semiconductor substrate, which shows the deposition of an oxide layer in a conventional technology and fills a trench; the second figure is a cross-sectional view of a semi-conductor substrate; the figure shows a shallow formation in the conventional technology The situation of trench isolation; the fourth is a cross-sectional view of a semiconductor substrate; the figure shows the situation of the formation of trenches in the present invention; the paper scale is applicable to the Chinese national standard (C ^ S) Α4 specification (210: ¾¾xen) '- -436974 A7 B7 V. Explanation of the invention (5) The fifth section is a cross-sectional view of a semiconductor substrate. The figure shows the situation where an oxide layer is deposited on the substrate and fills the trenches in the present invention; the sixth figure is a semiconductive substrate A cross-sectional view of the material shows the situation of the etched-back etched layer in the present invention. The seventh view is a cross-sectional view of the semiconducting substrate, which shows the lining oxide layer formed by the thermal oxidation method in the present invention to make the corner of the trench. Thickening situation; figure eight A cross-sectional view of a semi-conductor substrate, which shows the situation of flattening the substrate in the present invention. The ninth diagram is a cross-section circle of a semiconductor substrate, which shows the situation of forming a CMOS element in the active area of the substrate in the present invention. . Detailed description of the invention: Since then, the preferred embodiment of the present invention will be described together with the referenced drawings, in which the same parts will be marked with the same numbers, respectively. With reference to the fourth figure, a device with < 1 〇〇 & gt A single crystal substrate 200 with a crystalline surface, a pad oxide layer 205 having a thickness of about 50 to 500 angstroms, is formed on the substrate 200 by a conventional thermal oxidation method, and the temperature of the thermal oxidation method is about 700 to 1150 ° C. A silicon nitride layer 210 is deposited on the pad oxide layer 205 by SiH2Cl2 and NH3 as reactants. Then, the pad oxide layer 205 and the silicon nitride layer 210 are etched to form an active device region. Pattern, the ions of this etching process are completed by reactive etching, and the plasma source is a fluorine-containing gas, such as CF4, CHF3, C2F6, or C3Fp with a pad oxide layer 205 and a silicon nitride layer 210 as a mask, and dried anisotropically. The substrate is etched to form the trench 212. The etching plasma source may be Ch, BCI3, HBr'SF6, or SiCl4. -mm ---— This paper size is in accordance with Chinese National Standard (CNS) 8 4 grids (2! 0 × 297 mm) (read the notes on the back and then fill out this page) Order the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 4 3 6 9 7 4 A7 B7 V. Description of the invention () (Please read the notes on the back before filling this page) Refer to the fifth step, the pad oxide layer 2 5 located at the corner 212 of the trench 2 05. Wet etching process Etching back, and then forming a liner oxide layer 215 on the surface of the trench by a thermal oxidation method at a temperature between 700 and 1 1 50 ° C. Then, a thickness of 1000 is formed by using LPCVD, PECVD, or HDPCVD (high density plasma CVD). An oxide layer 220 to 10000 angstroms is deposited on the substrate and fills the trench 212. The material of the oxide layer 22 0 may be TEOS (tetra-tethyl-ortho-silicate), BPSG, PSG, BSG or USG (undoped silicate glass) 〇 Referring to the sixth figure, using buffer oxide etching (BOE) or a dilute hydrogen fluoride solution as an etchant, the oxide layer 220 is wet-etched, and the etching is performed until the liner oxide layer 215 at the corner 225 of the trench 212 is exposed or slightly higher. 》 Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by a consumer cooperative. When the lining oxide layer 215 at the corner 225 is exposed, the temperature is between 700 and 1 150 ° C. The substrate is thermally oxidized. Between 50 and 500 angstroms, as shown in the seventh figure. This thermal oxidation method will make the corner 225 of the liner oxide layer 215 become slippery 1 and release the stress of some substrates to improve the stress-induced leakage current (Stress- Induced Leakage Current (SILC) and edge parasitic leakage current problems. Refer to Chapter 8 for planarization of the substrate. Because the nature of the oxide layer 220 is related to the CMP and the pattern density of the active area, In a preferred embodiment, a planarization process of RIE and RIE-CMP is required to block the photoresist, which can avoid Cdishing / thinning. With reference to the ninth 圊 'a gate oxide layer 230, a doped polycrystalline silicon layer 240 (CNS) (210¾¾¾)' ί '4369 74 Α7 _____ Β7 _______ __ 5. Description of the invention () and a silicided metal layer 250 are pattern-transferred to the active area Above, the doped polycrystalline silicon layer 240 and the silicided metal layer 250 are gates of CMOS. Then, the silicided metal layer 250 is used as a mask, and the substrate is processed by LDD technology. The oxide layer 250 is deposited on the substrate 'and the pattern is transferred to the sidewalls of the gate oxide layer 230, the doped polycrystalline silicon layer 240, and the silicided metal layer 250. Finally, the substrate is processed by a heavy doping technique to form the source and Drain region. The method in the present invention can make the lining oxide layer 215 near the corner 225 of the trench 212 thick and round, and the improvement of the present invention has the following advantages = On the one hand, this improvement of the corner can release the existing in the substrate. Stress and reduce the occurrence of Stress-Induced Leakage Current (SILC) 'On the other hand, it can also reduce the chance of edge leakage currents. Therefore, the treatment of the lining oxide layer 215 near the corner 225 can greatly improve the quality of the device. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application. i IIII ------ I --- ------- I · ---- I--, line: > (Please read the notes on the back before filling this page) Intellectual Property of the Ministry of Economic Affairs The paper size printed by the Bureau's staff and cooperatives applies to the Chinese National Standard (CNS) A4 (210 X 297 public love)