3381.doc/002 3381.doc/002 經濟部中央標準局員工消費合作杜印製 A7 B7 五、發明説明（（） 本發明是有關於一種積體電路元件隔離結構之製造方 法，且特別是有關於一種淺溝渠隔離結構（Shallow Trench Isolation; STI)之製造方法，用以避免淺溝渠隔離結構上 形成微細刮痕（Microscratch)。 兀件隔離區係用以防止載子（Carrier)通過基底而在 相鄰之元件間移動，傳統上，元件隔離區形成於稠密的半 導體電路比如是動態隨機存取記憶體（DRAMs)中相鄰的 場效電晶體（Field Effect Transistor; FET)間，藉以減少 由場效電晶體產生的電荷遺漏（Charge Leakage)。元件 隔離區時常以厚場氧化層的形式延伸，而在半導體基底表 面下形成，其中最傳統且普遍的技術爲矽局部氧化技術 (LOCOS)。由於LOCOS技術之日趨成熟，因此可藉此 技術，以較低的成本獲得信賴度高且有效之元件隔離結 構，然而LOCOS仍具有多項缺點，包括已知應力產生之 相關問題與LOCOS場隔離結構周圍鳥嘴區（Bird，s Beak) 之形成等。而特別是鳥嘴區所造成的問題，使得在小型的 兀件上’ LOCOS場隔離結構不能做有效地隔離。 爲解決上述問題，習知以淺溝渠隔離結構來做爲元件 隔離的結構。習知淺溝渠隔離亦是一種普遍的元件隔離方 法’ 一般使用氮化矽作爲硬罩幕（Hard Mask)，以非等 向性（Anisotropic)蝕刻法在半導體基底上定義陡峭的溝 渠。之後再將溝渠塡滿氧化物層，而提供做爲元件隔離結 構，且此結構具有與原基底表面等高之上表面。然習知之 淺溝渠隔離結構亦有一些問題存在，這些問題將於下做詳 (請先閲讀背面之注意事項再填寫本頁) - 乙 丁 .HI In i^l I --- · ί -- HI I I li— !i— __ J ^.- - HI m i n 、一-11 - - - I - B - - 1-- HI 1^1 ^^1 Hi 1— i m In 1 i-i In m · 3381.doc/002 3381.doc/002 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明u ) 細說明。 第1A圖至第1E圖係繪示習知一種淺溝渠隔離區之製 造流程剖面圖。 請參照第1A圖，在矽基底1〇上形成氧化層n，其 中此氧化層I2作爲墊氧化層（Pad 0xide Layer)之用， 並用於保護基底10的表面，而於後續閘極氧化層形成之 前移去。之後以化學氣相沈積法（CVD)形成氮化矽層14。 然後’在氮化矽層14上形成光阻層18用以定義溝渠，其 中光阻層18已經微影蝕刻製程定義出欲形成淺溝渠隔離 結構的區域。 接著請參照第1B圖，續以此光阻層18爲蝕刻罩幕， 依序蝕刻氮化矽層14、墊氧化層12及基底1〇，使形成氮 化矽層14a和墊氧化層12a，完成在基底上形成溝渠20， 之後再移除蝕刻光阻層18。 接著請參照第1C圖，然後使用熱氧化法，在溝渠20 中的基底10表面形成一層襯氧化（Linear Oxide )層22。 接著，形成一層氧化層32塡滿並溢出溝渠20，而此氧化 層32於對應於溝渠20處會有凹陷的現象。 接著請參照第1D圖，在密實化之後，則以化學機械 硏磨法（Chemical Mechanical Polishing; CMP)去除氮化 矽層24上之多餘的氧化層32，而以氮化矽層24爲硏磨終 點，留下溝渠20區中的氧化插塞32a。 然而，在進行化學機械硏磨步驟時，由於硏漿（Slurry) 和硏磨粒子會磨擦晶片的表面，使氧化插塞33a的表面會 4 (請先閱讀背面之注意事項再填寫本頁)3381.doc / 002 3381.doc / 002 Consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs, printed by Du A7 B7 V. Description of the invention (() The present invention relates to a method for manufacturing integrated circuit component isolation structures, and in particular has A manufacturing method of a shallow trench isolation structure (Shallow Trench Isolation; STI) is used to avoid the formation of microscratch on the shallow trench isolation structure. The element isolation area is used to prevent carriers from passing through the substrate and Adjacent elements move between adjacent elements. Traditionally, element isolation zones are formed in dense semiconductor circuits such as adjacent field effect transistors (FETs) in dynamic random access memories (DRAMs) to reduce Charge leakage generated by field-effect transistors. The device isolation region often extends in the form of a thick field oxide layer and is formed under the surface of a semiconductor substrate. The most traditional and common technology is local silicon oxidation (LOCOS). As LOCOS technology is becoming more mature, this technology can be used to obtain a reliable and effective component isolation structure at a lower cost. LOCOS still has a number of disadvantages, including problems related to known stress generation and the formation of bird's beak areas (Bird, s Beak) around the LOCOS field isolation structure. Especially the problems caused by the bird's beak area make small components "LOCOS field isolation structure cannot be effectively isolated. In order to solve the above problem, it is known to use shallow trench isolation structure as the element isolation structure. It is known that shallow trench isolation is also a common method of element isolation." Nitriding is generally used Silicon is used as a hard mask. Anisotropic etching is used to define steep trenches on a semiconductor substrate. The trenches are then filled with an oxide layer and provided as an element isolation structure. It has an upper surface with the same height as the original base surface. However, the conventional shallow trench isolation structure also has some problems. These problems will be detailed below (please read the precautions on the back before filling this page)-Eding.HI In i ^ l I --- · ί-HI II li—! i— __ J ^ .--HI min, one -11---I-B--1-- HI 1 ^ 1 ^^ 1 Hi 1 — Im In 1 ii In m3381.doc / 002 3381.doc / 002 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of invention u) Detailed description. Figures 1A to 1E are sectional views showing the manufacturing process of a conventional shallow trench isolation area. Referring to FIG. 1A, an oxide layer n is formed on a silicon substrate 10. The oxide layer I2 serves as a pad oxide layer (Pad 0xide Layer), and is used to protect the surface of the substrate 10, and is formed on a subsequent gate oxide layer. Removed before. Thereafter, a silicon nitride layer 14 is formed by a chemical vapor deposition (CVD) method. Then, a photoresist layer 18 is formed on the silicon nitride layer 14 to define a trench, wherein the photoresist layer 18 has been lithographically etched to define a region where a shallow trench isolation structure is to be formed. Next, referring to FIG. 1B, the photoresist layer 18 is used as an etching mask, and the silicon nitride layer 14, the pad oxide layer 12, and the substrate 10 are sequentially etched to form a silicon nitride layer 14a and a pad oxide layer 12a. The trench 20 is formed on the substrate, and then the etching resist 18 is removed. Referring to FIG. 1C, a thermal oxidation method is used to form a linear oxide layer 22 on the surface of the substrate 10 in the trench 20. Then, an oxide layer 32 is formed and overflows the trench 20, and the oxide layer 32 will have a depression corresponding to the trench 20. Next, please refer to FIG. 1D. After the compaction, the chemical oxide polishing (CMP) method is used to remove the excess oxide layer 32 on the silicon nitride layer 24, and the silicon nitride layer 24 is used for honing. At the end point, the oxide plug 32a in the trench 20 region is left. However, during the chemical mechanical honing step, the surface of the oxide plug 33a will be rubbed by the slurry and honing particles, which will rub the surface of the wafer 4 (Please read the precautions on the back before filling this page)
本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） 3381.doc/002 A7 ___£7_^_ 五、發明説明（> ) 產生許多微細刮痕21，且於完成化學機械硏磨步驟後，這 些微細刮痕25很難消除。此外，在歷經常時間的硏磨， 會導致碟化（Dishing) 35問題的產生，且會造成整個晶 片表面的均勻度不隹，即平坦化的效果極差。 接著請參照第1E圖，移去氮化矽層24，.其方法比如 使用熱磷酸（H3P04)溶液。隨後以氫氟酸（HF)浸蝕移 除墊氧化層12a。雖然在移去墊氧化層12a時亦會移除部 份的氧化插塞32a ’使其形成氧化插塞32b，然而氧化插 塞32b的表面依然存在有許多微細刮痕25a，以及碟化35a 現象。這些刮痕21a以及碟化35a現象的地方，將會在後 續MOS的製程中殘留下導電材質，產生架橋（Bridging) 現象或者造成電性短路（Short)，所以會降低產品之良率 (Yield)。後續的半導體製程爲熟習此技藝者所熟知，故 此處不再贅述。 因此本發明的主要目的就是在提供一種淺溝渠隔離結 構之製造方法.，可避免化學機械硏磨步驟造成氧化插塞的 表面產生微細刮痕’以避免產生架橋現象或造成電性短 路，藉以提昇產品良率。 本發明的另一目的就是在提供〜種淺溝渠隔離結構之 製造方法’可避免晶片表面的均勻度不佳，以及碟化問題 的產生。 根據本發明的目的，提出一種淺溝渠隔離結構之製造 方法’首先利用形成於基底上已定義的罩幕層定義基底， 以於基底中形成溝渠。接著形成氧化靥塡入於溝渠中，其 1 本紙ϋ度適用中國國家標準（CNS ) A4規格（210X2.97公釐） --—-- 3381.doc/002 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（匕） 所形成的厚度與溝渠的深度約相同。之後形成保護層覆蓋 氧化層，續進行化學機械硏磨製程，以磨平保護層和氧化 層，直至暴露出罩幕層。最後去除罩幕層，直至暴露出基 底。 其特徵在於溝渠內所填入之氧化材質的厚度只約與溝 渠的深度相同，然後再形成一層保護層，因此於化學機械 硏磨製程期間，可避免硏漿和硏磨粒子直接傷害到溝渠內 的氧化插塞。當完成化學機械硏磨製程且剝除保護層後， 溝渠內氧化插塞的表面沒有微細刮痕，且沒有碟化現象。 故，可以避免微細刮痕或缺陷所產生的架橋現象與電性短 路，因此可提高產品之良率。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1A圖至第1E圖係繪示習知一種淺溝渠隔離結構之 製造流程剖面圖；以及 第2A圖至第2E圖係繪示依照本發明一較佳實施例的 一種淺溝渠隔離結構之製造流程剖面圖。 圖示標記說明： 10、100 :基底 12、112 :墊氧化層 14、114 :罩幕層 25、25a:微細刮痕 35、35a :碟化 讀 先 閔 % 背 意 事 項 再 填 賣 ik 訂 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 3381.doc/002 3381.doc/002 經濟部中央標準局員工消費合作社印裝 A7 __B7_ 五、發明説明（t) 18、118 :光阻層 20、120 :溝渠 22、122:襯氧化層 32、132 :氧化層 32a、32b、132.a、132b :氧化插塞 142、142a :保護層 130 :深度 實施例 第2A圖至第JE圖係繪示依照本發明一較佳實施例的 一種淺溝渠隔離結構之製造流程剖面圖。 首先請參照第2A圖，提供基底1〇〇，比如是具有一 P 型背景摻雜或摻雜P型的表面層之矽基底。在基底100上 形成氧化層112，其中此氧化層112作爲墊氧化層之用， 並用於保護基底100的表面免於遭受後續製程的破壞，而 於後續閘極氧化層形成之前移去。此氧化層112的形成， 比如利用熱氧化法，其厚度約爲50〜5〇〇人。之後以化學氣 相沈積法形成氮化矽層II4，做爲罩幕層之用。然後，在 氮化矽層II4上形成光阻層II1 2用以定義溝渠，其中光阻 層Π2已經微影蝕刻製程定義出欲形成淺溝渠隔離結構的 區域。 接著請參照第2B圖，續以此光阻層11δ的圖案依序 蝕刻氮化矽層II4、墊氧化層U2,並繼續往下蝕刻至基 底1〇〇中，而形成溝渠12〇。其中氮化矽層114和塾氧化 層II2形成氮化砂層l14a和墊氧化層ll2a。蝕刻的方法 (請先閱讀背面之注意事項再填寫本頁)This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 mm) 3381.doc / 002 A7 ___ £ 7 _ ^ _ 5. Description of the invention (>) Many fine scratches 21 are produced, and the chemical mechanical honing is completed After the steps, these fine scratches 25 are difficult to remove. In addition, honing over a long period of time will cause the problem of dishing (Dishing) 35, and will cause the unevenness of the entire wafer surface, that is, the effect of planarization is extremely poor. Next, please refer to FIG. 1E to remove the silicon nitride layer 24. The method is, for example, using a hot phosphoric acid (H3P04) solution. The pad oxide layer 12a is subsequently removed by hydrofluoric acid (HF) etching. Although some of the oxide plugs 32a 'will be removed when the pad oxide layer 12a is removed to form the oxide plugs 32b, the surface of the oxide plugs 32b still has many fine scratches 25a and dishing 35a. . Where these scratches 21a and dishing 35a occur, the conductive material will remain in the subsequent MOS process, resulting in bridging or electrical shorts, so the yield of the product will be reduced. . Subsequent semiconductor processes are well known to those skilled in the art, so they will not be repeated here. Therefore, the main purpose of the present invention is to provide a method for manufacturing a shallow trench isolation structure. It can avoid micro scratches on the surface of the oxidation plug caused by the chemical mechanical honing step, so as to avoid bridging phenomenon or electrical short circuit, thereby improving Product yield. Another object of the present invention is to provide a manufacturing method of a shallow trench isolation structure ', which can avoid the poor uniformity of the wafer surface and the problem of dishing. According to the purpose of the present invention, a method for manufacturing a shallow trench isolation structure is proposed. First, a substrate is defined by using a defined mask layer formed on the substrate to form a trench in the substrate. Oxidation is then formed into the trench, and its 1 paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X2.97 mm) --- 3381.doc / 002 A7 B7 Staff Consumption of the Central Standards Bureau of the Ministry of Economic Affairs Cooperative printed 5. Description of invention (dagger) The thickness formed is about the same as the depth of the trench. A protective layer is then formed to cover the oxide layer, and the chemical mechanical honing process is continued to smooth the protective layer and the oxide layer until the cover layer is exposed. Finally, the mask layer is removed until the substrate is exposed. It is characterized in that the thickness of the oxidized material filled in the trench is only about the same as the depth of the trench, and then a protective layer is formed. Therefore, during the chemical mechanical honing process, the mortar and honing particles can be prevented from directly harming the trench. Oxidation plug. After the chemical mechanical honing process is completed and the protective layer is removed, the surface of the oxidation plug in the trench has no micro scratches and no dishing phenomenon. Therefore, the bridging phenomenon and electrical short circuit caused by micro scratches or defects can be avoided, and the yield of the product can be improved. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1A to FIG. FIG. 1E is a cross-sectional view showing a manufacturing process of a conventional shallow trench isolation structure; and FIGS. 2A to 2E are cross-sectional views showing a manufacturing process of a shallow trench isolation structure according to a preferred embodiment of the present invention. Explanation of icon marks: 10, 100: substrate 12, 112: pad oxide layer 14, 114: mask layer 25, 25a: micro scratches 35, 35a: dishing, reading, reading, and writing ik book Paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 3381.doc / 002 3381.doc / 002 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 __B7_ V. Description of the invention (t) 18, 118: Barrier layers 20, 120: trenches 22, 122: lining oxide layers 32, 132: oxide layers 32a, 32b, 132.a, 132b: oxide plugs 142, 142a: protective layer 130: depth embodiment 2A to JE FIG. Is a cross-sectional view showing a manufacturing process of a shallow trench isolation structure according to a preferred embodiment of the present invention. First, please refer to FIG. 2A to provide a substrate 100, such as a silicon substrate having a P-type background doped or doped P-type surface layer. An oxide layer 112 is formed on the substrate 100. The oxide layer 112 serves as a pad oxide layer and is used to protect the surface of the substrate 100 from being damaged by subsequent processes, and is removed before the subsequent gate oxide layer is formed. The oxide layer 112 is formed, for example, by a thermal oxidation method, and has a thickness of about 50 to 500 people. Then, a silicon nitride layer II4 is formed by a chemical vapor deposition method as a mask layer. Then, a photoresist layer II12 is formed on the silicon nitride layer II4 to define a trench. The photoresist layer II2 has been lithographically etched to define a region where a shallow trench isolation structure is to be formed. Next, referring to FIG. 2B, the silicon nitride layer II4 and the pad oxide layer U2 are sequentially etched in this pattern of the photoresist layer 11δ, and the etching is continued down to the substrate 100 to form a trench 120. The silicon nitride layer 114 and the hafnium oxide layer II2 form a nitrided sand layer 114a and a pad oxide layer 112a. Etching method (Please read the precautions on the back before filling this page)
1 2 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） '~~' ----- 3 3 81. do c/ Ο Ο 2 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（έ ) 比如可使用乾式蝕刻製程或者濕式蝕刻製程。一般而言， 利用非等向性的蝕刻製程，於此基底1〇〇中形^的g渠 12〇,其深度約爲2000〜5〇〇〇A。當此溝渠12〇触刻完成後， 則使用傳統的灰化製程來移除此光阻層118。 接著請參照第2C圖’.然後比如便用熱氧化法，在溝 渠1_2〇中的基底100表面形成一'層襯氧化層I22。之後形 成一層氧化層132約塡滿溝渠120 ’其方法比如使用化學 氣相沉積法，然所沈積的厚度不同於習知，在此本發明中 所沈積的厚度僅約等於溝渠12〇的深度130。對應於溝渠 120處之氧化層132仍有凹陷的現象。本發明的特徵之一， 在於氧化層132上方再形成一層保護層（protective Layer) 142，此保護層142的材質較爲緻密，於化學機械製程中 可以保護溝渠120內的材質不會產生微細刮痕，此保護層 142的材質比如是氮化矽。 接著請參照第2D圖，在密實化之後，則以化學機械 硏磨法去除氮化矽層114a上之多餘的氧化層I32和保護 層142，而以氮化矽層114a爲硏磨終點，留下溝渠12〇區 中的氧化插塞132a，以及保護層142a。由於在溝渠12〇 中的氧化插塞132a有保護層142a做保護，所以在化學機 械硏磨步驟中不會受到硏漿和硏磨粒子的傷害’因此可以 避免產生如習知之微細刮痕；且由於保護層142a的保護’ 所以可以避免溝渠120內之材質被過度蝕刻’因此不會有 碟化的問題產生，使整個晶片表面可以得到極佳的均勻 度。 8 (请先聞讀背面之注意事項再勒賞本頁)1 2 This paper size applies to China National Standard (CNS) A4 (210X297 mm) '~~' ----- 3 3 81. do c / Ο Ο 2 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (Hand) For example, a dry etching process or a wet etching process may be used. Generally speaking, an anisotropic etching process is used to form a g channel 12 in the substrate 100, which has a depth of about 2000 to 5000 A. After the trench 120 is etched, the photoresist layer 118 is removed using a conventional ashing process. Please refer to FIG. 2C ′. Then, for example, a thermal oxidation method is used to form a 'lining oxide layer I22' on the surface of the substrate 100 in the trenches 1-20. Afterwards, an oxide layer 132 is formed to fill the trench 120 ′. For example, a method such as chemical vapor deposition is used, but the deposited thickness is different from the conventional one. In the present invention, the thickness is only approximately equal to the depth 130 of the trench 120. . The oxide layer 132 corresponding to the trench 120 still has the phenomenon of depression. One of the features of the present invention is that a protective layer 142 is formed over the oxide layer 132. The material of the protective layer 142 is dense, and the material in the trench 120 can be protected from fine scratches during the chemical mechanical process. The material of the protective layer 142 is, for example, silicon nitride. Next, please refer to FIG. 2D. After compaction, the excess oxide layer I32 and protective layer 142 on the silicon nitride layer 114a are removed by chemical mechanical honing, and the silicon nitride layer 114a is used as the honing end point. An oxide plug 132a in the lower trench 120 region, and a protective layer 142a. Since the oxidation plug 132a in the trench 120 is protected by a protective layer 142a, it will not be harmed by the slurry and honing particles during the chemical mechanical honing step ', so the micro-scratch as known can be avoided; and Due to the protection of the protective layer 142a, the material in the trench 120 can be prevented from being over-etched, so there is no problem of dishing, so that the entire wafer surface can have excellent uniformity. 8 (Please read the notes on the back before appreciating this page)
本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） i38l.doc/〇〇2 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（7 ) 接著請參照第2E圖，移去氮化矽層ii4a和保護層 142a ’其方法比如使用熱磷酸溶液，以暴露出氧化插塞 132a，由於氧化插塞132a有保護層142a做保護，所以沒 有微細刮痕。隨後以氫氟酸浸蝕移除墊氧化層ma。在移 去墊氧化層ll2a時亦會移除部份的氧化插塞132a，使其 形成氧化插塞132b。由於於本發明中的氧化插塞132b的 表面沒有微細刮痕，亦沒有碟化現象。因此在後續MOS 的製程中不會造成導電材質於氧化插塞132b上方的殘留， 於是可以避免產生架橋現象或者避免造成電性短路，所以 會提高產品之良率。後續的半導體製程爲熟習此技藝者所 熟知，故此處不再贅述。 本發明的特徵在於溝渠內所塡入之氧化材質的厚度只 約與溝渠的深度相同，然後再形成一層保護層，因此於化 學機械硏磨製程期間，可避免硏漿和硏磨粒子直接傷害到 溝渠內的氧化插塞。當完成化學機械硏磨製程且剝除保護 層後，溝渠內氧化插塞的表面沒有微細刮痕，且沒有碟化 現象。故，可以避免微細刮痕或缺陷所產生的架橋現象與 電性短路，因此可提高產品之良率。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾’因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (请先閲讀背面之注意事項再填寫本頁) :裝·This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) i38l.doc / 〇〇2 A7 B7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (7) Then refer to Figure 2E, The silicon nitride layer ii4a and the protective layer 142a are removed by a method such as using a hot phosphoric acid solution to expose the oxidation plug 132a. Since the oxidation plug 132a is protected by the protection layer 142a, there are no micro scratches. Subsequently, the pad oxide layer ma is removed by etching with hydrofluoric acid. When the pad oxide layer 112a is removed, a part of the oxide plug 132a is also removed, so that it forms an oxide plug 132b. Since the surface of the oxidized plug 132b in the present invention is free of fine scratches, there is no dishing phenomenon. Therefore, in the subsequent MOS manufacturing process, the conductive material will not be left over the oxidation plug 132b, so the bridging phenomenon or the electrical short circuit can be avoided, so the yield of the product will be improved. Subsequent semiconductor processes are well known to those skilled in the art, so they will not be repeated here. The present invention is characterized in that the thickness of the oxidized material inserted in the trench is only about the same as the depth of the trench, and then a protective layer is formed. Therefore, during the chemical mechanical honing process, the mortar and the honing particles can be prevented from directly harming them. Oxidation plugs in the trench. After the chemical mechanical honing process is completed and the protective layer is removed, the surface of the oxidation plug in the trench has no micro scratches and no dishing. Therefore, the bridging phenomenon and electrical short circuit caused by micro scratches or defects can be avoided, and the yield of the product can be improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 9 This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page):
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