321783 A7 ____B7 五、發明説明（） 發明領域： 本發明與一種積體電路之淺溝渠絶緣阻隔（shallow trench isolation)之形成方法有關，特别是-種選擇性回 蝕刻及化學機械研磨在淺溝渠阻隔之平坦化應用。 發明背景： 積體電路製程中涉及到一種元件主動區間之絶緣層 之形成方法，因此在製造積體電路時，元件彼此間之绝緣 隔離區域在形成元件之前必須先行製作，目前由於傾向於 將元件縮小化’是故提供製作絶緣隔離區域之空間亦減 少，在次微米技術中製作有效之絶緣隔離區域是一項具挑 戰性之工作，在超大型積體電路中，每個元件間之微小漏 電流將造成整個電路中可觀之能量散失。 目前已有許多種製作絶緣層之方法，例如 LOCOS(l〇cal oxidation of silicon)、淺溝渠絶緣阻隔區 域（shallow trench isolation; STI)等。LOCOS 製程與 _ 種場氧化層（field oxides; FOX)之製作有關主要是在基板 上之非主動區域製作絶緣區域。但是當元件之尺寸逐漸縮 小化時傳統之LOCOS製程將會達到一個極限，例如場氧 化層之鳥嘴效應（bird'sbeak)將深入元件之主動區域，另 夕卜是對次微米之製程而言LOC〇S之外觀地形地勢 I----------i------訂------锊 (請先閔讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 2321783 A7 ____B7 V. Description of the invention () Field of the invention: The present invention relates to a method for forming shallow trench isolation of integrated circuits, in particular-selective back etching and chemical mechanical polishing in shallow trench isolation Flattening application. Background of the Invention: The integrated circuit manufacturing process involves a method of forming an insulating layer in the active area of the device. Therefore, when manufacturing an integrated circuit, the insulating and isolation regions between the components must be manufactured before the device is formed. The “miniaturization of components” means that the space for making insulating isolation areas is also reduced. Making effective insulating isolation areas in sub-micron technology is a challenging task. In ultra-large integrated circuits, the tiny gap between each element Leakage current will cause considerable energy loss in the entire circuit. At present, there are many methods for making an insulating layer, such as LOCOS (10cal oxidation of silicon), shallow trench isolation (STI) and so on. The LOCOS process is related to the production of _field oxides (FOX), which is mainly to form insulating regions on the non-active regions on the substrate. However, when the size of the device is gradually reduced, the traditional LOCOS process will reach a limit, such as the bird's beak effect of the field oxide layer (bird'sbeak) will penetrate into the active area of the device, and the other is for the sub-micron process LOC〇S Appearance Topography I ---------- i ------ Subscribe ------ Cheng (Please read the notes on the back first and then fill out this page) Central Ministry of Economic Affairs Printed by Peking Consumer Cooperative of Standards Bureau 2
經濟部中央標準局員工消費合作社印褽 ^21783 A7 ________B7^___ 五、發明説明（） (topography)不佳’因此利用溝渠絶緣層技術來製作主動 區域間之絶緣區域逐漸受到重視。 在VLSI與ULSI技術中以大量採用溝渠絶緣技術 (trench isolation)做爲元件間之絶緣區域，因此此技術能 夠用來將替代傳統之LOCOS製程。淺溝渠爲利用微影及 敍刻方式製作於基板之中，以化學氣相沈積之氧化層回填 進入淺溝渠中，接著再利用回蝕刻或是化學機械研磨法將 氧化層予以平坦化以得到較佳之外觀地勢 (topography) 〇但是傳統之方法已面臨到一些問題，例如 如第一圖所示’在基板1上較寬廣之溝渠區域經施以化學 機械研磨之後會形成所謂之凹陷結構（dishing)3，另外亦 會形成氧化物與氮化物殘留於晶圓上造成之氮化物無法 被去除’也有可能會產生因氮化物被磨掉的現象 (erosion) 〇 傳统解決上述問題之方法將如下所述，如第二圖所 示，一矽半導體基板1上形成一薄之氧化物做爲墊層（pad Uyer)5 ’此整層5之厚度爲9〇至ι8〇埃’然後—厚度約 爲1500至2000埃之氮化矽層7形成於該墊層5之上做爲 後續平坦化製程之停止層（st〇p layer)。 參閲第二圈，一光阻形成氮化矽層7上做爲定義淺溝 渠區域（罩幕，接著藉由蝕刻技術以光阻爲罩募將氮化矽 本紙張纽適财關家標準（CNS )公麓 --------r--------IT------#—— (請先閱讀背面之注意事項再填寫本f ) 五、發明説明（ A7 B7 層7、垫層5及基板·!蝕刻出一淺溝 則將光阻去除。 及4尔形成I後 參閲第三圏’二氧化矽層9沈锖於 、L ^ ^ 見於上迷您氮化矽層7 (上以及回填進入該淺溝渠之中做爲絶緣之氧化層， 此二氧化矽層9之厚度約爲5000至8〇〇〇埃之間。接著， 一光阻囷案11形成於上述之二氧化矽層9之上，此光阻 11將溝渠區域之上方遮蓋而曝露其他區域。 如第四圖所示，利用此光阻u做爲罩暮將 覆蓋之部份二氧化矽蚀刻，然後再將光阻去 機械研磨技術有一種特性就是在淺溝渠區域上 速率周圍區域快，因此此方法增加在淺溝渠區域 度將改善化學機械研磨後之效果。接著施以一化 磨法（C h e m i c a 1 M e c h a n i c a I Ρ ο Π s h i n g; C Μ Ρ)將 化層9予以平坦化至氮化矽層7之表面。但是在 程需要額外增加一道光阻之製程、蝕刻製程以及 步骤，因此傳统之方法將使產能降低。是故目前 不必額外增加光阻、餘刻以及去除光阻製程之方 產能》 未被光阻 除。化學 方之研磨 上方之厚 學機械研 上述之氧 實施此製 去除光阻 需要一種 法以增進 (請先閲讀背面之注意事項再填寫本頁} .Λ衣. -訂- 镍 經濟部中央標準局貞工消費合作衽印製 i準 標 家 國 國 中 用 一適|啵 -尺 I張 紙i本 I釐 公 7 9 2 A7 製程 經濟部中央榡準局員工消費合作社印製 五、發明説明（） 發明目的及；to述 本發明之目的爲一種積禮電路中元件間絶緣區域之 化學目的爲提供—種利用選擇…刻及 化學機械研磨在淺溝渠阻隔之平坦化應用 ^發明之再-目的爲利帛。z〇ne_TE〇SS pETE〇s 上具有不同蚀刻速率之特性"增進化學機械 研磨製程之品質。 ^ 於矽半導體基板上形成一薄之氧化物做爲墊層，隨 氮化矽層形成於該墊層之上PE_氧化層接著形成於上 述之氮化矽層之上，一光阻圖案定義於PE氧化層之上做 爲形成淺溝渠區域之罩幕，然後利用上述之光阻做爲蝕刻 罩募藉由蝕刻技術將PE_氧化層、氮化矽層、氧化墊層以 及夕基板餘刻形成淺溝渠（sha〗]ow· trench)。完成淺溝渠 足製作之後再將光阻圏案去除。利用化學氣相沈積法形成 〇z〇ne-TEOS ’形成在PE_氧化層上之〇z〇ne_TE〇s之品質 較形成在石夕基板2上的ozone-TEOS差，ozone-TEOS形 成於不同材質上具有不同之溼蝕刻速率，然後使用選擇性 回蝕刻將〇z〇ne-TEOS層蝕刻，隨後利用一化學機械研 磨法（CMP)將上述之〇zone_TEOS層予以平坦化至氮化石夕 層之表面’接著在含氧環境下將ozone_TE〇s層施以熱處 理’此熱處理步驟將增進ozone-TEOS層之緻密性並且將 本紙張尺度適用中國國家標準（CNS ) M規格（21〇><297公釐） - - —i n n 訂 —-I n IJ (請先閲讀背面之注意事項再填寫本頁) A7 經濟部中央標準局員工消費合作社印製 五、發明説明（） 在淺溝渠絶緣層邊緣及底下形成墊襯氧化層⑴η oxide)’此塾說氧化層將提昇淺溝渠絶緣廣之絶緣效果。g 圖式簡單説明： 第一圖爲傳統製程形成凹陷結構於基板上之截面囷； 第二圖爲傳統製程之形成淺溝渠於基板上之截面囷； 第三圖爲傳統製程之形成二氧化矽於氮化矽層之上以 回塡於淺溝渠中之截面囷； 第四圖爲傳統製程之利用微影以及蝕刻製程將二氧化矽 層部份蝕刻形成在溝渠區域上方形成凸出部份之截面 囷； 第五圖爲本發明之形成氧化墊層、氮化矽層以及pE氧化 層於基板上之截面圖； 第六圖爲本發明之形成淺溝渠之截面囷； 第七圖爲本發明之形成〇z〇ne_TE〇s層於PE_氧化層之上 以及回塡淺溝渠中之截面圏； 第八圖爲本發明之選擇性蝕刻去除位於pE_氧化層上之 ozone-TEOS之截面圖； 第九圖爲本發明之CMP將〇z〇ne-TEOS層平坦化之截面 圖；及 第十圖爲本發明之施以熱處理將增進〇zone_TEOS層品 質以及形成概墊氧化層之截面圖。 本紙張尺度適用中國國家標準（CNS ) M規格（21〇χ297公釐） I------.玎------# (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 32Ϊ783 λ7 I --------Β7 五、發明説明（) ~-- 發明詳細説明： 本發明之利用〇zone-TE〇S做爲淺溝渠阻隔絶緣區 | 域之填充物質（gapfilling material)，然後 〇z〇ne TE〇s I對於形成在PE-氧化層及矽上具有不同之蝕刻速率，利用 此選擇性蝕刻特性以及化學機械研磨技術可以增進淺溝 渠阻隔絶緣區域之平坦化效果。本發明之方法不但可以有 效解決傳統方法產生之凹陷現象（dishing)以及氮侵蝕 (erosion)現象也解決氧化物在氮化物上之殘留問題（因氮 化物/PE-TEOS上之用ozone_TE〇s可先用溼蝕刻選擇性 地先去除），而且本發明之方法不需要額外增加一光罩之 製程’製程較簡單且可以增加產能。 以下爲本發明淺溝渠阻隔絶緣區域之方法，如第五圖 所示，一 P型或N型之矽半導體基板2上形成一薄之二氧 化石夕做爲墊層（pad lay er)4，此墊層通常爲利用熱氧化方 式形成厚度約爲90至130埃之間，隨後一厚度爲1500至 2000埃之氮化矽層（siHcon nitride)6形成於該墊層4之上 做爲後續平坦化製程之停止層（st〇p layer)。上述之氮化 石夕層6以較佳實施例而言可以利用低壓化學氣相沈積法Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ 21783 A7 ________ B7 ^ ___ V. Poor invention description () (topography) is poor. Therefore, the use of trench insulation layer technology to create insulating areas between active areas has gradually attracted attention. In VLSI and ULSI technology, a large amount of trench isolation technology (trench isolation) is used as the insulating region between the components, so this technology can be used to replace the traditional LOCOS process. Shallow trenches are fabricated in the substrate using lithography and narrative methods. The chemical vapor deposited oxide layer is backfilled into the shallow trench, and then the oxide layer is planarized using etchback or chemical mechanical polishing to obtain a better comparison. Topography 〇 But the traditional method has already faced some problems, for example, as shown in the first figure, 'the wider trench area on the substrate 1 will form a so-called recessed structure after being subjected to chemical mechanical polishing 3. In addition, oxide and nitride will remain on the wafer and the nitride cannot be removed. It may also cause erosion due to nitride. Traditional methods for solving the above problems will be described below As shown in the second figure, a silicon oxide substrate 1 is formed with a thin oxide as a pad layer (pad Uyer) 5 'the thickness of the entire layer 5 is 90 to ι8〇 Angstrom' and then-a thickness of about 1500 A silicon nitride layer 7 up to 2000 angstroms is formed on the pad layer 5 as a stop layer for the subsequent planarization process. Referring to the second circle, a photoresist is formed on the silicon nitride layer 7 to define a shallow trench region (mask, and then the photoresist is used as a mask by etching technology to apply the silicon nitride paper to the new financial standards ( CNS) Gonglu -------- r -------- IT ------ # —— (please read the precautions on the back before filling in this f) 5. Description of invention (A7 B7 layer 7, pad layer 5 and substrate ·! A shallow trench is etched to remove the photoresist. And after forming 4 I, please refer to the third ring 'silicon dioxide layer 9 Shen Jieyu, L ^ ^ see you above The silicon nitride layer 7 (upper and backfilled into the shallow trench is used as an insulating oxide layer. The thickness of the silicon dioxide layer 9 is about 5000 to 8000 angstroms. Then, a photoresist case 11 Formed on the above-mentioned silicon dioxide layer 9, this photoresist 11 covers the upper part of the trench area to expose other areas. As shown in the fourth figure, using this photoresist u as a mask will cover part of the dioxide Silicon etching, and then removing the photoresist mechanical grinding technology has a characteristic that the speed of the surrounding area is fast in the shallow trench area, so this method increases the degree of shallow trench area will improve the chemical mechanical research After the effect. Then apply a chemical grinding method (C hemica 1 Mechanica I Ρ ο Π shing; C Μ Ρ) to planarize the layer 9 to the surface of the silicon nitride layer 7. But in the process need to add an additional The photoresist process, etching process and steps, so the traditional method will reduce the production capacity. Therefore, there is no need to increase the photoresist, the remaining time and the photoresist removal process. The capacity is not removed by the photoresist. Houjie Machinery Research Group Co., Ltd. The above-mentioned oxygen implementation of this system to remove the photoresist requires a method to improve (please read the precautions on the back and then fill out this page). Λ clothing.-訂-Nickel Ministry of Economic Affairs Central Standards Bureau Zhengong Consumer Cooperation 载Print i prospective bidder home country with a suitable | 啵-ruler I sheets of paper I copy Igong 7 9 2 A7 Process Ministry of Economic Affairs Central Bureau of Precincts printed by the staff consumer cooperatives V. Description of invention () Purpose of invention and; to The purpose of the present invention is to provide a chemical purpose for the insulating area between the components in the circuit. It is to provide-a kind of application using ... engraving and chemical mechanical polishing in the shallow trench barrier flattening application ^ Re-object of the invention For the benefit. The features of different etching rates on z〇ne_TE〇SS pETE〇s " enhance the quality of the chemical mechanical polishing process. ^ A thin oxide is formed on the silicon semiconductor substrate as a pad layer, along with silicon nitride A PE_oxide layer is formed on the pad layer and then formed on the silicon nitride layer. A photoresist pattern is defined on the PE oxide layer as a mask to form the shallow trench region, and then use the above light The resist is used as an etching mask to form a shallow trench (sha〗 ow trench) by etching technology to the PE oxide layer, the silicon nitride layer, the oxide pad layer and the evening substrate. After the shallow trenches were made, the photoresist case was removed. The chemical vapor deposition method is used to form 〇z〇ne-TEOS. The quality of 〇z〇ne_TE〇s formed on the PE_oxide layer is worse than that of the ozone-TEOS formed on the Shixi substrate 2. The ozone-TEOS is formed in different The materials have different wet etching rates, and then use selective etch back to etch the 〇z〇ne-TEOS layer, and then use a chemical mechanical polishing method (CMP) to planarize the above-mentioned zone_TEOS layer to the nitrite layer The surface 'then heat-treat the ozone_TE〇s layer in an oxygen-containing environment' This heat treatment step will increase the density of the zone-TEOS layer and apply this paper scale to the Chinese National Standard (CNS) M specifications (21〇 < 297mm)---inn set --I n IJ (please read the notes on the back before filling in this page) A7 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention description () At the edge of the shallow trench insulation And under the formation of a pad oxide layer (η oxide) 'This school says that the oxide layer will enhance the insulation effect of shallow trench insulation. Brief description of the g diagram: The first picture is the cross-sectional wall of the recessed structure formed on the substrate by the traditional process; the second picture is the cross-sectional wall of the shallow trench formed on the substrate by the traditional process; the third picture is the formation of silicon dioxide by the traditional process The cross-section of the silicon nitride layer is buried in the shallow trench; the fourth picture shows the use of lithography and etching process to etch the silicon dioxide layer partially in the traditional process to form the convex part above the trench area Sectional diagram; Fifth figure is a sectional view of the present invention forming an oxide pad layer, a silicon nitride layer and a pE oxide layer on a substrate; The sixth figure is a sectional view of the present invention forming a shallow trench; The seventh figure is the present invention The formation of a cross-sectional layer of the 〇z〇ne_TE〇s layer on the PE_ oxide layer and the shallow trenches of the Huicheng; Figure 8 is a cross-sectional view of the selective etching of the present invention to remove the ozone-TEOS on the pE_ oxide layer The ninth figure is a cross-sectional view of the CMP planarizing the 〇z〇ne-TEOS layer of the present invention; and the tenth figure is a cross-sectional view of applying the heat treatment of the present invention to improve the quality of the zone_TEOS layer and forming an oxide pad. This paper scale is applicable to the Chinese National Standard (CNS) M specifications (21〇297297 mm) I ------. 玎 ------ # (Please read the precautions on the back before filling this page) Economy Printed 32Ϊ783 λ7 I by Ministry of Standards and Staff Consumer Cooperative -------- B7 V. Description of the invention () ~-Detailed description of the invention: The invention uses 〇zone-TE〇S as a shallow trench barrier insulation The filling material of the area | region (gapfilling material), then 〇z〇ne TE〇s I has a different etching rate for the formation of PE-oxide layer and silicon, using this selective etching characteristics and chemical mechanical polishing technology can improve the shallow The trench blocks the flattening effect of the isolation edge area. The method of the present invention can not only effectively solve the dangling phenomenon and erosion phenomenon caused by the traditional method, but also solve the residual problem of oxide on the nitride (due to the use of ozone_TE〇s on the nitride / PE-TEOS Wet etching is used to selectively remove first), and the method of the present invention does not require an additional process of adding a photomask. The process is simpler and can increase productivity. The following is a method for blocking trench isolation regions of the present invention. As shown in the fifth figure, a thin silicon dioxide substrate is formed on a P-type or N-type silicon semiconductor substrate 2 as a pad lay 4, The pad layer is usually formed by thermal oxidation with a thickness of about 90 to 130 angstroms, and then a silicon nitride layer 6 with a thickness of 1500 to 2000 angstroms (siHcon nitride) 6 is formed on the pad layer 4 for subsequent flatness The stop layer of the chemical process (stop layer). In the preferred embodiment, the above-mentioned nitride nitride layer 6 can use a low-pressure chemical vapor deposition method
(Low Pressure Chemical Vapo'r Deposition; LPCVD) ' 電漿增強式化學氣相沈積法（Plasma Enhance Chemical Vapor Deposition; PECVD)、或高密度電漿化學氣相沈 積法（High Density Plasma Chemical Vapor Deposition; HDPCVD)形成，製程溫度爲350-800 ·〇之間（使用PECVD(Low Pressure Chemical Vapo'r Deposition; LPCVD) 'Plasma Enhance Chemical Vapor Deposition (PECVD), or High Density Plasma Chemical Vapor Deposition; HDPCVD ) Formation, process temperature is between 350-800 · 〇 (using PECVD
本紙張尺度通用r國國家標準（CNS) A4規格（2丨0><297公釐） . .—*1------訂------- (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 五、發明説明（ 之製程溫度約爲350-450 °〇，使用LPCVD之製程溫度约 爲 700-800 ·(〇)，反應氣體爲 SiH4, NH3/ N2, N20 或 sm2ci2, NH3, N2, n2o。 仍請參閲第五圖，一 PE-TEOS氧化層8接著形成於 上述之氮化矽層6之上，PE-TEOS氧化層8爲利用TEOS 爲反應物以電漿增強式製程所形成之二氧化珍層 (plasma enhanced oxide) ’該PE-TEOS氧化層8之較佳 厚度約爲500至1500埃之間。 參閲第六圖，一光阻圖案定義於PE-TEOS氧化層8 之上做爲形成淺溝渠區域之罩幕，然後利用上述之光阻做 爲蝕刻軍募藉由蝕刻技術將PE-TEOS氧化層8、氮化矽 層6、氧化墊層4以及矽基板2蝕刻形成一深度约爲300〇 至5000埃之淺溝渠（shallow trench)。完成淺溝渠之製作 之後再將光阻圖案去除。 參閲第七圖，利用次大氣壓化學氣相沈積法（sub-atmospheric chemical vapor deposition ;SACVD)沈積 氧化層12於上述之PE-TEOS氧化層8之上並且回塡進入 淺溝渠之中做爲絶緣之填充物質，此氧化矽層1 2爲利用 ozone-TEOS爲反應物形成（以下氧化夕層12將稱爲 ozone-TEOS層12)，反應溫度約爲360至440。〇之間。形 成在PE-氧化層8上之ozone-TEOS之品質較形成在矽基 本紙張尺度適用中國國家標準（CNS ) A4規格（21 〇 X 297公釐） , ---^-- (請先閱讀背面之注意事續再填寫本頁) 訂 經濟部中央揉準局貝工消費合作社印製 A7 _____B7 五、發明説明（） 板2上的〇zone_TEOS差，因此ozone-TEOS分别在PE-氧化層8與發上具有不同之渔社刻速率。以本發明之實施 例而T ’形成在石夕2上之ozone-TEOS12之渔姑刻速率约 爲300至320埃/分鐘，形成在氣化梦屠6上之〇z〇ne-TEOS 12之溼蝕刻速率约爲300至360埃/分鐘之間，而形成在 PE-氧化層8上之ozone-TEOS 12之溼蝕刻速率則顯著較 快，約爲2000至2200埃/分鐘。 如第八圖所示，以下步骤爲使用單一钱刻劑進行選擇 性回蝕刻及化學機械研磨特性改善平坦化之結果，換言 之’利用上述之特性配合適當之溼蝕刻劑將〇z〇ne_TE〇S 層12任刻，以較佳實施例而言，此溼钱刻之钱刻劑爲使 用HF或BOE(buffer oxide etching)。由第八圖可知囡蝕 刻速率之差異性（2000 : 300)，蝕刻後將在淺溝渠區域（矽 基板2)之正上方將有凸起之〇z〇ne-TEOS 12a殘留。另外 化學機械研磨技術在淺溝渠區域上方之研磨速率較鄰近 區域快，所以本發明利用在淺溝渠區域凸起之〇z〇ne_ TE OS 12a可以增進化學機械研磨之平坦化效果以及解決 傳統方法之問題，除此之外本發明之方法不需要額外增加 光罩之製程。 如第九圖所示，利用一化學機械研磨法（CMp)將上述 之〇z〇ne-TEOS層12予以平坦化至氮化矽層6之表面。利 用本發明之方法可以提昇淺溝渠製程於CMP後之品質。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公慶） ---------种衣------1T------^ (請先閲讀背面之注意事項再填寫本頁) A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（ 參閲第十圖’接著在含氧環境下將〇z〇ne_T]E〇s層12 施以熱處理’此熱處理步驟將增進〇z〇ne_TE〇s層12之 缴密性並且將在淺溝渠絶緣層（〇z〇neTE〇s層12)邊緣及 底下形成襯墊氧化層（lining 〇xide)14，此襯墊氧化層14 將提昇淺溝#絶緣層1 2之絶緣效果。此熱處理製程之最 佳化製程條件爲在溫度约爲1 〇 〇 〇至11 〇 〇 ·〇之下進行約3 〇 至12 0分鐘。另外’此熱處理也可以在選擇性回蝕刻後， 化學機械研磨前實施。 本發明以較佳實施例説明如上’而熟悉此領域技藝 者，在不脱離本發明之精神範圍内，當可作些許更動潤 飾’例如’本發明利用ozone_TE〇s在不同材質上（矽與 PE-氧化層）具有不同之蝕刻速率特性配合CMp來增進平 坦化（效果，因此凡是利用選擇性回蝕刻及化學機械研磨 特性增進淺溝渠阻隔之平坦化效果均涵蓋於本發明精神 之下，其專利保護範圍更當視後附之申請專利範圍及其等 同領域而定。 10 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 裝 ---訂------絲！----!Γ (請先閲讀背面之注意事項再填寫本頁)The size of this paper is common to the national standard (CNS) A4 specification (2 丨 0> < 297mm)...-* 1 ------ order ------- (please read the notes on the back first Please fill in this page again.) Printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative V. Description of the invention (The process temperature is about 350-450 ° 〇, the process temperature using LPCVD is about 700-800 · (〇), the reaction gas is SiH4, NH3 / N2, N20 or sm2ci2, NH3, N2, n2o. Still referring to the fifth figure, a PE-TEOS oxide layer 8 is then formed on the above-mentioned silicon nitride layer 6, PE-TEOS oxide layer 8 Plasma enhanced oxide (plasma enhanced oxide) formed by using TEOS as a reactant in a plasma enhanced process. The preferred thickness of the PE-TEOS oxide layer 8 is about 500 to 1500 angstroms. Refer to the sixth figure , A photoresist pattern is defined on the PE-TEOS oxide layer 8 as a mask to form a shallow trench area, and then use the photoresist as an etching army to recruit PE-TEOS oxide layer 8 and nitride by etching technology The silicon layer 6, the oxide pad layer 4 and the silicon substrate 2 are etched to form a shallow trench with a depth of about 300 to 5000 angstroms. The shallow trench is completed After that, the photoresist pattern is removed. Referring to the seventh figure, an oxide layer 12 is deposited on the above-mentioned PE-TEOS oxide layer 8 by sub-atmospheric chemical vapor deposition (SACVD) and returned to the substrate Entering the shallow trench as an insulating filling material, the silicon oxide layer 12 is formed by using ozone-TEOS as a reactant (hereinafter the oxide layer 12 will be called ozone-TEOS layer 12), and the reaction temperature is about 360 to 440 〇between. The quality of ozone-TEOS formed on the PE-oxide layer 8 is more applicable to the Chinese National Standard (CNS) A4 specification (21 〇X 297 mm) than that formed on the silicon basic paper scale, --- ^- (Please read the notes on the back and continue to fill out this page) Order A7 _____B7 printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs V. Invention description () The zone_TEOS on board 2 is poor, so ozone-TEOS is in PE -The oxide layer 8 and the hair have different engraving rates for fishing clubs. In the embodiment of the present invention, the fishing engraving rate of ozone-TEOS12 with T ′ formed on Shixi 2 is about 300 to 320 angstroms / minute, which is The wet etching rate of 〇z〇ne-TEOS 12 on the gasification dream slaughter 6 Between 300 to 360 Angstroms / minute, is formed on the ozone-TEOS oxide layer 8 PE- 12 of the wet etching rate is significantly faster than, about 2000 to 2200 angstroms / min. As shown in the eighth figure, the following steps are the results of selective etching back and chemical mechanical polishing characteristics using a single etchant to improve planarization. In other words, the above characteristics are combined with an appropriate wet etchant to 〇z〇ne_TE〇S At any time of layer 12, in a preferred embodiment, the money etching agent for wet money etching is HF or BOE (buffer oxide etching). From the eighth figure, we can see the difference in etching rate (2000: 300). After the etching, there will be a protruding 〇z〇ne-TEOS 12a just above the shallow trench area (silicon substrate 2). In addition, the polishing rate of the chemical mechanical polishing technology above the shallow trench area is faster than that of the adjacent area, so the present invention uses the 〇z〇ne_ TE OS 12a raised in the shallow trench area to improve the planarization effect of chemical mechanical polishing and solve the traditional method. Problem, in addition, the method of the present invention does not require additional manufacturing process of the photomask. As shown in the ninth figure, a chemical mechanical polishing method (CMp) is used to planarize the above-mentioned ZONES-TEOS layer 12 to the surface of the silicon nitride layer 6. The method of the present invention can improve the quality of the shallow trench process after CMP. This paper scale is applicable to China National Standard (CNS) A4 specification (210X297 Gongqing) --------- seed coat ------ 1T ------ ^ (Please read the notes on the back first (Fill in this page again) A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (see the tenth figure 'Then apply the heat treatment to the 〇z〇ne_T] E〇s layer 12 in an oxygen-containing environment' The heat treatment step will enhance the tightness of the 〇z〇ne_TE〇s layer 12 and will form a lining oxide layer (lining 〇xide) 14 on the edge and under the shallow trench insulation layer (〇z〇neTE〇s layer 12), this lining The pad oxide layer 14 will enhance the insulating effect of the shallow trench # insulating layer 12. The optimized process conditions for this heat treatment process are performed at a temperature of about 1,000 to 11,000 under about 30 to 120. In addition, this heat treatment can also be carried out after selective etch back and before chemical mechanical polishing. The present invention is described above with preferred embodiments. Those skilled in the art who are familiar with this field, without departing from the spirit of the present invention, Can be used for a little modification and retouching 'for example', the invention uses ozone_TE〇s on different materials (silicon and PE- Layer) with different etch rate characteristics and CMp to improve planarization (effect, so all the selective planarization and chemical mechanical polishing characteristics to improve the shallow trench barrier planarization effect are covered by the spirit of the present invention, and its patent protection The scope is more dependent on the scope of the attached patent application and its equivalent fields. 10 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm). -! Γ (Please read the notes on the back before filling this page)