CN111081548A - 完全硅化栅控装置及其形成方法 - Google Patents

完全硅化栅控装置及其形成方法 Download PDF

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CN111081548A
CN111081548A CN201910070502.4A CN201910070502A CN111081548A CN 111081548 A CN111081548 A CN 111081548A CN 201910070502 A CN201910070502 A CN 201910070502A CN 111081548 A CN111081548 A CN 111081548A
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CN111081548B (zh
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陈奕寰
周建志
林大为
段孝勤
亚历山大·卡尔尼斯基
郑光茗
吴佳泓
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开的各种实施例涉及一种完全硅化(fully silicided，FUSI)栅控装置及其形成方法，所述方法包括：在衬底上方的栅极结构上形成掩模层，栅极结构包括多晶硅层。在栅极结构的相对侧上的衬底内形成第一源极区及第一漏极区，栅极结构是在第一源极区及第一漏极区之前形成。执行第一移除工艺，以移除掩模层的一部分，并暴露出多晶硅层的上部表面。第一源极区及第一漏极区是在第一移除工艺之前形成。形成与多晶硅层的上部表面直接接触的导电层。导电层是在第一移除工艺之后形成。将导电层和多晶硅层转换成完全硅化层。完全硅化层较薄且厚度均匀。

Description

完全硅化栅控装置及其形成方法
技术领域
本发明实施例是有关于一种完全硅化栅控装置及其形成方法。
背景技术
许多现代电子装置含有金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor；MOSFET)。MOSFET具有布置于源极区与漏极区之间的衬底上方的栅极结构。施加到栅极结构的栅极电极的电压决定MOSFET的导电率。由于高介电常数(k)MOSFET装置微型化的优点，具有完全硅化(fully silicided；FUSI)栅极电极的栅极结构是下一代MOSFET装置的理想候选。
发明内容
根据本发明的一些实施例，一种形成完全硅化栅控装置的方法包括以下工艺。在衬底上方的栅极结构上形成掩模层。栅极结构包括多晶硅层。在栅极结构的相对侧上的衬底内形成第一源极区以及第一漏极区。执行第一移除工艺，以移除掩模层的一部分，并暴露出多晶硅层的上部表面。形成导电层，导电层与多晶硅层的上部表面直接接触。以及将导电层及多晶硅层转换成完全硅化层。
根据本发明的另一些实施例，一种形成完全硅化栅控装置的方法包括以下工艺。在包括多晶硅层的栅极结构上方形成第一掩模层，其中第一掩模层包括分别定义开口的两组侧壁。根据第一掩模层选择性地蚀刻多晶硅层，以移除位于开口正下方的部分栅极结构。在开口下方的衬底内形成第一源极/漏极区以及第二源极/漏极区。在第一掩模层上方形成介电层，其中介电层填充开口。执行平坦化工艺以移除第一掩模层以及介电层的一部分。执行第一蚀刻，以根据位于第一掩模层上方且覆盖开口的第二掩模层来选择性地移除部分的第一掩模层以及多晶硅层。在多晶硅层上方形成导电层。以及执行退火工艺，以将导电层以及多晶硅层转换成硅化物层。
根据本发明的一些实施例，一种完全硅化栅控装置包括第一介电层、高介电常数介电层、金属层、完全硅化层以及多晶硅层。第一介电层位于衬底上方。高介电常数介电层上覆于第一介电层。金属层上覆于高介电常数介电层。完全硅化层上覆于金属层。多晶硅层与完全硅化层的相对侧接触。多晶硅层的底部表面以及完全硅化层的底部表面与金属层接触，以及其中多晶硅层的厚度大于完全硅化层的厚度。
附图说明
结合附图阅读以下详细说明会最佳地理解本公开的各方面。应注意，根据行业中的标准惯例，各种特征未按比例绘制。实际上，为了论述清晰起见，可任意增大或减小各种特征的尺寸。
图1示出一些实施例的包括两个MOSFET装置的集成电路(integrated circuit；IC)的剖视图，所述两个MOSFET装置分别包括位于金属层上方的薄FUSI层。
图2示出一些实施例的包括MOSFET装置的IC的剖视图，所述MOSFET装置包括位于金属层上方的薄FUSI层。
图3和图4示出一些实施例的包括一对MOSFET装置的IC的剖视图，所述一对MOSFET装置分别包括位于金属层上方的薄FUSI层。
图5、图6、图7A、图8到图16示出根据本公开一些实施例的形成包括MOSFET装置的存储器装置的方法的剖视图，所述MOSFET装置包括位于金属层上方的薄FUSI层。
图7B示出一些实施例的在金属层上方包括薄多晶硅层的图7A的剖视图的俯视图。
图17示出根据本公开一些实施例的形成包括MOSFET装置的存储器装置的方法的流程图，所述MOSFET装置在金属层上方具有薄FUSI层的。
具体实施方式
本公开提供用于实施本公开的不同特征的许多不同实施例或实例。下文描述组件和配置的特定实例以简化本公开。当然，这些只是实例且并不意欲为限制性的。举例来说，在以下描述中，第一特征在第二特征上方或第二特征上的形成可包括第一特征和第二特征直接接触地形成的实施例，并且还可包括额外特征可在第一特征与第二特征之间形成使得第一特征和第二特征可不直接接触的实施例。另外，本公开可以在各种实例中重复附图标号和/或字母。此重复是出于简化和清楚的目的，且本身并不规定所论述的各种实施例和/或配置之间的关系。
此外，为易于描述附图中所示的一个组件或特征与另一组件或特征的关系，本文中可使用例如“在...下面(beneath)”、“在...下方(below)”、“下部(lower)”、“在...上方(above)”、“上部(upper)”等空间相对用语。除附图中所绘示的定向之外，所述空间相对术语意欲涵盖装置在使用或操作中的不同定向。设备可以其他方式定向(旋转90度或处于其他定向)，且本文中所使用的空间相对用语可同样相应地进行解译。
典型的金属氧化物半导体场效应晶体管(MOSFET)包括位于衬底内的阱区上方的栅极结构。源极区和漏极区位于栅极结构下方的沟道区的相对侧的衬底中。栅极结构包括设置于栅极介电层上方的栅极电极。从栅极电极向源极区和漏极区施加电压将改变MOSFET的电阻。增加电压将增加沟道区中的电荷载体(例如，电子)的浓度，从而降低源极区与漏极区之间的电阻。
在过去二十年中，MOFSET晶体管通常使用的是包括多晶硅的栅极结构。近年来，高k金属栅极(high k metal gate；HKMG)晶体管已开始广泛使用，因为其能够进一步实现调整并提高MOSFET装置的性能。然而，使用HKMG替换栅极工艺将低电压装置和高电压装置内嵌在一起具有挑战性。HKMG的一种替代方案是使用完全硅化(FUSI)栅极。在制造具有FUSI栅极的MOSFET期间，多晶硅层形成于栅极介电层上方，且金属层形成于多晶硅层上方。执行退火工艺以将多晶硅层和金属层转换成栅极结构的完全硅化(FUSI)栅极电极。随后，源极区和漏极区形成于栅极结构的相对侧上。将导电接触窗(conductive contact)设置于FUSI栅极电极以及源极区和漏极区上方。上方的金属线随后形成于导电接触窗上方的层间介电(inter-level-dielectric；ILD)层内。
理想地，在FUSI工艺期间使用相对较薄的多晶硅层。这是因为较厚的多晶硅层在退火工艺期间将导致工艺问题。举例来说，如果多晶硅层太厚(例如大于大约600埃)，且厚度不均匀，那么退火工艺将无法将整个多晶硅层转换成FUSI栅极电极，使得FUSI栅极电极的一些部分(例如FUSI栅极电极的中心区内)为多晶硅而降低MOSFET装置的性能。然而，已了解在栅极介电层上方形成较薄多晶硅层之后，将存在晶界(grain boundary)，这将产生具有提升高度的凸起缺陷(hump defect)。凸起缺陷导致衬底上的MOSFET装置阵列上方的多晶硅层高度不均匀，这也将在退火工艺期间导致工艺问题。
本公开一些实施例涉及一种形成MOSFET装置的方法，所述方法包括在栅极介电层上方形成包括第一介电层(例如包括高k介电质的第一介电层)的栅极结构，在第一介电层上方形成金属层(例如包括TiN的金属层)，以及在金属层上方形成多晶硅层。多晶硅层均匀地且无缺陷地形成于金属层上，由此消除任何潜在的凸起缺陷问题。形成源极区和漏极区于栅极结构的相对侧上。形成第二介电层于栅极结构以及源极区和漏极区上方。执行平坦化工艺和蚀刻工艺以暴露多晶硅层的上部表面。形成导电层于多晶硅层的上部表面上方，并执行退火工艺以将多晶硅层和导电层转换成FUSI层。在金属层上形成多晶硅层使得多晶硅层较薄(例如厚度约小于300埃)且大体上厚度均匀，确保退火工艺使导电层正下方的整个厚度的多晶硅层硅化。
参考图1，提供根据一些实施例的集成电路(IC)100的剖视图。
IC 100包括衬底101，其中第一MOSFET装置122及第二MOSFET装置124设置于衬底101的上方及衬底101内。在一些实施例中，MOSFET装置又可被称为栅控装置(gateddevice)或栅控结构(gated structure)。蚀刻停止层110设置于衬底101上方以及第一MOSFET装置122及第二MOSFET装置124的侧壁周围。第一层间介电(ILD)层128设置于第一MOSFET装置122和第二MOSFET装置124以及蚀刻停止层110上方。
第一MOSFET装置122和第二MOSFET装置124分别包括栅极结构121。栅极结构121包括栅极介电层112、第一介电层114、金属层116以及完全硅化(FUSI)层118。栅极介电层112与衬底101直接接触。第一介电层114上覆于(overlie)栅极介电层112。金属层116上覆于第一介电层114。FUSI层118上覆于金属层116。在一些实施例中，FUSI层118相对较薄且厚度均匀，举例来说，FUSI层118的每个点的顶部表面至FUSI层118的相应底部表面之间的厚度在约-15埃到+15埃的范围内变化。在一些实施例中，FUSI层118被形成为厚度在约150埃到约300埃的范围内。在其它实施例中，FUSI层118被形成为厚度在约225埃到约300埃的范围内。在一些实施例中，FUSI层118被完全硅化，从而使得FUSI层118的顶部表面与底部表面之间不存在未硅化的多晶硅材料。在一些实施例中，金属层116包括氮化钛(TiN)。侧壁间隙壁120环绕栅极结构121中的相应各层的侧壁。第一导电接触窗126分别上覆于第一MOSFET装置122和第二MOSFET装置124的FUSI层118。
第一源极/漏极区102和第二源极/漏极区104设置于第一MOSFET装置122的栅极结构121的相对侧上。第三源极/漏极区106和第四源极/漏极区108设置于第二MOSFET装置124的栅极结构121的相对侧上。第一源极/漏极区102、第二源极/漏极区104、第三源极/漏极区106以及第四源极/漏极区108设置于衬底101内。第一源极/漏极区102和第二源极/漏极区104具有第一掺杂类型。第三源极/漏极区106和第四源极/漏极区108具有第二掺杂类型。在一些实施例中，第一掺杂类型和第二掺杂类型相同。在又一实施例中，第一掺杂类型为P+型且第二掺杂类型为N+型，或反之亦然。
在一些实施例中，第一MOSFET装置122和第二MOSFET装置124可包括高电压装置。高电压技术已广泛应用于功率管理(power management)、调节器(regulator)、电池保护器、直流电动机(DC motor)、自动化相关(automotive relative)、面板显示驱动器(STN、TFT、OLED等)、彩色显示器驱动器、电源供应器相关、电信等等。在一些实施例中，所公开的MOFSET装置可包括对称和不对称的横向扩散的MOSFET(laterally diffused MOSFET；LDMOS)、双扩散MOSFET(double-diffused MOSFET；DMOS)装置或类似装置。上覆于金属层116的较薄且均匀的FUSI层118确保低电压装置和高电压装置可嵌入在一起。
使FUSI层118上覆于金属层116使得FUSI层118具有相对较薄且均匀的厚度(例如厚度小于或等于约300埃或处于约150埃到300埃的范围内)。此相对较薄且均匀的厚度确保整个厚度的FUSI层118完全硅化，并减少与FUSI层118的厚度相关的工艺问题。具有金属层116确保相反掺杂类型的MOSFET装置可以最小缺陷(例如防止凸起缺陷)嵌入在FUSI层118内的同一平台(platform)上(例如具体地在电压范围为约6伏到32伏的高电压应用中)。
图2示出一些其它实施例的IC 200的剖视图。
IC 200包括衬底101，其中第一MOSFET装置122设置于衬底101上及衬底101内。衬底101可以是例如块状衬底(例如，块状硅衬底)、绝缘体上硅(silicon-on-insulator；SOI)衬底、P掺杂硅或N掺杂硅。第二介电层212上覆于第一MOSFET装置122。第一ILD层128设置于第二介电层212上方。
第一MOSFET装置122包括栅极结构121。栅极结构121包括栅极介电层112、第一介电层114、金属层116以及完全硅化(FUSI)层118。栅极介电层112与衬底101直接接触。在一些实施例中，举例来说，栅极介电层112可为或可包括氧化物(例如氧化硅、氮氧化硅或其类似物)、高k介电质(例如氧化铪、硅酸锆或其类似物)或前述的任何组合，且被形成为厚度为约208埃或处于约50埃到约250埃的范围内。第一介电层114上覆于栅极介电层112。在一些实施例中，举例来说，第一介电层114可为或可包括高k介电质、氧化铪(HfO2)、氧化锆(ZrO，)或前述的任何组合，且被形成为厚度为约10埃、20埃或处于约5埃到约25埃的范围内。在本文中，高k介电质可以是例如介电常数k大于约3.9、10或20的介电质。金属层116上覆于第一介电层114。在一些实施例中，举例来说，金属层116可为或可包括氮化钛(TiN)、钛(Ti)、钽(Ta)、氮化钽(TaN)或前述的任何组合，且被形成为厚度为约10埃、30埃或处于约5埃到约40埃的范围内。FUSI层118上覆于金属层116。在一些实施例中，举例来说，FUSI层118可为或可包括硅化镍、硅化钴、硅化钛、硅化铜或前述的任何组合，且被形成为厚度为约150埃、169埃、200埃、250埃或处于约125埃到约325埃的范围内。
栅极结构121被定义为位于中心区214a内。在一些实施例中，中心区214a居中于栅极结构121的中点(midpoint)(例如，FUSI层118的中点)或中线(midline)处。第一外部区214b和第二外部区214c被定义为位于中心区214a的相对侧上。FUSI层118被定义为位于中心区214a内。整个厚度的FUSI层118完全硅化，从而使得FUSI层118的顶部表面与底部表面之间不存在未硅化的多晶硅材料。第一外部区214b和第二外部区214c分别包括上覆于金属层116的多晶硅层204。在一些实施例中，举例来说，多晶硅层204可为或可包括多晶硅，且被形成为厚度为约150埃、300埃或处于约125埃到约500埃的范围内。在一些实施例中，多晶硅层204的底部层与FUSI层118的底部层对准，且多晶硅层204的厚度大于FUSI层118的厚度。在一些实施例中，多晶硅层204的厚度比FUSI层118的厚度厚约10％、25％、50％或75％。在一些实施例中，多晶硅层204的一部分通过FUSI层118的导电材料而部分或完全硅化。
掩模层210上覆于多晶硅层204。在一些实施例中(未绘示)，掩模层210可从多晶硅层204的正上方延伸到FUSI层118的正上方。在一些此类实施例中，FUSI层118可具有成角外侧(angled outer side)(即，定义FUSI层118与多晶硅层204之间的成角界面)，使得FUSI层118的宽度随着距衬底101的距离增加而增加。在一些实施例中，举例来说，掩模层210可为或可包括氮化硅(SiN)、碳化硅(SiC)、氧化硅(SiO2)或前述的任何组合，且被形成为厚度为约150埃、250埃或处于约100埃到约350埃的范围内。第二介电层212上覆于掩模层210。
第一外部区214b和第二外部区214c分别包括第一接触区209a和第二接触区209b。第一接触区209a和第二接触区209b分别包括被U型蚀刻停止层208包围的第三介电层206。在一些实施例中，中心区214a和栅极结构121被定义为位于第一接触区209a及第二接触区209b的内侧壁之间。第一源极/漏极区102和第二源极/漏极区104分别设置于第一接触区209a和第二接触区209b正下方的衬底101内。第一硅化区102a和第二硅化区104a分别设置于第一源极/漏极区102和第二源极/漏极区104上方。在一些实施例中，第一源极/漏极区102和第二源极/漏极区104具有与衬底101的掺杂类型相反的第一掺杂类型。隔离结构202延伸到衬底101的上部表面或顶部表面中，以提供MOSFET装置122与相邻装置之间的电隔离。隔离结构202包括分别位于MOSFET装置122的相对侧上的一对隔离部分。在一些实施例中，隔离结构202包括介电材料和/或为浅沟槽隔离(STI)结构、深沟槽隔离(deep trenchisolation DTI)结构或其它适合的隔离结构。
参考图3，提供一些实施例的包括第一MOSFET装置122和第二MOSFET装置124的IC300的剖视图。
IC 300包括衬底101，其中第一MOSFET装置122及第二MOSFET装置124设置于衬底101上方及衬底101内。在一些实施例中，衬底101掺杂有N型掺质或P型掺质。在衬底101内，第一阱区304和第二阱区308分别上覆于第一深阱区302和第二深阱区306。第一源极/漏极扩展区303分别沿第一源极/漏极区102和第二源极/漏极区104的内侧壁设置。第一源极/漏极扩展区303包括较低浓度的与第一源极/漏极区102和第二源极/漏极区104相同的掺质。第二源极/漏极扩展区305分别沿第三源极/漏极区106和第四源极/漏极区108的内侧壁设置。第二源极/漏极扩展区305包括较低浓度的与第三源极/漏极区106和第四源极/漏极区108相同的掺质。
在一些实施例中，第一源极/漏极区102和第二源极/漏极区104分别包括第一掺质类型(例如P型或N型)。第一阱区304和第一深阱区302分别包括第二掺质。第一掺质与第二掺质相反。在一些实施例中，第三源极/漏极区106和第四源极/漏极区108分别包括第三掺质。第二阱区308和第二深阱区306分别包括第四掺质。第三掺质与第四掺质相反。在一些实施例中，第一掺质和第三掺质相同或相反，或者第一掺质和第四掺质相同或相反。因此，在一些实施例中，第一MOSFET装置122为N型且第二MOSFET装置124为P型，或反之亦然。在一些实施例中，第一MOSFET装置122和第二MOSFET装置124两者都为N型或P型。
第一MOSFET装置122和第二MOSFET装置124分别包括栅极结构121。栅极结构121包括栅极介电层112、第一介电层114、金属层116、FUSI层118以及第二侧壁间隙壁310。栅极介电层112与衬底101直接接触。第一介电层114设置于栅极介电层112上方。金属层116设置于第一介电层114上方。FUSI层118设置于金属层116上方。第二侧壁间隙壁310包括设置于金属层116上方FUSI层118的相对侧上的两个部分。第二侧壁间隙壁310的两个部分包夹(sandwich)FUSI层118。在一些实施例中，第二侧壁间隙壁310可例如为或包括SiN、SiC、SiO或前述的任何组合。第一ILD层128设置于第一MOSFET装置122和第二MOSFET装置124以及衬底101上方。
第一导电接触窗126分别上覆于第一MOSFET装置122和第二MOSFET装置124的FUSI层118和源极/漏极区(第一源极/漏极区102、第二源极/漏极区104、第三源极/漏极区106以及第四源极/漏极区108)。第一导电接触窗126可例如为或包括钨(W)、铜(Cu)、铝(A1)、前述的组合或其类似物。第一导电线314分别上覆于第一导电接触窗126且设置于第二ILD层312内。第一导电线314可例如为或包括Cu、A1、其组合或其类似物。第二导电通孔318分别上覆于第一导电线314且设置于第三ILD层316内。第二导电通孔318可例如为或包括Cu、A1、其组合或其类似物。第二导电线322分别上覆于第二导电通孔318且设置于第四ILD层320内。第二导电线322可例如为或包括Cu、A1、其组合或其类似物。
参考图4，提供一些实施例的包括第一MOSFET装置122和第二MOSFET装置124的IC400的剖视图。第一MOSFET装置122和第二MOSFET装置124各自如图2的MOSFET装置122所示和所描述，其中第一MOSFET装置122和第二MOSFET装置124各自包括FUSI层118和金属层116。另外，第一MOSFET装置122和第二MOSFET装置124分别包括如图3中所描述的第一阱区304和第二阱区308。在一些实施例中，第一MOSFET装置122和第二MOSFET装置124分别包括设置于第一阱区304和第二阱区308下方的深阱区。在一些实施例中，第一MOSFET装置122为N型且第二MOSFET装置124为P型，或反之亦然。在一些实施例中，第一MOSFET装置122和第二MOSFET装置124两者均为N型或P型。
图5、图6、图7A、图8到图16示出根据本公开一些实施例的形成包括MOSFET装置的IC的方法的剖视图500、剖视图600、剖视图700a、剖视图800到剖视图1600，其中所述MOSFET装置具有FUSI层和金属层。虽然图5、图6、图7A、图8到图16中绘示的剖视图500、剖视图600、剖视图700a、剖视图800到剖视图1600参照一种方法描述，但是应了解，图5、图6、图7A、图8到图16中绘示的结构不限于所述方法，而是可单独作为与所述方法分开的结构。虽然图5、图6、图7A、图8到图16被描述为一系列动作，但是应了解，这些动作不限于所述动作次序，可在其它实施例中更改这些动作的次序，且所公开的方法还适用于其它结构。在其它实施例中，一些示出和/或描述的动作可完全或部分地省略。
如图5的剖视图500中所绘示，形成隔离结构202，隔离结构202延伸到衬底101的上部表面或顶部表面中，以提供MOSFET装置与相邻装置之间的电隔离。举例来说，衬底101可为块状单晶硅衬底、其它适合的块状半导体衬底、绝缘体上硅(SOI)衬底或其它适合的半导体衬底。隔离结构202包括一对隔离部分。在一些实施例中，隔离结构202包括介电材料和/或为浅沟槽隔离(STI)结构、深沟槽隔离(DTI)结构或其它适合的隔离结构。在一些实施例中，形成隔离结构202包括：图案化衬底101以形成沟槽，以及用介电材料填充沟槽。在一些实施例中，形成阱区于隔离结构202的所述一对隔离部分之间的衬底101内。在一些实施例中，形成深阱区于阱区下方。
如图6的剖视图600中所绘示，形成栅极介电层112于衬底101上方。形成第一介电层114于栅极介电层112上方。形成金属层116于第一介电层114上方。举例来说，可通过化学气相沉积(chemical vapor deposition；CVD)、物理气相沉积(physical vapordeposition；PVD)、其它适合的沉积工艺或前述的任何组合来形成栅极介电层112、第一介电层114以及金属层116。
如图7A的剖视图700a中所绘示，形成多晶硅层204于金属层116上方。形成掩模层210于多晶硅层204上方。掩模层210包括定义第一开口702和第二开口704的一组两个侧壁。第一开口702和第二开口704暴露出多晶硅层204的上部表面。举例来说，可通过化学气相沉积(CVD)、物理气相沉积(PVD)、其它适合的沉积工艺或前述的任何组合来形成多晶硅层204和掩模层210。
在一些实施例中，金属层116可例如为或包括氮化钛(TiN)。多晶硅层204以均匀厚度形成于金属层116上方，而减少多晶硅层204内的缺陷(例如，凸起缺陷)。在一些实施例中，此工艺确保多个MOSFET装置分别具有大体上均匀的高度。
图7B示出一些其它实施例的IC 700b的俯视图。
IC 700b包括硅晶片706沿图7A的剖视图700a的水平线(图7A的A与A′之间)的俯视图。所述水平线(图7A的A与A′之间)与多晶硅层204的上部表面对准。多个凸起缺陷204a分布在硅晶片706上。所述多个凸起缺陷204a凸出在多晶硅层204的上部表面上方。所述多个凸起缺陷204a与多晶硅层204的上部表面之间的高度差是归因于在栅极介电层(图7A的112)的上方形成多晶硅层204时的工艺误差(processing error)(例如晶界)导致产生多个凸起缺陷204a。在一些实施例中，所述多个凸起缺陷204a包括遍布硅晶片706的10个或少于10个的凸起缺陷，相比之下，不具有金属层(图7A的116)的实施例包括遍布硅晶片706的1000个或多于1000个凸起缺陷。在一些实施例中，不存在凸起缺陷及所述多个凸起缺陷204a，使得多晶硅层204包括大体上平坦且均匀的上部表面。在一些实施例中，多晶硅层204与水平线对准。因此，金属层(图7A的116)的存在克服多晶硅层204的工艺误差并产生跨越(across)硅晶片706的均匀且无凸起缺陷的上部表面。
如图8的剖视图800中所绘示，执行图案化工艺，以移除位于第一开口和第二开口(图7A的第一开口702、第二开口704)下方的部分栅极介电层112、第一介电层114、金属层116以及多晶硅层204。图案化工艺分别定义第一孔802和第二孔804。在一些实施例中，可通过将第一开口和第二开口(图7A的第一开口702、第二开口704)下方的层暴露于蚀刻剂806来执行图案化工艺。举例来说，可通过光刻/蚀刻工艺和/或其它适合的图案化工艺来执行所述图案化工艺。
形成第一源极/漏极区102和第二源极/漏极区104于第一孔802和第二孔804正下方的衬底101内。形成第一硅化区102a和第二硅化区104a于第一孔802和第二孔804正下方的衬底101内。举例来说，可通过离子植入和/或将掺质植入到衬底101中的其它适合的掺杂工艺来形成第一源极/漏极区102和第二源极/漏极区104。
如图9的剖视图900中所绘示，形成蚀刻停止层208于掩模层210上方并衬于第一孔802和第二孔804的内表面。蚀刻停止层208在第一孔802和第二孔804内具有U型。
如图10的剖视图1000中所绘示，形成第三介电层206于蚀刻停止层208上方。第三介电层206完全填满第一孔802和第二孔804。沿水平线1002执行平坦化工艺(产生图11中所示出的结构)。平坦化工艺移除部分的掩模层210、蚀刻停止层208以及第三介电层206。举例来说，可通过化学机械平坦化(chemical mechanical planarization；CMP)工艺和/或其它适合的平坦化工艺来执行平坦化。
如图11的剖视图1100中所绘示，形成第二掩模层1102于掩模层210、蚀刻停止层208以及第三介电层206上方。第二掩模层1102包括定义位于多晶硅层204正上方的第三开口1104的侧壁。
如图12的剖视图1200中所绘示，执行图案化工艺，以移除部分的掩模层210和多晶硅层204，并定义第三孔1204。在一些实施例中，图案化工艺移除约5埃到约150埃的多晶硅层204，产生比多晶硅层204的外部部分更薄的多晶硅层204的中心部分。在一些实施例中，可通过将第三开口(图11的1104)下方的多晶硅层204暴露于蚀刻剂1202来执行图案化工艺。举例来说，可通过光刻/蚀刻工艺和/或其它适合的图案化工艺来执行所述图案化工艺。
如图13的剖视图1300中所绘示，形成导电层1304于第三孔1204正下方的多晶硅层204上方。在一些实施例中，导电层1304形成于多晶硅层204的中心部分上方，且从多晶硅层204的最外侧壁横向后移非零间隙。在一些实施例中，导电层1304可例如为或包括镍、铂、钯、钴、钛、硅化镍(NiSi)、硅化钴(CoSi)、硅化钛(TiSi)、硅化铜(CuSi)或其类似物，且被形成为厚度约25埃、50埃、75埃或处于约5埃到约150埃的范围内。
进行退火工艺1306，以将多晶硅层204的中心部分和导电层1304转换成FUSI层(图14的118)。退火工艺1306将整个厚度的多晶硅层204的中心部分转换成FUSI层(图14的118)。FUSI层(图14的118)可例如为或包括NiSi、CoSi、TiSi、CuSi或其类似物的硅化物，且被形成为厚度约169埃、150埃、300埃或处于约125埃到约325埃的范围内。在一些实施例中，位于所述中心部分以外的部分多晶硅层(例如图14的FUSI层118的外侧壁以外的部分多晶硅层204)被部分和/或完全硅化。
如图14的剖视图1400中所绘示，通过蚀刻工艺(未绘示)移除第二掩模层(图13的1102)。在一些实施例中，蚀刻工艺可使用干式蚀刻剂。在其它实施例中，蚀刻工艺可使用湿式蚀刻剂(例如，丙酮、1-甲基-2-吡咯烷酮(NMP)或其类似物)。形成第二介电层212于FUSI层118和掩模层210上方。
如图15的剖视图1500中所绘示，形成第一ILD层128于第二介电层212上方。分别形成第一导电接触窗126于第一源极/漏极区102、第二源极/漏极区104以及FUSI层118上方。
如图16的剖视图1600中所绘示，形成互连结构1602于图15的结构上方。互连结构1602包括ILD层1604、ILD层1606、多个导线1622、多个通孔1620以及多个接触垫1624。可例如通过CVD、PVD、其它适合的沉积工艺或前述的任何组合来形成ILD层1604及ILD层1606。所述多个导线1622、多个通孔1620以及多个接触垫1624可例如分别通过以下方法来形成：利用通孔1620、导线1622或接触垫1624的图案将ILD层1604、ILD层1606图案化，以形成通孔、导线或接触垫开口；沉积导电层，以填充通孔、导线、接触垫开口并上覆于ILD层1604、ILD层1606；以及对导电层执行平坦化直到到达ILD层1604或ILD层1606。可例如通过光刻/蚀刻工艺和/或其它适合的图案化工艺来执行图案化。可例如通过CVD、PVD、无电镀覆、电镀、其它适合的沉积工艺或前述的任何组合来进行沉积。可例如通过CMP和/或其它适合的平坦化工艺执行平坦化。所述多个导线1622、多个通孔1620以及多个接触垫1624可例如分别为或包括A1、Cu或其类似物。为便于说明，仅标记所述多个导线1622、多个通孔1620以及多个接触垫1624中的一些。
图17示出根据一些实施例的形成存储器装置的方法1700。虽然方法1700被说明和/或描述为一系列动作或事件，但应了解，所述方法不限于所说明的次序或动作。因此，在一些实施例中，这些动作可以与所说明的不同次序进行，和/或可同时进行。此外，在一些实施例中，所说明的动作或事件可细分成多个动作或事件，所细分出的多个动作或事件可与其他动作或子动作在不同时间进行或同时进行。在一些实施例中，可省略一些所说明的动作或事件，且可包括其它未说明的动作或事件。
在动作1702处，形成第一介电层于衬底上方，形成第二介电层于第一介电层上方，以及形成金属层于第二介电层上方。图6示出对应于动作1702的一些实施例的剖视图600。
在动作1704处，形成多晶硅层于金属层上方并形成第一掩模层于多晶硅层上方，第一掩模层定义开口。图7A示出对应于动作1704的一些实施例的剖视图700a。
在动作1706处，移除多晶硅层、金属层、第二介电层以及第一介电层位于开口正下方的部分，以暴露出衬底的上部表面。图8示出对应于动作1706的一些实施例的剖视图800。
在动作1708处，形成第一源极/漏极区和第二源极/漏极区于衬底内。图8示出对应于动作1708的一些实施例的剖视图800。
在动作1710处，形成蚀刻停止层于第一掩模层和衬底上方。图9示出对应于动作1710的一些实施例的剖视图900。
在动作1712处，形成第三介电层于蚀刻停止层上，第三介电层填充开口。图10示出对应于动作1712的一些实施例的剖视图1000。
在动作1714处，执行平坦化工艺以移除部分的第一掩模层、第三介电层以及蚀刻停止层。图10示出对应于动作1714的一些实施例的剖视图1000。
在动作1716处，形成第二掩模层于第一掩模层上方，第二掩模层覆盖开口。图11示出对应于动作1716的一些实施例的剖视图1100。
在动作1718处，移除部分的第一掩模层和多晶硅层。图12示出对应于动作1718的一些实施例的剖视图1200。
在动作1720处，形成导电层于多晶硅层上方。图13示出对应于动作1720的一些实施例的剖视图1300。
在动作1722处，将导电层和多晶硅层的中心区转换成FUSI层。图13示出对应于动作1722的一些实施例的剖视图1300。
在动作1724处，形成ILD层于FUSI层和第一掩模层上方。图15示出对应于动作1724的一些实施例的剖视图1500。
因此，在一些实施例中，本申请涉及一种MOSFET装置，其包括具有形成于金属层正上方的较薄FUSI层的栅极结构。
在一些实施例中，本申请提供一种用于形成完全硅化(FUSI)栅控装置的方法，所述方法包括：在衬底上方的栅极结构上形成掩模层，栅极结构包括多晶硅层；在栅极结构的相对侧上的衬底内形成第一源极区和第一漏极区，其中栅极结构在第一源极区和第一漏极区之前形成；执行第一移除工艺以移除掩模层的一部分并暴露多晶硅层的上部表面，其中第一源极区和第一漏极区在第一移除工艺之前形成；在第一移除工艺之后形成与多晶硅层的上部表面直接接触的导电层；以及将导电层和多晶硅层转换成FUSI层。
在上述形成完全硅化栅控装置的方法中，其中栅极结构更包括与衬底接触的第一介电层、上覆于第一介电层的高介电常数介电层以及设置于多晶硅层与高介电常数介电层之间的金属层。
在上述形成完全硅化栅控装置的方法中，其中在第一移除工艺之后，多晶硅层包括中心区、第一外部区以及第二外部区，中心区被横向包夹在第一外部区与第二外部区之间，且中心区的高度小于第一外部区的高度及第二外部区的高度；其中在将导电层以及多晶硅层转换成完全硅化层之前，掩模层存在于第一外部区以及第二外部区上方且不存在于中心区上方；以及其中在将导电层以及多晶硅层转换成完全硅化层之后，中心区中整个厚度的多晶硅层被完全硅化且转换为完全硅化层。
在上述形成完全硅化栅控装置的方法中，其中完全硅化层的厚度范围为约150埃至约300埃。
在上述形成完全硅化栅控装置的方法中，更包括：在形成栅极结构之前在衬底内形成阱区，栅极结构形成于阱区正上方。
在上述形成完全硅化栅控装置的方法中，其中在将掩模层形成于栅极结构上方之前，在第一源极区以及第一漏极区内形成硅化物。
在上述形成完全硅化栅控装置的方法中，更包括：在第一移除工艺之前，在掩模层上方形成第二介电层，其中第二介电层完全覆盖位于多晶硅层的上部表面正上方的掩模层的上部表面。
在上述形成完全硅化栅控装置的方法中，更包括：在第一移除工艺之前，执行第一平坦化工艺，以移除部分的掩模层以及第二介电层。
在一些实施例中，本申请提供一种用于形成完全硅化(FUSI)栅控装置的方法，所述方法包括：在包括多晶硅层的栅极结构上方形成第一掩模层，其中第一掩模层包括分别定义开口的两组侧壁；根据第一掩模层选择性地蚀刻多晶硅层，以移除位于开口正下方的部分栅极结构；在开口下方的衬底内形成第一源极/漏极区和第二源极/漏极区；在第一掩模层上方形成第一介电层，其中第一介电层填充开口；执行平坦化工艺，以移除部分的第一掩模层和第一介电层；执行第一蚀刻，以根据位于第一掩模层上方且覆盖开口的第二掩模层选择性地移除部分第一掩模层和部分多晶硅层；在多晶硅层上方形成导电层；以及执行退火工艺，以将导电层和多晶硅层转换成硅化物层。
在上述形成完全硅化栅控装置的方法中，其中在第一蚀刻之后，多晶硅层包括中心区、第一外部区以及第二外部区，中心区被横向包夹在第一外部区与第二外部区之间且居中于栅极结构的中线；其中在退火工艺之前，第一掩模层存在于第一外部区以及第二外部区上方且不存在于中心区上方；以及其中在退火工艺之后，中心区中的整个厚度的多晶硅层被完全硅化且转换为硅化物层。
在上述形成完全硅化栅控装置的方法中，其中硅化物层的厚度范围为约150埃至约300埃。
在上述形成完全硅化栅控装置的方法中，其中在形成第一掩模层之后形成第一源极/漏极区以及第二源极/漏极区，在形成第一源极/漏极区以及第二源极/漏极区之后执行第一蚀刻，在第一蚀刻之后形成导电层，以及在形成导电层之后立即执行退火工艺。
在上述形成完全硅化栅控装置的方法中，其中栅极结构更包括与衬底接触的栅极介电层、上覆于栅极介电层的高介电常数介电层，以及设置于多晶硅层与高介电常数介电层之间的氮化钛层；以及其中第一源极/漏极区以及第二源极/漏极区包括P型掺质。
在上述形成完全硅化栅控装置的方法中，更包括：在形成栅极结构的同时形成第二栅极结构，其中第二栅极结构包括接触衬底的第二栅极介电层、上覆于第二栅极介电层的第二高介电常数介电层、设置于第二多晶硅层与第二高介电常数介电层之间的第二氮化钛层；形成包括N型掺质的第三源极/漏极区以及第四源极/漏极区；其中第一蚀刻移除部分第一掩模层以及部分第二多晶硅层；以及其中退火工艺将第二导电层及第二多晶硅层转换成第二硅化物层。
在上述形成完全硅化栅控装置的方法中，其中硅化物层具有直接接触氮化钛层的底部表面。
在一些实施例中，本申请提供一种完全硅化(FUSI)栅控装置，包括：阱区，设置于衬底内；第一介电层，接触衬底；高介电常数介电层，上覆于第一介电层；金属层，上覆于高介电常数介电层；FUSI层，上覆于金属层；以及多晶硅层，沿FUSI层的相对侧布置，其中多晶硅层的底部表面与FUSI层的底部表面对准，其中多晶硅层与FUSI层相比具有较大厚度。
在上述完全硅化栅控装置中，其中完全硅化层沿成角界面接触多晶硅层，使得完全硅化层的宽度随着距衬底的距离增加而增加。
在上述完全硅化栅控装置中，其中第一介电层为栅极氧化物，以及金属层包括氮化钛，以及完全硅化层的厚度范围为150埃至300埃。
在上述完全硅化栅控装置中，更包括：第一源极/漏极区以及第二源极/漏极区，设置于完全硅化层的相对侧上，其中第一源极/漏极区以及第二源极/漏极区包括P型掺质。
在上述完全硅化栅控装置中，其中多晶硅层的厚度比完全硅化层的厚度大至少10％。
以上概述若干实施例的特征，以使本领域的技术人员可更好地理解本公开的各方面。本领域的技术人员应了解，其可轻易地使用本公开作为设计或修改其它工艺和结构的基础，以实现本文所介绍的实施例的相同目的和/或达到相同优点。本领域的技术人员还应认识到，此类等效构造并不脱离本公开的精神及范围，且本领域的技术人员可在不脱离本公开的精神和范围的情况下对本文进行各种改变、置换以及变更。

Claims (10)

1.一种形成完全硅化栅控装置的方法，其特征在于，所述方法包括：
(i)在衬底上方的栅极结构上形成掩模层，所述栅极结构包括多晶硅层；
(ii)在所述栅极结构的相对侧上的所述衬底内形成第一源极区以及第一漏极区；
(iii)执行第一移除工艺，以移除所述掩模层的一部分，并暴露出所述多晶硅层的上部表面；
(iv)形成导电层，所述导电层与所述多晶硅层的所述上部表面直接接触；以及
(v)将所述导电层及所述多晶硅层转换成完全硅化层。
2.根据权利要求1所述的形成完全硅化栅控装置的方法，其中所述栅极结构更包括与所述衬底接触的第一介电层、上覆于所述第一介电层的高介电常数介电层以及设置于所述多晶硅层与所述高介电常数介电层之间的金属层。
3.根据权利要求1所述的形成完全硅化栅控装置的方法，
其中在所述第一移除工艺之后，所述多晶硅层包括中心区、第一外部区以及第二外部区，所述中心区被横向包夹在所述第一外部区与所述第二外部区之间，且所述中心区的高度小于所述第一外部区的高度及所述第二外部区的高度；
其中在将所述导电层以及所述多晶硅层转换成所述完全硅化层之前，所述掩模层存在于所述第一外部区以及所述第二外部区上方且不存在于所述中心区上方；以及
其中在将所述导电层以及所述多晶硅层转换成所述完全硅化层之后，所述中心区中整个厚度的所述多晶硅层被完全硅化且转换为所述完全硅化层。
4.根据权利要求1所述的形成完全硅化栅控装置的方法，更包括：
在所述第一移除工艺之前，在所述掩模层上方形成第二介电层，其中所述第二介电层完全覆盖位于所述多晶硅层的上部表面正上方的所述掩模层的上部表面。
5.根据权利要求4所述的形成完全硅化栅控装置的方法，更包括：
在所述第一移除工艺之前，执行第一平坦化工艺，以移除部分的所述掩模层以及所述第二介电层。
6.一种形成完全硅化栅控装置的方法，其特征在于，所述方法包括：
在包括多晶硅层的栅极结构上方形成第一掩模层，其中所述第一掩模层包括分别定义开口的两组侧壁；
根据所述第一掩模层选择性地蚀刻所述多晶硅层，以移除位于所述开口正下方的部分所述栅极结构；
在所述开口下方的衬底内形成第一源极/漏极区以及第二源极/漏极区；
在所述第一掩模层上方形成介电层，其中所述介电层填充所述开口；
执行平坦化工艺，以移除部分的所述第一掩模层以及所述介电层；
执行第一蚀刻，以根据位于所述第一掩模层上方且覆盖所述开口的第二掩模层来选择性地移除部分的所述第一掩模层以及所述多晶硅层；
在所述多晶硅层上方形成导电层；以及
执行退火工艺，以将所述导电层以及所述多晶硅层转换成硅化物层。
7.根据权利要求6所述的形成完全硅化栅控装置的方法，
其中在所述第一蚀刻之后，所述多晶硅层包括中心区、第一外部区以及第二外部区，所述中心区被横向包夹在所述第一外部区与所述第二外部区之间且居中于所述栅极结构的中线；
其中在所述退火工艺之前，所述第一掩模层存在于所述第一外部区以及所述第二外部区上方且不存在于所述中心区上方；以及
其中在所述退火工艺之后，所述中心区中的整个厚度的所述多晶硅层被完全硅化且转换为所述硅化物层。
8.根据权利要求7所述的形成完全硅化栅控装置的方法，
其中所述栅极结构更包括与所述衬底接触的栅极介电层、上覆于所述栅极介电层的高介电常数介电层，以及设置于所述多晶硅层与所述高介电常数介电层之间的氮化钛层；以及
其中所述第一源极/漏极区以及所述第二源极/漏极区包括P型掺质。
9.一种完全硅化栅控装置，其特征在于，包括：
第一介电层，位于衬底上方；
高介电常数介电层，上覆于所述第一介电层；
金属层，上覆于所述高介电常数介电层；
完全硅化层，上覆于所述金属层；以及
多晶硅层，与所述完全硅化层的相对侧接触，其中所述多晶硅层的底部表面以及所述完全硅化层的底部表面与所述金属层接触，以及其中所述多晶硅层的厚度大于所述完全硅化层的厚度。
10.根据权利要求9所述的完全硅化栅控装置，其中所述完全硅化层沿成角界面接触所述多晶硅层，使得所述完全硅化层的宽度随着距所述衬底的距离增加而增加。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11133226B2 (en) * 2018-10-22 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. FUSI gated device formation

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6063680A (en) * 1998-02-19 2000-05-16 Texas Instruments - Acer Incorporated MOSFETS with a recessed self-aligned silicide contact and an extended source/drain junction
US20040175876A1 (en) * 2003-03-03 2004-09-09 Fang-Yu Yeh [semiconductor device and manufacturing method thereof]
US20060148181A1 (en) * 2004-12-31 2006-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Strained channel CMOS device with fully silicided gate electrode
US20090053883A1 (en) * 2007-08-24 2009-02-26 Texas Instruments Incorporated Method of setting a work function of a fully silicided semiconductor device, and related device
US20090218640A1 (en) * 2008-02-29 2009-09-03 Roland Hampp Self Aligned Silicided Contacts
CN107452785A (zh) * 2016-06-01 2017-12-08 台湾积体电路制造股份有限公司 高压晶体管装置

Family Cites Families (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358879A (en) * 1993-04-30 1994-10-25 Loral Federal Systems Company Method of making gate overlapped lightly doped drain for buried channel devices
JP2606143B2 (ja) * 1994-07-22 1997-04-30 日本電気株式会社 半導体装置及びその製造方法
US6111319A (en) * 1995-12-19 2000-08-29 Stmicroelectronics, Inc. Method of forming submicron contacts and vias in an integrated circuit
US5714414A (en) * 1996-08-19 1998-02-03 Micron Technology, Inc. Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate
US6165880A (en) * 1998-06-15 2000-12-26 Taiwan Semiconductor Manufacturing Company Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
US6051470A (en) * 1999-01-15 2000-04-18 Advanced Micro Devices, Inc. Dual-gate MOSFET with channel potential engineering
US6312995B1 (en) * 1999-03-08 2001-11-06 Advanced Micro Devices, Inc. MOS transistor with assisted-gates and ultra-shallow “Psuedo” source and drain extensions for ultra-large-scale integration
US6177317B1 (en) * 1999-04-14 2001-01-23 Macronix International Co., Ltd. Method of making nonvolatile memory devices having reduced resistance diffusion regions
US6069032A (en) * 1999-08-17 2000-05-30 United Silicon Incorporated Salicide process
US6544844B2 (en) * 1999-10-08 2003-04-08 Macronix International Co., Ltd. Method for forming a flash memory cell having contoured floating gate surface
US6774429B2 (en) * 2000-08-10 2004-08-10 Matsushita Electric Industrial Co., Ltd. Hybrid semiconductor device with a poly-metal gate structure
TW533539B (en) * 2002-06-13 2003-05-21 Intelligent Sources Dev Corp A scaled MOSFET device and its fabricating method
US6713393B2 (en) * 2002-06-20 2004-03-30 Intelligent Sources Development Corp. Method of forming a nanometer-gate MOSFET device
US6894353B2 (en) * 2002-07-31 2005-05-17 Freescale Semiconductor, Inc. Capped dual metal gate transistors for CMOS process and method for making the same
KR100456699B1 (ko) * 2002-10-04 2004-11-10 삼성전자주식회사 하부 막질에 대한 하부 전극의 접촉 구조 및 그 형성 방법
KR100480636B1 (ko) * 2002-11-22 2005-03-31 삼성전자주식회사 반도체 장치의 제조방법
US7067379B2 (en) * 2004-01-08 2006-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide gate transistors and method of manufacture
US7285829B2 (en) * 2004-03-31 2007-10-23 Intel Corporation Semiconductor device having a laterally modulated gate workfunction and method of fabrication
US7279735B1 (en) * 2004-05-05 2007-10-09 Spansion Llc Flash memory device
US7498641B2 (en) * 2004-05-28 2009-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Partial replacement silicide gate
US7582931B2 (en) 2004-06-04 2009-09-01 Samsung Electronics Co., Ltd. Recessed gate electrodes having covered layer interfaces and methods of forming the same
US7018901B1 (en) * 2004-09-29 2006-03-28 Freescale Semiconductor, Inc. Method for forming a semiconductor device having a strained channel and a heterojunction source/drain
JP4440080B2 (ja) * 2004-11-12 2010-03-24 株式会社東芝 半導体装置およびその製造方法
US7538351B2 (en) * 2005-03-23 2009-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an SOI structure with improved carrier mobility and ESD protection
KR100724563B1 (ko) * 2005-04-29 2007-06-04 삼성전자주식회사 다중 일함수 금속 질화물 게이트 전극을 갖는 모스트랜지스터들, 이를 채택하는 씨모스 집적회로 소자들 및그 제조방법들
US20060255405A1 (en) * 2005-05-12 2006-11-16 National Chiao Tung University Fully-depleted SOI MOSFET device and process for fabricating the same
US20060273410A1 (en) * 2005-06-07 2006-12-07 National University Of Singapore Thermally stable fully silicided Hf silicide metal gate electrode
JP2006344836A (ja) * 2005-06-09 2006-12-21 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2007059691A (ja) * 2005-08-25 2007-03-08 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体装置
JP2007081249A (ja) * 2005-09-15 2007-03-29 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US20090302390A1 (en) * 2005-09-15 2009-12-10 Nxp B.V. Method of manufacturing semiconductor device with different metallic gates
JP2007103694A (ja) * 2005-10-05 2007-04-19 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
CN1945852A (zh) * 2005-10-06 2007-04-11 松下电器产业株式会社 半导体装置及其制造方法
JP4928890B2 (ja) * 2005-10-14 2012-05-09 株式会社東芝 不揮発性半導体記憶装置
JP2007123431A (ja) * 2005-10-26 2007-05-17 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2007123632A (ja) * 2005-10-28 2007-05-17 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US20090045469A1 (en) * 2005-11-28 2009-02-19 Kensuke Takahashi Semiconductor Device and Manufacturing Method Thereof
JP2007158220A (ja) * 2005-12-08 2007-06-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP2007242894A (ja) * 2006-03-08 2007-09-20 Toshiba Corp 半導体装置およびその製造方法
WO2007112779A1 (en) * 2006-04-03 2007-10-11 L'air Liquide Societe Anonyme A Directoire Et Conseil De Surveillance Pour L'etude Et L'exploitation Des Procedes Georges Claude Pentakis(dimethylamino) disilane precursor comprising compound and method for the preparation thereof
JP2008028107A (ja) * 2006-07-20 2008-02-07 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7893476B2 (en) * 2006-09-15 2011-02-22 Imec Tunnel effect transistors based on silicon nanowires
EP1900681B1 (en) * 2006-09-15 2017-03-15 Imec Tunnel Field-Effect Transistors based on silicon nanowires
US7374980B2 (en) * 2006-10-13 2008-05-20 International Business Machines Corporation Field effect transistor with thin gate electrode and method of fabricating same
JP2008140853A (ja) * 2006-11-30 2008-06-19 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2008159614A (ja) * 2006-12-20 2008-07-10 Toshiba Corp 不揮発性半導体メモリ
JP4861204B2 (ja) * 2007-01-22 2012-01-25 株式会社東芝 半導体装置およびその製造方法
US7439134B1 (en) * 2007-04-20 2008-10-21 Freescale Semiconductor, Inc. Method for process integration of non-volatile memory cell transistors with transistors of another type
JP2009004444A (ja) * 2007-06-19 2009-01-08 Panasonic Corp 半導体装置及びその製造方法
US20090001477A1 (en) * 2007-06-29 2009-01-01 Louis Lu-Chen Hsu Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures
US20090007037A1 (en) * 2007-06-29 2009-01-01 International Business Machines Corporation Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures
US8247861B2 (en) * 2007-07-18 2012-08-21 Infineon Technologies Ag Semiconductor device and method of making same
US7749822B2 (en) * 2007-10-09 2010-07-06 International Business Machines Corporation Method of forming a resistor and an FET from the metal portion of a MOSFET metal gate stack
JP2009130137A (ja) * 2007-11-22 2009-06-11 Toshiba Corp 半導体記憶装置及びその製造方法
EP2068351A1 (en) * 2007-12-03 2009-06-10 INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) Floating gate non-volatile memory device and method for manufacturing same
US7943997B2 (en) * 2008-04-17 2011-05-17 International Business Machines Corporation Fully-depleted low-body doping field effect transistor (FET) with reverse short channel effects (SCE) induced by self-aligned edge back-gate(s)
US20110049639A1 (en) * 2008-04-29 2011-03-03 Nxp B.V. Integrated circuit manufacturing method and integrated circuit
KR101079205B1 (ko) * 2008-08-22 2011-11-03 주식회사 하이닉스반도체 반도체 장치 및 그 제조 방법
US7943988B2 (en) * 2008-09-05 2011-05-17 Freescale Semiconductor, Inc. Power MOSFET with a gate structure of different material
JP2010080498A (ja) * 2008-09-24 2010-04-08 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US8012817B2 (en) * 2008-09-26 2011-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor performance improving method with metal gate
US8258587B2 (en) * 2008-10-06 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor performance with metal gate
KR101149044B1 (ko) * 2009-04-30 2012-05-24 에스케이하이닉스 주식회사 비휘발성 메모리 소자 및 그 제조 방법
US8193900B2 (en) * 2009-06-24 2012-06-05 United Microelectronics Corp. Method for fabricating metal gate and polysilicon resistor and related polysilicon resistor structure
US20110097867A1 (en) * 2009-10-22 2011-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of controlling gate thicknesses in forming fusi gates
US8530971B2 (en) * 2009-11-12 2013-09-10 International Business Machines Corporation Borderless contacts for semiconductor devices
JP5537130B2 (ja) * 2009-11-25 2014-07-02 株式会社東芝 半導体記憶装置
US20110248343A1 (en) * 2010-04-07 2011-10-13 International Business Machines Corporation Schottky FET With All Metal Gate
KR101676818B1 (ko) * 2010-05-19 2016-11-17 삼성전자주식회사 게이트 구조를 포함하는 반도체 소자들 및 그 제조 방법
US8349681B2 (en) * 2010-06-30 2013-01-08 Sandisk Technologies Inc. Ultrahigh density monolithic, three dimensional vertical NAND memory device
US8391068B2 (en) * 2010-12-20 2013-03-05 Texas Instruments Incorporated Adaptive programming for flash memories
US8697557B2 (en) * 2011-06-07 2014-04-15 Globalfoundries Inc. Method of removing gate cap materials while protecting active area
CN102227001B (zh) * 2011-06-23 2013-03-06 北京大学 一种锗基nmos器件及其制备方法
US9070784B2 (en) * 2011-07-22 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate structure of a CMOS semiconductor device and method of forming the same
JP5667961B2 (ja) * 2011-11-04 2015-02-12 株式会社東芝 半導体装置の製造方法
US20130140442A1 (en) * 2011-12-02 2013-06-06 Sony Corporation Amplifying circuit and manufacturing method, solid-state imaging element, and electronic device
CN103165601B (zh) * 2011-12-12 2015-12-09 中芯国际集成电路制造(北京)有限公司 集成半导体器件及其制造方法
JP2013182949A (ja) * 2012-02-29 2013-09-12 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US8569127B2 (en) * 2012-03-13 2013-10-29 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US8753931B2 (en) * 2012-04-05 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Cost-effective gate replacement process
US9159802B2 (en) * 2012-05-14 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with mask layers and methods for forming the same
JP2014011173A (ja) * 2012-06-27 2014-01-20 Toshiba Corp 半導体装置及びその製造方法
US9123577B2 (en) * 2012-12-12 2015-09-01 Sandisk Technologies Inc. Air gap isolation in non-volatile memory using sacrificial films
US8872285B2 (en) * 2013-03-01 2014-10-28 Globalfoundries Inc. Metal gate structure for semiconductor devices
US9236440B2 (en) * 2013-12-05 2016-01-12 Globalfoundries Inc. Sandwich silicidation for fully silicided gate formation
US9515155B2 (en) * 2013-12-20 2016-12-06 Globalfoundries Inc. E-fuse design for high-K metal-gate technology
US9349734B2 (en) * 2014-09-03 2016-05-24 Globalfoundries Inc. Selective FuSi gate formation in gate first CMOS technologies
US9666590B2 (en) * 2014-09-24 2017-05-30 Sandisk Technologies Llc High stack 3D memory and method of making
US9472642B2 (en) * 2014-12-09 2016-10-18 Globalfoundries Inc. Method of forming a semiconductor device structure and such a semiconductor device structure
US9954067B2 (en) * 2015-02-26 2018-04-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US10134641B2 (en) * 2015-05-21 2018-11-20 CoolStar Technology, Inc. Enhanced integration of DMOS and CMOS semiconductor devices
US9570568B2 (en) * 2015-05-28 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor component and method for fabricating the same
US9780193B2 (en) * 2015-10-27 2017-10-03 United Microelectronics Corporation Device with reinforced metal gate spacer and method of fabricating
US10431670B2 (en) * 2016-12-15 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd Source and drain formation technique for fin-like field effect transistor
US10056481B2 (en) * 2017-01-13 2018-08-21 Globalfoundries Inc. Semiconductor device structure
CN109494222B (zh) * 2017-09-13 2020-10-09 联华电子股份有限公司 半导体存储装置
US10340357B2 (en) * 2017-09-25 2019-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Dishing prevention dummy structures for semiconductor devices
US10510685B2 (en) * 2017-09-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Dishing prevention columns for bipolar junction transistors
US11133226B2 (en) * 2018-10-22 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. FUSI gated device formation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6063680A (en) * 1998-02-19 2000-05-16 Texas Instruments - Acer Incorporated MOSFETS with a recessed self-aligned silicide contact and an extended source/drain junction
US20040175876A1 (en) * 2003-03-03 2004-09-09 Fang-Yu Yeh [semiconductor device and manufacturing method thereof]
US20060148181A1 (en) * 2004-12-31 2006-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Strained channel CMOS device with fully silicided gate electrode
US20090053883A1 (en) * 2007-08-24 2009-02-26 Texas Instruments Incorporated Method of setting a work function of a fully silicided semiconductor device, and related device
US20090218640A1 (en) * 2008-02-29 2009-09-03 Roland Hampp Self Aligned Silicided Contacts
CN107452785A (zh) * 2016-06-01 2017-12-08 台湾积体电路制造股份有限公司 高压晶体管装置

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