JP2019046875A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2019046875A JP2019046875A JP2017165990A JP2017165990A JP2019046875A JP 2019046875 A JP2019046875 A JP 2019046875A JP 2017165990 A JP2017165990 A JP 2017165990A JP 2017165990 A JP2017165990 A JP 2017165990A JP 2019046875 A JP2019046875 A JP 2019046875A
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Abstract
【解決手段】LDMOSのソース領域側の半導体基板SBには、チャネル領域CHと、チャネル領域CHよりも低い不純物濃度を有するウェル領域HPWとが形成されている。ここで、チャネル領域CHの一部は、ゲート電極G1と平面視で重なるように形成されている。また、LDMOSのゲート長方向において、チャネル領域CH内のウェル領域HPWの端部は、ゲート電極G1から遠ざかるように、LDMOSのソース領域側のゲート電極G1の端部から離れている。
【選択図】図12
Description
図1は、本実施の形態の半導体装置の大まかなレイアウトを示す回路ブロック図である。
図14および図15は、本願発明者がゲート電極G1とウェル領域HPWとの位置関係を検討した際に得られたデータである。これら図14および図15と、図12のLDMOSに図示した長さLaとを用いて、本願発明者の検討結果を以下に記す。
次に、図17、図18および図19を用いて、ユニットセルUCの終端部TCの構造を説明する。前述したように、図17のB−B線は、終端部TCのLDMOSのゲート長方向の断面を示しており、図18の断面図に対応している。図17のC−C線は、活性部ACおよび終端部TCのLDMOSのゲート幅方向の断面を示しており、図19の断面図に対応している。なお、図18および図19の断面図では、LDMOSが形成される領域1Aのみを示している。
図20および図21を用いて、実施の形態1の変形例の半導体装置とその製造方法を説明する。なお、図20および図21の断面図では、LDMOSが形成される領域1Aのみを示している。
AC 活性部
BG 拡散層(半導体領域)
C1〜C3 回路ブロック
CH チャネル領域
CP1、CP2 キャップ膜
D1、D2 拡散層(半導体領域)
EX エクステンション領域(半導体領域)
FG1、FG2 導電性膜
G1、G2 ゲート電極
GI1、GI2 ゲート絶縁膜
La 長さ
Lb 長さ
LOC 絶縁膜
HNW ウェル領域(不純物領域)
HPW ウェル領域(不純物領域)
IF1、IF2 絶縁膜
IL0,IL1 層間絶縁膜
M1 配線
NS 不純物領域(半導体領域)
NV ドリフト領域(半導体領域)
P1〜P4 ピーク位置
PG プラグ
RP1〜RP5 レジストパターン
S1、S2 拡散層(半導体領域)
SB 半導体基板
SL シリサイド膜
STI 素子分離部
SW サイドウォールスペーサ
TC 終端部
UC ユニットセル
Claims (19)
- 半導体基板上に形成された第1MISFETの第1ゲート絶縁膜と、
前記第1ゲート絶縁膜上に形成された前記第1MISFETの第1ゲート電極と、
前記第1MISFETのゲート長方向において、前記第1ゲート電極の一方の端部側の前記半導体基板に形成された第1導電型の第1ドレイン領域と、
前記第1MISFETのゲート長方向において、前記第1ゲート電極の他方の端部側の前記半導体基板に形成され、且つ、前記第1導電型と反対の導電型である第2導電型の第1ウェル領域と、
前記第1ウェル領域を含む前記半導体基板に形成され、且つ、前記第1ウェル領域よりも高い不純物濃度を有する前記第2導電型の第1チャネル領域と、
前記第1チャネル領域内に形成された前記第1導電型の第1ソース領域と、
を有し、
前記第1ウェル領域の深さは、前記第1チャネル領域の深さよりも深く、
前記第1チャネル領域の一部は、前記第1ゲート電極と平面視で重なるように形成されており、
前記第1MISFETのゲート長方向において、前記第1チャネル領域内の前記第1ウェル領域の端部は、前記第1ゲート電極から遠ざかるように、前記第1ゲート電極の他方の端部から離れている、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1チャネル領域内の前記第1ウェル領域の端部が、前記第1ゲート電極の他方の端部から離れている距離は、0.1μm以上であって0.2μm以下である、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1MISFETのゲート幅方向において、前記第1MISFETは、前記第1チャネル領域内に前記第1ソース領域が形成されている活性部と、前記第1チャネル領域内に前記第1ソース領域が形成されていない終端部とを有し、
前記終端部の前記第1ウェル領域は、前記第1ゲート電極と平面視で重なるように形成されており、
前記第1チャネル領域の一部は、前記第1MISFETのゲート長方向およびゲート幅方向において、平面視で前記第1ウェル領域の内側に形成されている、半導体装置。 - 請求項3に記載の半導体装置において、
前記第1ドレイン領域は、前記第1導電型の第2ウェル領域と、前記第2ウェル領域内に形成され、前記第2ウェル領域よりも高い不純物を有し、且つ、前記第1導電型を有する第1拡散層とを有し、
前記終端部の前記第1ウェル領域は、前記第2ウェル領域と直接接しないように離れている、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1ウェル領域は、前記第1チャネル領域内に形成された上部と、前記第1チャネル領域よりも深い位置に形成された下部とを有し、
前記第1MISFETのゲート長方向において、前記第1ウェル領域の下部は、前記第1ウェル領域の上部よりも、前記第1ゲート電極の一方の端部側に近い場所に位置している、半導体装置。 - 請求項5に記載の半導体装置において、
前記第1ウェル領域の上部は、前記第1ゲート電極と平面視で重なっておらず、
前記第1ウェル領域の下部は、前記第1ゲート電極と平面視で重なっている、半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体基板上に、前記第1ゲート絶縁膜よりも厚い膜厚を有する第1絶縁膜が形成されており、
前記第1ゲート電極の一方の端部は、前記第1絶縁膜上に位置している、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1導電型はn型であり、
前記第2導電型はp型である、半導体装置。 - (a)第1導電型の半導体基板に、前記第1導電型と反対の導電型である第2導電型の第1ウェル領域を形成する工程、
(b)前記半導体基板上に、第1MISFETの第1ゲート絶縁膜を形成する工程、
(c)前記第1ゲート絶縁膜上に、第1導電性膜を形成する工程、
(d)前記第1MISFETの第1ドレイン領域側が開口されるように、前記第1導電性膜を選択的に除去することで、第2導電性膜を形成する工程、
(e)前記第2導電性膜上に、第1レジストパターンを形成する工程、
(f)前記(e)工程後、前記第1レジストパターンをマスクとして、前記第1MISFETの第1ソース領域側が開口されるように、前記第2導電性膜を選択的に除去することで、前記第1MISFETの第1ゲート電極を形成する工程、
(g)前記(f)工程後、前記第1レジストパターンが存在する状態でイオン注入を行うことで、前記第1ウェル領域が形成されている前記半導体基板に、前記第1ウェル領域よりも高い不純物濃度を有する前記第2導電型の第1チャネル領域を形成する工程、
を有し、
前記第1ウェル領域の深さは、前記第1チャネル領域の深さよりも深く、
前記第1チャネル領域の一部は、前記第1ゲート電極と平面視で重なる位置まで形成されており、
前記第1MISFETのゲート長方向において、前記第1チャネル領域内の前記第1ウェル領域の端部は、前記第1ゲート電極から遠ざかるように、前記第1ソース領域側の前記第1ゲート電極の端部から離れている、半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、更に、
(h)前記(g)工程後、前記第1レジストパターンを除去する工程、
(i)前記(h)工程後、前記第1ゲート電極上に、前記第1チャネル領域を開口する第2レジストパターンを形成する工程、
(j)前記第2レジストパターンがある状態で、イオン注入を行うことで、前記第1チャネル領域内に、前記第2導電型であり、且つ、前記第1ソース領域の一部となる不純物領域を形成する工程、
(k)前記(j)工程後、前記第2レジストパターンを除去する工程、
を有し、
前記(g)工程で行われるイオン注入は、前記半導体基板に対する垂線から傾けた第1角度で行われ、
前記(j)工程で行われるイオン注入は、前記半導体基板に対して垂直な角度で行われるか、または、前記半導体基板に対する垂線から傾けた第2角度であって、且つ、前記第1角度よりも小さい前記第2角度で行われる、半導体装置の製造方法。 - 請求項10に記載の半導体装置の製造方法において、
前記(e)工程で形成される前記第1レジストパターンの厚さは、前記(i)工程で形成される前記第2レジストパターンの厚さよりも厚い、半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、
前記(e)工程で形成される前記第1レジストパターンの厚さは、前記第2導電性膜の厚さの4倍以上である、半導体装置の製造方法。 - 請求項12に記載の半導体装置の製造方法において、
前記(g)工程での前記第1レジストパターンの厚さは、前記第1ゲート電極の厚さの2倍以上である、半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、
前記(a)工程における前記第1ウェル領域形成工程は、
(a1)第1イオン注入によって、前記第1チャネル領域よりも深い位置の前記半導体基板に、前記第1ウェル領域の下部を形成する工程、
(a2)第2イオン注入によって、前記第1チャネル領域内に、前記第1ウェル領域の上部を形成する工程、
を有し、
前記第2イオン注入は、前記半導体基板に対する垂線から傾けた第1角度で行われ、
前記第1イオン注入は、前記半導体基板に対して垂直な角度で行われるか、または、前記半導体基板に対する垂線から傾けた第2角度であって、且つ、前記第1角度よりも小さい前記第2角度で行われる、半導体装置の製造方法。 - 請求項14に記載の半導体装置の製造方法において、
前記第1MISFETのゲート長方向において、前記第1ウェル領域の下部は、前記第1ウェル領域の上部よりも、前記第1ドレイン領域側の前記第1ゲート電極の端部に近い場所に位置している、半導体装置の製造方法。 - 請求項15に記載の半導体装置の製造方法において、
前記第1ウェル領域の上部は、前記第1ゲート電極と平面視で重なっておらず、
前記第1ウェル領域の下部は、前記第1ゲート電極と平面視で重なっている、半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、
前記第1MISFETは、前記半導体基板の第1領域に形成されており、
前記第1領域とは別の前記半導体基板の第2領域には、第2MISFETが形成されており、
前記(a)工程では、前記第2領域の前記半導体基板に、前記第2導電型を有する第2ウェル領域が形成され、
前記(c)工程では、前記第2ウェル領域上にも前記第1導電性膜が形成され、
前記(d)工程では、第2MISFETの第2ドレイン領域側および第2ソース領域側が開口されるように、前記第2領域の前記第1導電性膜を選択的に除去することで、前記第2MISFETの第2ゲート電極が形成される、半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、
前記第1導電型はn型であり、
前記第2導電型はp型である、半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、
前記第1MISFETは、前記第1MISFETのゲート幅方向において、前記第1チャネル領域内に前記第1ソース領域が形成されている活性部と、前記第1MISFETのゲート幅方向において、前記第1チャネル領域内に前記第1ソース領域が形成されていない終端部とを有し、
前記終端部の前記第1ウェル領域は、前記第1ゲート電極と平面視で重なるように形成されており、
前記第1チャネル領域の一部は、前記第1MISFETのゲート長方向およびゲート幅方向において、平面視で前記第1ウェル領域の内側に形成されている、半導体装置の製造方法。
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