CN110970358B - 堆叠半导体器件及其制造方法 - Google Patents

堆叠半导体器件及其制造方法 Download PDF

Info

Publication number
CN110970358B
CN110970358B CN201910927994.4A CN201910927994A CN110970358B CN 110970358 B CN110970358 B CN 110970358B CN 201910927994 A CN201910927994 A CN 201910927994A CN 110970358 B CN110970358 B CN 110970358B
Authority
CN
China
Prior art keywords
device layer
substrate
sidewall
layer
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910927994.4A
Other languages
English (en)
Other versions
CN110970358A (zh
Inventor
吕宗兴
何军
朱立寰
曹佩华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN110970358A publication Critical patent/CN110970358A/zh
Application granted granted Critical
Publication of CN110970358B publication Critical patent/CN110970358B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05681—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/0807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08121—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the connected bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8122—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/8123—Polychromatic or infrared lamp heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface

Abstract

方法包括提供第一和第二晶圆；在第一晶圆的顶部中形成第一器件层；在第二晶圆的顶部中形成第二器件层；在第一器件层中形成第一凹槽；在第二器件层中形成第二凹槽；在形成第一凹槽和第二凹槽中的至少一个之后，将第一晶圆和第二晶圆接合在一起；以及通过切割工艺切割接合的第一晶圆和第二晶圆，其中切割工艺切割穿过第一凹槽和第二凹槽。本发明的实施例还涉及堆叠半导体器件及其制造方法。

Description

堆叠半导体器件及其制造方法
技术领域
本发明的实施例涉及堆叠半导体器件及其制造方法。
背景技术
集成电路(IC)行业经历了指数式增长。IC材料和设计的技术进步已产生了多代IC，其中每一代都具有比上一代更小和更复杂的电路。在IC演化过程中，功能密度(即，每个芯片区域的互连器件的数量)通常增加，而几何尺寸(即，可以使用制造工艺创建的最小组件(或线))减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。
随着半导体技术的进一步发展，例如3D集成电路(3D-IC)的堆叠半导体器件已经作为进一步减小半导体器件的物理尺寸的有效替代出现。在堆叠半导体器件中，晶圆/管芯彼此堆叠并且使用诸如衬底通孔(TSV)的连接件互连。例如，3D-IC的一些优点包括占用空间更小，通过降低信号互连件的长度来降低功耗，以及改进良率和制造成本(如果在组装之前单独测试单独的管芯)。然而，对堆叠的半导体结构进行切割具有挑战性。切割是一种将含芯片的半导体结构(例如晶圆上晶圆结构)切成单独的管芯的工艺。机械切割(例如使用锯片或锯片)或激光切割已在工业中用于分割管芯。如果仅依靠机械切割，则机械切割期间的热应力和机械应力可能会导致衬底晶格畸变并在包含电路的层中产生裂纹，这被称为硅剥离。仅依靠激光切割时，激光辐照可能会产生硅屑，引起切割的侧壁的污染。因此，需要一种在实质上不引起硅剥离和硅屑的情况下切割堆叠半导体器件的方法。
发明内容
本发明的实施例提供了一种制造堆叠半导体器件的方法，包括：提供第一晶圆和第二晶圆；在所述第一晶圆的顶部中形成第一器件层；在所述第二晶圆的顶部中形成第二器件层；在所述第一器件层中形成第一凹槽；在所述第二器件层中形成第二凹槽；在形成所述第一凹槽和所述第二凹槽中的至少一个之后，将所述第一晶圆和所述第二晶圆接合在一起；以及通过切割工艺切割接合的第一晶圆和第二晶圆，其中，所述切割工艺切割穿过所述第一凹槽和所述第二凹槽。
本发明的另一实施例提供了一种制造堆叠半导体器件的方法，包括：提供第一结构，所述第一结构具有第一衬底和位于所述第一衬底上的第一器件层；提供第二结构，所述第二结构具有第二衬底和位于所述第二衬底上的第二器件层；在所述第二器件层中形成第二凹槽；将所述第一衬底的底面接合至所述第二器件层的顶面；在所述接合之后，在所述第一器件层中形成第一凹槽；以及依次切割穿过所述第一凹槽、所述第一衬底、所述第二凹槽和所述第二衬底。
本发明的又一实施例提供了一种堆叠半导体器件，包括：第一衬底，具有第一侧壁；第一器件层，位于所述第一衬底上，具有第二侧壁，其中，所述第二侧壁的表面粗糙度大于所述第一侧壁的表面粗糙度；以及材料层，接合至所述第一器件层，其中，所述第一器件层包括第一导电部件，所述第一导电部件电连接到所述材料层中的第二导电部件。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A、图1B和图1C示出了根据本发明的各个方面的用于制造堆叠半导体器件的示例性方法的流程图。
图2、图3、图4、图5、图6、图7、图8A、图9、图10、图11、图12、图13、图14、图15、图16、图17、图18、图19、图20、图21和图22是根据本发明的各个方面的示例性器件的截面图。
图8B和图8C示出了根据本发明的各个方面的图8A中的示例性堆叠半导体器件的边缘的斜率和表面粗糙度的特性。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然这些仅是实例而不旨在限制。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。
此外，本发明可以在各个示例中重复参考数字和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。此外，在本发明中的另一部件上形成连接到和/或耦合到另一部件的部件可以包括形成直接接触的部件的实施例，并且还可以包括其中可形成插入部件之间的附加特征的实施例，使得部件不直接接触。此外，空间相对术语，例如“下部”、“上部”、“水平”、“垂直”、“之上”、“上方”、“下方”、“之下”、“向上”、“向下”、“顶部”、“底部”等及其派生词(例如“水平地”、“向下地”、“向上地”等)便于本发明用于描述一个部件与另一个部件之间的关系。空间相对术语旨在涵盖包括这些部件的器件的不同方向。此外，当用“约”、“近似”等的数值或数值范围时，除非另有说明，否则该术语旨在涵盖在所述数量的+/-10％之内的数量。例如，术语“约5nm”包括从4.5nm至5.5nm的尺寸范围。
在完成堆叠半导体制造之后，接合工艺将第一晶圆物理地接合至第二晶圆，从而产生晶圆上晶圆结构。晶圆上晶圆结构包括由划线沟道分隔开的大量重复的半导体器件。各种各样的技术被用来沿着划线沟道将处理的晶圆划分成单独的小片，每个管芯代表一个特定的半导体芯片。当今工业上流行的晶圆切割技术包括机械切割和激光切割。
机械切割采用锯切工艺，诸如使用金刚石刀片或金刚石锯片。在机械切割期间，划线沟道被完全切割穿过以分割小片。可选地，在机械切割(例如，预开裂工艺)期间基本切割穿过划线沟道，然后沿着预开裂的划线沟道进行机械切割，以分割小片。切割工艺会沿着小片的边缘留下微裂纹。这些裂纹容易通过不可预期的裂纹路径在晶圆上传播，也称为硅剥离，这可能会导致严重的器件损坏并导致器件良率损失。对于具有微型芯片尺寸的器件的晶圆，良率损失可能会变得越来越严重。伴随锯切操作的振动、剪切和冲击的影响可能会加剧裂纹并造成更多的器件损坏和良率损失。此外，锯片或刀片的物理尺寸限制了晶圆上的划线沟道的进一步缩小，这抑制了晶圆上的划线沟道尺寸按比例缩小以及在先进的加工技术中为功能性半导体器件提供最大可能的晶圆面积的普遍趋势。
另一方面，激光切割在划线沟道上采用高能激光束或脉冲撞击，破坏晶圆晶体材料的微结构并形成切割切口。当使用激光切割时，晶圆表面上的高能激光的撞击可能会在周围环境中产生大量晶圆材料颗粒，也称为硅屑。这些颗粒可能会再沉积回晶圆上并造成严重的颗粒污染。另外，由于晶圆晶体材料的局部高温，电子束也可能引起微裂纹。
本发明涉及切割半导体器件的方法，并且更具体地涉及利用混合切割工艺对堆叠半导体器件(诸如晶圆上晶圆结构)进行切割的方法。在一些实施例中，混合切割工艺包括接合之前的激光切槽和随后的机械切割。激光切槽基本上限于器件层，而没有进一步深入到硅衬底中，因为器件层主要包含介电材料和金属迹线，在激光切槽期间产生的硅屑较少。同时，机械切割限于硅衬底而不锯切器件层，从而防止了微裂纹从硅衬底传播到器件层中。因此，混合切割工艺将显著减少切割堆叠半导体器件期间的不利影响，诸如与传统晶圆切割方法相关联的微裂纹和硅屑的再沉积。因此，混合切割工艺将减少切割相关的器件损坏并提高产品良率。在讨论如图1A至图22所示的本发明的各个实施例之后，这些和其他益处将变得明显。
图1A、图1B和图1C示出了根据一些实施例的用于对堆叠半导体器件(诸如晶圆上晶圆结构)进行切割的方法10的流程图。方法10仅是示例，并且不是意图将本发明限制在权利要求书中未明确限定的范围之外。可以在方法10之前、期间和之后提供附加操作，并且对于该方法的其他实施例，可以替换、消除或移动所描述的一些操作。下面结合图2至图22描述方法10。图2至图22示出了在根据方法10的制造步骤期间的堆叠半导体器件的各种截面图和相关的边缘轮廓。
在操作12中，方法10(图1A)提供或提供有第一器件100(图2)。在实施例中，第一器件100是晶圆，诸如掺硼硅晶圆，具有约300μm至约800μm的厚度以及约100、125、150、200mm或更大的直径。第一器件100包括衬底102和形成在衬底102顶部上的器件层104。衬底102可以是半导体衬底，诸如硅或陶瓷衬底。可选地或另外地，半导体衬底包括：元素半导体，包括锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP或它们的组合。此外，衬底102也可以是绝缘体上半导体(SOI)。
在一些实施例中，外延生长器件层104，然后进行各种操作以形成例如半导体器件的有源区或感测区。器件层104的厚度T1可以在约1.5μm至约30μm或更厚的范围内。为了简化描述，器件层104示出为单层，但是实际上，器件层104可以包括位于衬底102上方的有源层(有源器件形成在该有源层处)、耦合器件以形成功能电路并且位于保护钝化层上面的互连金属层。器件层104包括多个区域，该区域包括多个全芯片区域106和位于相邻对全芯片区域106之间的划线沟道区域108。每个全芯片区域106包括半导体IC，随后将沿着划线沟道区域108中的划线沟道切割半导体IC。在一些实施例中，半导体IC是光电感测IC，并且每个全芯片区域106包括光电感测区域。在一些实施例中，半导体IC包括逻辑电路，并且每个全芯片区域106还包括晶体管区域和金属化层。在一些实施例中，划线沟道区域108还包括电耦合至半导体IC的金属化层(未示出)，金属化层允许在切割之前检测芯片缺陷。
仍参考图2，器件层104包括设置在其中和/或其上的各种部件。例如，器件层104可以包括各种晶体管，诸如晶体管110。在各个实施例中，晶体管110可以是金属氧化物半导体场效应晶体管(MOSFET)(诸如CMOS晶体管)、鳍式场效应晶体管(FinFET)、双极结型晶体管(BJT)、高压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管(PFET/NFET)。
器件层104还包括耦合到晶体管110的多层互连件(MLI)114。MLI 114包括各种导电部件，导电部件可以是垂直互连件(诸如接触件和/或通孔)和/或水平互连件(诸如导线)。各种导电部件包括诸如金属的导电材料。在示例中，可以使用包括铝、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、金属硅化物或它们的组合的金属，并且各个导电部件可以称为铝互连件。可以通过包括物理气相沉积(PVD)、化学气相沉积(CVD)或它们的组合的工艺形成铝互连件。形成各个导电部件的其他制造技术可以包括光刻处理和蚀刻以图案化导电材料以形成垂直和水平连接件。可以采用其他制造工艺以形成MLI 114，诸如热退火以形成金属硅化物。多层互连件中使用的金属硅化物可以包括硅化镍、硅化钴、硅化钨、硅化钽、硅化钛、硅化铂、硅化铒、硅化钯或它们的组合。可选地，各个导电部件可以是铜多层互连件，包括铜、铜合金、钛、氮化钛、钽、氮化钽、钨、多晶硅、金属硅化物或它们的组合。铜互连件可以通过包括PVD、CVD或它们的组合的工艺来形成。MLI 114不受所描绘的导电部件的数量、材料、大小和/或尺寸的限制，因此，取决于器件层104的设计要求，MLI 114可以包括导电部件的任意数量、材料、大小和/或尺寸。在所示的实施例中，MLI 114还包括形成在器件层104的最上部分中的金属焊盘116。金属焊盘116的横向尺寸可以在约10μm至约200μm的数量级。
MLI 114的各种导电部件设置在层间(或层级间)介电(ILD)层中。ILD层可以包括二氧化硅、氮化硅、氮氧化硅、TEOS氧化物、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟化硅玻璃(FSG)、碳掺杂的氧化硅、非晶氟化碳、聚对二甲苯、BCB(双苯并环丁烯)、聚酰亚胺、其他合适的材料或它们的组合。ILD层可以具有多层结构。可以通过包括旋涂、CVD、溅射的工艺或其他合适的工艺来形成ILD层。在示例中，可以以包括镶嵌工艺(诸如双镶嵌工艺或单镶嵌工艺)的集成工艺形成MLI 114和ILD层。
在操作14中，方法10(图1A)提供或提供有第二器件200(图3)。除第一器件100之外，单独准备了第二器件200。在实施例中，第二器件200和第一器件100两者都是具有相同直径的晶圆。第二器件200的各种材料组分、有源区和无源区、互连金属层与以上参考图2中的第一器件100所讨论的相似，并且为了方便起见，下面将对其进行简要讨论。重复附图标记以便于理解。第二器件200包括衬底202和形成在衬底202的顶部上的器件层204。衬底202可以是半导体衬底，包括硅或其他合适的半导体材料。器件层204的厚度T2可以在约1.5μm至约30μm或更厚的范围内。器件层204包括多个区域，多个区域包括多个全芯片区域106和位于相邻对全芯片区域106之间的划线沟道区域108。每个全芯片区域106构成半导体IC，半导体IC将沿着划线沟道区域108中的划线沟道切割。全芯片区域106可以包括晶体管区域和金属化层(诸如MLI 114)，以将来自晶体管110的信号通过金属焊盘116路由到外部。
在操作16中，方法10(图1A)穿过第一器件100的器件层104并可选地穿入衬底102(图4)的上部中形成凹槽120。沿着与相邻对的半导体芯片之间的横向边界对应的划线沟道区域108形成凹槽120。在一些实施例中，操作16采用激光束或脉冲来形成凹槽，这也称为激光开槽工艺。在各个实施例中，激光器是固态激光器、钇铝石榴石(YAG)激光器、钕YAG激光器或其他合适的激光器。可选地，开槽工艺可以使用除激光器之外的其他合适的非机械切割方法，诸如等离子切割工艺。通过去除对整个芯片区域106有选择的划线沟道区域108的中心部分或全部，形成穿过器件层104的凹槽120。换句话说，划线沟道区域108为形成凹槽120提供足够的宽度而不去除全芯片区域106的部分。凹槽120的开口宽度W1可以在约5um至约100um或更宽的范围内。在一些实施例中，开口宽度W1在器件层104的厚度T1的约1.5到约10倍之间。在特定实施例中，凹槽120具有约55μm的开口宽度W1和约15μm的深度D1。凹槽120的底部可以停在衬底102的顶面处或可选地稍微延伸到衬底102中。因此，深度D1可以分为两部分，第一部分是器件层104的厚度T1，第二部分是延伸到衬底102的凹槽120的底部的深度。其中第一部分(T1)与第二部分(D1-T1)的比率可以在约5：1至约20：1的范围内，诸如约8：1。如果T1/(D1-T1)大于约20：1，这意味着延伸到衬底102中的凹槽120的底部可以是浅的，使得机械误差可能引起一些其他凹槽没有完全延伸穿过器件层104。如果T1/(D1-T1)小于约5∶1，这意味着凹槽120的底部可以延伸到衬底102太深，使得激光辐射可能产生太多硅屑。穿过器件层104的激光凹槽避免在随后的切割操作期间由于锯片的机械应力和热应力而损坏该层。激光凹槽基本上限于器件层104，这避免了由激光照射到衬底102中引起的硅屑污染。
在形成凹槽120之后，待切割的半导体IC(即，全芯片区域106)的边缘包括锥形侧壁124。锥形侧壁实质上包括一半的激光开槽轮廓(减去稍后将讨论的机械切割的切割宽度)。锥形侧壁124从器件层104的顶面延伸到衬底102的顶面或任选地在衬底102的顶面下方。锥形侧壁124可具有圆形或尖形底部。锥形侧壁124的不同位置处的斜率可能会有所不同。如图4所示，基准是测量位于凹槽深度的一半(D1/2)处的P点处的斜率。斜率定义为衬底102的顶面与通过点P的锥形侧壁124的切线之间形成的角度α的正切。在一些实施例中，角度α的范围是从约35°到约80°的范围内，诸如约45°。角度α被称为由相应的侧壁形成的角度。锥形侧壁124的表面粗糙度(以RMS测量)表示为R1。在特定示例中，R1可以在约20nm至约100nm的范围内。如下所示，激光开槽轮廓的表面粗糙度通常大于机械切割轮廓，诸如在一些实施例中至少约五倍。
在操作24中，方法10(图1A)形成穿过第二器件200的器件层204并可选地进入衬底202的上部的凹槽120(图5)。操作24的方面基本上类似于上文参考图4所讨论的操作16。在图5中重复附图标记以便于理解。类似地，器件层204中的凹槽120的深度D2可以等于或略大于器件层204的厚度T2。在深度D2的一半处的锥形侧壁124的角度α在约35°至约80°的范围内，诸如约45°。如果角度α小于35°，则开口宽度W1可以比划线沟道区域108可以提供的宽度宽。如果角度α大于80°，则开口宽度W1可能太窄，以至于机械小片工具(将在下面讨论)无法通过而不会碰到锥形侧壁124。
在操作32处，方法10(图1A)通过接合工艺将第一器件100物理连接到第二器件200以形成堆叠半导体器件。图6示出了接合工艺的一个实施例。在所示的实施例中，器件200被翻转并且器件层204直接面向器件100的器件层104。在实施例中，接合工艺是热压接合工艺，因此器件100和器件200放置在两个热板(未显示)之间，并且施加热量和力以物理接合这两个器件。在这种技术中，将两个器件加热到大于约150℃的温度，诸如约350℃，同时施加约1Mpa和约100Mpa之间的压力，诸如约20Mpa。在所示的实施例中，第一器件100的凹槽120(下部凹槽)直接位于第二器件200的凹槽120(上部凹槽)下方。未对准可能会导致上、下部凹槽的中心位置横向偏移。只要下部凹槽的一部分位于上部凹槽的一部分的正下方，则两个凹槽的空间关系仍称为“正下方”。在接合之后，一对上部凹槽和下部凹槽连接并形成较大的空隙，该空隙从上部凹槽连续地延伸到下部凹槽。
可选地，在接合工艺的实施例中，第一器件100的器件层104和第二器件200的器件层204对准并通过金属焊盘116接合在一起。接的金属焊盘116提供从第一器件层104到第二器件层204的信号路径。在实施例中，在待接合的金属焊盘116上的接合接触件之间施加接合介质，诸如铜、钨、铜锡合金、金锡合金、铟金合金、铅锡合金等。在进一步的实施例中，接合工艺可以是回流工艺。在这种工艺中，在金属焊盘116的位置处施加焊料，然后将器件100和200放置在两个热板之间，并且将温度升高到合适的温度，使得焊料将回流。该回流将外部导体接合在一起。在另一示例中，接合工艺可以是近红外(NIR)回流工艺。在这种工艺中，可以引导近红外辐射而不是直接加热，以使焊料回流并且接合外部导体。此外可以可选地利用热压接合、回流工艺、NIR回流工艺或任何其他合适的接合工艺。
在操作42中，方法10(图1A)使用除激光之外的其他切割技术(诸如机械切割)沿划线沟道区区域108进行切割，以将接合的半导体结构分为两个或多个小片300(图7)。在一些实施例中，机械切割采用锯片或刀片(未示出)以依次切割穿过衬底202、上部凹槽120、下部凹槽120和衬底102。在一些可选实施例中，锯片或刀片可不完全切割穿过衬底102，而是通过机械切割工艺将接合的半导体器件裂成小片。锯片或刀片可附接到壳体，该壳体保持驱动锯片或刀片固定到其上的转子的电机。在特定示例中，机械切割使用具有镍-金刚石切割表面的圆形刀片。
在机械切割期间以及在将小片300完全物理分离之前，机械切割工艺形成切割切口126，切割切口126在其朝向凹槽120的开口处测得的宽度W2小于凹槽120的开口的宽度W1。在一些实施例中，宽度W1是宽度W2的约两倍至约二十倍，诸如约五倍。在各个实施例中，机械切割形成直切口，使得切割切口126的侧壁128基本上是垂直的。在这里，“基本上垂直”是指在侧壁128和相应衬底的顶面之间形成的角度大于80°。
由于机械切割穿过凹槽120并且与器件层104和204没有实质的物理接触，所以切割期间的热应力和机械应力主要限制在衬底102和202中，这减轻了对器件层104和204的损坏。例如，硅剥离(如果有的话)不大可能传播到器件层104和204中，这降低了器件缺陷率。
参考图8A，示出了在结合了激光开槽和机械切割的混合切割工艺之后的切割的半导体IC 300。具体地，半导体IC 300包括第一器件100的衬底102和器件层104(包括晶体管和全芯片区域中的金属层)以及第二器件200的器件层204(包括晶体管和全芯片区域中的金属层)和衬底202。器件层104和204中的电路可以通过接合的金属焊盘116彼此电耦合。半导体IC 300的边缘包括基本垂直的上部侧壁128、上部锥形侧壁124、下部锥形侧壁124和基本垂直的下部侧壁128。在所示实施例中，侧壁124和128形成连续的侧壁轮廓。上部侧壁128和下部侧壁128中的每一个基本上包括一半的机械切割切口轮廓。上部和下部锥形侧壁124中的每个基本上包括激光开槽轮廓的一半(减去机械切割宽度的约一半)。上部和下部锥形侧壁124形成向半导体芯片300的中心弯曲的凹部130。凹部130的宽度D定义为从上部侧壁128和上部锥形侧壁124的相交点到下部侧壁128和下部锥形侧壁124的另一相交点的长度。凹部130的高度H定义为从器件层104和204的界面处的边缘点到以上定义的任何一个相交点的横向距离。凹部130的宽度D等于或略大于器件层104和204的厚度总和。在一些实施例中，宽度D的范围从约3um到约80um。凹部的高度H约是凹槽宽度W1的一半减去机械切割切口宽度W2的一半((W1-W2)/2)。在一些实施例中，高度H的范围是从1μm至约50μm。在一些实施例中，H/D的比率在约0.01至约20的范围内。在特定实施例中，凹部130具有约30μm的宽度D和约28μm的高度H。
图8B和图8C示出了半导体IC 300的边缘的特性。具体地，在图8B中，垂直轴表示边缘的斜率，水平轴z表示沿垂直方向从衬底102的底面的距离；在图8C中，垂直轴表示边缘的表面粗糙度，水平轴z表示沿垂直方向从衬底102的底面的距离。参考图8B，由于基本上垂直的侧壁128，衬底102和202中的斜率具有最大值S1。根据一些实施例，该斜率轮廓在器件层和衬底之间的界面处或附近具有拐点。该斜率在衬底102和202内基本上是平坦的，在界面处下降到接近零，然后增加到值S2，其中S2小于S1。在一些实施例中，S1对应于大于80°的角的正切，而S2对应于约35°和约80°之间的角的正切，诸如约45°。参考图8C，在一些实施例中，锥形侧壁124(覆盖器件层104和204的边缘以及可选地略微进入衬底102和202)的表面粗糙度R1(以RMS测量)大于机械切割轮廓的表面粗糙度。换句话说，由于机械切割而产生的侧壁128通常比由于激光开槽而产生的侧壁更光滑。在一些实施例中，侧壁128(覆盖衬底102和202的大部分或整个边缘)的表面粗糙度R2(以RMS测量)小于R1的约五分之一。
在某些情况下，接合期间的未对准可能导致第一器件100和第二器件200之间的横向偏移。如图9所示，成对的凹槽的锥形侧壁124可能由于横向偏移而中断，并且形成台阶轮廓。在器件层104和204之间的界面的一个边缘处的区域302中，器件层204的面向下的表面被暴露。在器件层104和204之间的界面的另一边缘处的区域304中，器件层104的面向上的表面被暴露。在一些实施例中，取决于横向偏移的距离，器件层104和204的任一表面可以暴露约0.1μm至约20μm。
在某些情况下，成对的凹槽可能具有不同的开口宽度，这也会在切割后的半导体IC 300的边缘处引起台阶轮廓。在图10中，切割之前的器件层104中的下部凹槽的开口小于器件层204中的上部凹槽。结果，在区域302和304中，器件层104的顶面都暴露，并且锥形侧壁124不连续并形成台阶轮廓。不同的凹槽开口宽度可能是由于在开槽期间的不同的激光强度或由于不同的器件层厚度引起，通常器件层越薄，凹槽越浅和窄。在半导体IC 300的任一边缘上，器件层104的顶面可能会暴露约0.1um至约20um
再次参考方法10(图1A)的操作32，接合工艺的又一可选实施例是将一个器件的衬底接合至另一器件的器件层，而无需翻转器件。如图11所示，在接合之前，第二器件200的衬底202的底面直接面向第一器件100的器件层104的顶面。器件100中的凹槽120直接在器件200中的相应的凹槽120下方，但是被凹槽之间的衬底202分隔开。在接合之前，第二器件200还可以具有形成在衬底202中的硅通孔(TSV)140，以将器件层204中的电路信号路由到衬底202的底面。可以通过蚀刻穿过衬底202的垂直孔并用诸如铜的导电材料填充该孔来形成TSV140。也可以通过合适的方法(诸如单镶嵌工艺或双镶嵌工艺)在衬底202的最底部处形成金属焊盘116。接合工艺可以基本上类似于以上结合图6所讨论的方法。热压接合、回流工艺或NIR回流工艺或其他合适的接合工艺可以用于物理地连接第一器件和第二器件。在接合之后，器件层204中的电路通过TSV 140和接合的金属焊盘116电耦合至器件层104中的电路。
返回到操作42，方法10(图1A)使用除激光之外的切割技术(诸如机械切割方法)沿着划线沟道区域108进行切割，以将接合的半导体结构分为两个或多个小片300(图12)。在各个实施例中，机械切割基本上类似于以上结合图7所讨论的切割。区别之一是在机械切割中使用锯片或刀片依次切割穿过上部凹槽120、衬底202、下部凹槽120和衬底102。衬底202中的切割切口126连接上部凹槽120和下部凹槽120。
在图13中示出了在结合了激光开槽和机械切割的混合切割工艺之后的接合的可选实施例的切割的半导体IC 300。半导体IC 300的边缘包括五个段，即依次为上部锥形侧壁124、来自机械切割穿过衬底202的上部侧壁128、衬底202的底面、下部锥形侧壁124和来自机械切割穿过衬底102的下部侧壁128。由于机械切割的侧壁128通常比由于激光开槽的锥形侧壁124光滑。在各个实施例中，锥形侧壁124的表面粗糙度(以RMS测量)至少是侧壁128的表面粗糙度的五倍。在一些实施例中，参考半导体IC 300的底面，侧壁128形成大于80°的角度，并且锥形侧壁124形成在约35°与约80°之间的角度，诸如约45°。
参考图1B，在方法10的一些其他实施例中，将第一和第二器件接合在一起的操作32可以在第二器件层中形成凹槽的操作24之前。如图14所示，在第一器件100的划线沟道区域108中形成凹槽120，但是在第二器件200中不形成凹槽120。可以利用热压接合、回流工艺、NIR回流工艺或其他合适的接合工艺来物理地连接第一和第二器件。在接合之后，第二器件200的衬底202覆盖第一器件100的器件层104中的凹槽120。TSV140和金属焊盘116提供用于电连接器件层104和204中的电路的信号路径。
在操作24中，在接合之后，方法10(图1B)形成穿过第二器件200的器件层204并可选地进入衬底202的上部的凹槽120(图15)。该开槽工艺基本上类似于以上结合图5所讨论的那些。器件层204中的凹槽120直接位于器件层104中的相应凹槽120之上。
随后，在操作42中，方法10(图1B)利用除激光之外的切割技术(诸如机械切割方法)沿划线沟道区域108进行切割，以将接合的半导体结构切成两个或更多个小片300(图16)。在一些实施例中，机械切割采用锯片或刀片(未示出)以依次切割穿过上部凹槽120、衬底202、下部凹槽120和衬底102。衬底202中的切割切口126连接上部凹槽120和下部凹槽120。机械切割基本上类似于以上结合图12所讨论的。
参考图1C，方法10可以可选地包括其他操作。在一些实施例中，在接合第一器件100和第二器件200的操作32之后，方法10进行到操作34以进行衬底厚度减小工艺(图17)。执行衬底厚度减小工艺(也称为减薄工艺)以减小其中一个衬底或两者的厚度。在所示的实施例中，减薄第二器件200的衬底202。例如，从约700μm的厚度到约5μm的厚度。在一些实施例中，将粗磨和精磨施加到衬底202的背面。在粗磨步骤中，去除相当大的一部分但不是整个衬底202的厚度。在该粗磨步骤中去除的材料的量部分地由粗磨和额外的工艺步骤之后的硅表面的总粗糙度来确定，额外的工艺步骤将需要用来消除在粗磨步骤期间产生的粗糙度和损伤。粗磨的表面的平均粗糙度可以使用轮廓仪确定，平均粗糙度在一个平方厘米的面积上进行测量。为了去除在粗研磨步骤中产生的粗糙度和损伤，对衬底202的表面进行第二研磨步骤，即细磨步骤。对于细磨，可以使用网眼精磨轮。
在操作36中，方法10(图1C)在减薄的衬底上形成滤色器和/或透镜(图17)。在所示的实施例中，滤色器134设置在减薄的衬底202的背面上方并与全芯片区域106内的光感测区域对准。滤色器134被设计为使其过滤预定波长的某些光。例如，滤色器134可过滤红色波长、绿色波长或蓝色波长的可见光到达感测区域。滤色器134包括任何合适的材料。在示例中，滤色器134包括用于滤出特定频带(例如，期望的光的波长)的基于染料的(或基于颜料的)聚合物。可选地，滤色器134包括具有彩色颜料的树脂或其他有机基材料。可以将透镜(未示出)设置在衬底202的背面上方，特别是滤色器134上方并且还与光感测区域对准。透镜可与感测区域和滤色器134处于各种位置布置，使得透镜将入射辐射聚焦在感测区域上。透镜包括合适的材料，并且可以具有多种形状和尺寸，这取决于用于透镜的材料的折射率和/或透镜与感测区域之间的距离。可选地，滤色器134和透镜层的位置可以颠倒，使得将透镜设置在减薄的衬底202和滤色器134之间。
在操作38中，方法10(图1C)形成沟槽138以暴露金属焊盘116(图18)。在所示的实施例中，沟槽138被图案化并从衬底202的背面穿过衬底202和器件层204进行蚀刻，并到达设计用于接收接合线的金属焊盘116。沟槽138可以被认为是硅通孔(TSV)，并且金属焊盘116可以被认为是接合焊盘。
在操作42中，方法10(图1C)使用除激光之外的其他切割技术(诸如机械切割)沿着划线沟道区域108进行切割，以将接合的半导体结构分为两个或多个小片300(图19)。在一些实施例中，机械切割采用锯片或刀片(未示出)依次切割穿过减薄的衬底202、上部凹槽120、下部凹槽120和衬底102。在一些可选实施例中，锯片或刀片没有完全切割穿过衬底102，但是随后进行机械切割工艺以使接合的半导体结构破裂成小片。
方法10(图1C)可以进一步进行其他操作以完成半导体IC 300，诸如通过沟槽138将接合线142落在接合焊盘116上以将器件层104和204中的电路外部电耦合至诸如引线框架(图20)。
图21示出了形成倒装芯片接合以从芯片底部布线单个路径的半导体IC 300的另一实施例。在所示的实施例中，TSV 146形成在衬底102中，金属焊盘148形成在衬底102的底面上。随后在金属焊盘148上沉积焊料凸块(或Cu凸块)152。图22示出了在器件层204的顶面上形成引线接合的半导体IC 300的另一实施例。在所示的实施例中，衬底202在接合工艺中直接面向器件层104。衬底202中的TSV 140提供从器件层204到器件层104的信号路径。器件层204的金属焊盘116暴露在半导体IC 300的顶面上，以向接合线142提供着陆焊盘。接合线142将器件层104和204中的电路外部电耦合至诸如引线框架。
尽管不限于此，但是本发明的一个或多个实施例提供了对堆叠半导体器件及其制造方法的改进。例如，本发明的实施例提供了一种混合切割工艺，该工艺包括在接合之前进行激光开槽工艺，然后进行机械切割，这减轻堆叠半导体器件切割期间的不利影响，诸如与传统晶圆切割方法相关的微裂纹和硅屑再沉积，因此减少了与切割相关的器件损坏并提高了产品良率。此外，堆叠半导体器件的形成可以容易地集成到现有的半导体制造工艺中。
因此，本发明提供了用于制造半导体器件的许多不同实施例。在一个示例性方面，本发明针对一种方法。该方法包括提供第一和第二晶圆；在第一晶圆的顶部中形成第一器件层；在第二晶圆的顶部中形成第二器件层；在第一器件层中形成第一凹槽；在第二器件层中形成第二凹槽；在形成第一凹槽和第二凹槽中的至少一个之后，将第一晶圆和第二晶圆接合在一起；以及通过切割工艺切割接合的第一晶圆和第二晶圆，其中切割工艺切割穿过第一凹槽和第二凹槽。在一些实施例中，通过激光开槽工艺形成第一凹槽和第二凹槽的每个。在一些实施例中，切割工艺包括用锯片或刀片进行机械切割。在一些实施例中，在接合之后，第二凹槽直接位于第一凹槽下方。在一些实施例中，第一凹槽完全延伸穿过第一器件层，并且第二凹槽完全延伸穿过第二器件层。在一些实施例中，在接合之后，第一器件层面向第二器件层，使得空隙从第一凹槽连续地延伸到第二凹槽。在一些实施例中，第一器件层包括第一接合焊盘，并且第二器件层包括第二接合焊盘，并且其中，接合将第一接合焊盘物理地连接到第二接合焊盘。在一些实施例中，该方法还包括在接合之前在第二晶圆中形成衬底通孔(TSV)，使得衬底通孔将第二器件层电耦合至第二晶圆的底面处的接合焊盘。在一些实施例中，在接合之后，第二器件层面向第一晶圆的底面。在一些实施例中，该方法还包括在接合之前在第一晶圆中形成衬底通孔(TSV)，使得衬底通孔在接合之后将第一器件层电耦合至第二器件层。在一些实施例中，第一凹槽具有第一侧壁，通过切割工艺形成的切口具有第二侧壁，并且第一侧壁的斜率小于第二侧壁的斜率。
在另一个示例性方面，本发明针对一种制造堆叠半导体器件的方法。该方法包括提供第一结构，第一结构具有第一衬底和位于第一衬底上的第一器件层；提供第二结构，第二结构具有第二衬底和位于第二衬底上的第二器件层；在第二器件层中形成第二凹槽；将第一衬底的底面接合至第二器件层的顶面；在接合之后，在第一器件层中形成第一凹槽；以及依次切割穿过第一凹槽、第一衬底、第二凹槽和第二衬底。在一些实施例中，通过激光开槽工艺形成第一凹槽和第二凹槽中的每个。在一些实施例中，切割包括用锯片或刀片的机械切割。在一些实施例中，第一凹槽延伸到第一衬底的顶部中，并且第二凹槽延伸到第二衬底的顶部中。在一些实施例中，第一凹槽和第二凹槽中的每个沿着划线沟道。在一些实施例中，第一凹槽具有第一侧壁，第一衬底具有通过切割形成的第二侧壁，并且第一侧壁的表面粗糙度大于第二侧壁的表面粗糙度。
在又一示例性方面，本发明针对一种堆叠半导体器件。该堆叠半导体器件包括：第一衬底，具有第一侧壁；第一器件层，位于第一衬底上，具有第二侧壁，其中，第二侧壁的表面粗糙度大于第一侧壁的表面粗糙度；以及材料层，接合至第一器件层，其中，第一器件层包括电连接到材料层中的第二导电部件的第一导电部件。在一些实施例中，第二侧壁的表面粗糙度是第一侧壁的表面粗糙度的至少五倍。在一些实施例中，第二侧壁的斜率小于第一侧壁的斜率。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基底来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并且不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种制造堆叠半导体器件的方法，包括：
提供第一晶圆和第二晶圆；
在所述第一晶圆的顶部中形成第一器件层；
在所述第二晶圆的顶部中形成第二器件层；
在所述第一器件层中通过第一工艺形成第一凹槽；
在所述第二器件层中通过所述第一工艺形成第二凹槽；
在形成所述第一凹槽和所述第二凹槽中的至少一个之后，将所述第一晶圆和所述第二晶圆接合在一起；以及
通过机械切割工艺切割接合的第一晶圆和第二晶圆，其中，所述机械切割工艺切割穿过所述第一凹槽和所述第二凹槽，
其中，所述第一晶圆具有位于所述第一器件层下方的第一衬底，所述第二晶圆具有位于所述第二器件层下方的第二衬底，
其中，所述第一工艺为：假设切割器件层和衬底时在所述衬底中产生的硅屑大于在所述器件层中产生的硅屑的工艺，并且所述第一工艺基本上限于所述器件层而没有进一步深入到所述衬底中，所述第一工艺与所述机械切割工艺相比减轻了在所述器件层中产生的微裂纹；
并且其中，所述机械切割工艺限于所述第一衬底和所述第二衬底而不切割所述第一器件层和所述第二器件层；
其中，所述第一器件层和所述第二器件层各自分别包括晶体管和耦合到所述晶体管的多层互连件，其中所述多层互连件包括设置在层间介电层中的导电部件以及形成在所述第一器件层和所述第二器件层的最上部分中的金属焊盘。
2.根据权利要求1所述的方法，其中，所述第一工艺为激光开槽工艺。
3.根据权利要求2所述的方法，其中，所述机械切割工艺包括用锯片或刀片的机械切割。
4.根据权利要求1所述的方法，其中，在所述接合之后，所述第二凹槽直接位于所述第一凹槽下方。
5.根据权利要求1所述的方法，其中，所述第一凹槽完全延伸穿过所述第一器件层，并且所述第二凹槽完全延伸穿过所述第二器件层。
6.根据权利要求1所述的方法，其中，在所述接合之后，所述第一器件层面向所述第二器件层，使得空隙从所述第一凹槽连续地延伸到所述第二凹槽。
7.根据权利要求6所述的方法，其中，所述第一器件层包括第一接合焊盘，并且所述第二器件层包括第二接合焊盘，并且其中，所述接合将所述第一接合焊盘物理地连接到所述第二接合焊盘，
其中，所述第一接合焊盘为所述第一器件层中的金属焊盘，所述第二接合焊盘为所述第二器件层中的金属焊盘。
8.根据权利要求6所述的方法，还包括：
在所述接合之前，在所述第二晶圆中形成衬底通孔，使得所述衬底通孔将所述第二器件层电耦合至所述第二晶圆的底面处的金属焊盘。
9.根据权利要求1所述的方法，其中，在所述接合之后，所述第二器件层面向所述第一晶圆的底面。
10.根据权利要求9所述的方法，还包括：
在所述接合之前，在所述第一晶圆中形成衬底通孔，使得在所述接合之后，所述衬底通孔将所述第一器件层电耦合至所述第二器件层。
11.根据权利要求1所述的方法，其中，所述第一凹槽具有第一侧壁，通过所述机械切割工艺形成的切口具有第二侧壁，并且所述第一侧壁的斜率小于所述第二侧壁的斜率。
12.一种制造堆叠半导体器件的方法，包括：
提供第一结构，所述第一结构具有第一衬底和位于所述第一衬底上的第一器件层；
提供第二结构，所述第二结构具有第二衬底和位于所述第二衬底上的第二器件层；
在所述第二器件层中通过第一工艺形成第二凹槽；
将所述第一衬底的底面接合至所述第二器件层的顶面；
在所述接合之后，在所述第一器件层中通过所述第一工艺形成第一凹槽；以及
通过机械切割工艺，依次切割穿过所述第一凹槽、所述第一衬底、所述第二凹槽和所述第二衬底，
其中，所述第一工艺为：假设切割器件层和衬底时在所述衬底中产生的硅屑大于在所述器件层中产生的硅屑的工艺，并且所述第一工艺基本上限于所述器件层而没有进一步深入到所述衬底中，所述第一工艺与所述机械切割工艺相比减轻了在所述器件层中产生的微裂纹；
并且其中，所述机械切割工艺限于所述第一衬底和所述第二衬底而不切割所述第一器件层和所述第二器件层；
其中，所述第一器件层和所述第二器件层各自分别包括晶体管和耦合到所述晶体管的多层互连件，其中所述多层互连件包括设置在层间介电层中的导电部件以及形成在所述第一器件层和所述第二器件层的最上部分中的金属焊盘。
13.根据权利要求12所述的方法，其中，所述第一工艺为激光开槽工艺。
14.根据权利要求12所述的方法，其中，所述机械切割工艺包括用锯片或刀片的机械切割。
15.根据权利要求12所述的方法，其中，所述第一凹槽延伸到所述第一衬底的顶部中，并且所述第二凹槽延伸到所述第二衬底的顶部中。
16.根据权利要求12所述的方法，其中，所述第一凹槽和所述第二凹槽中的每个沿着划线沟道。
17.根据权利要求12所述的方法，其中，所述第一凹槽具有第一侧壁，所述第一衬底具有通过所述机械切割工艺形成的第二侧壁，并且所述第一侧壁的表面粗糙度大于所述第二侧壁的表面粗糙度。
18.一种堆叠半导体器件，包括：
第一衬底，具有第一侧壁；
第一器件层，位于所述第一衬底上，具有第二侧壁，其中，所述第二侧壁的表面粗糙度大于所述第一侧壁的表面粗糙度；以及
材料层，接合至所述第一器件层，其中，所述第一器件层包括第一导电部件，所述第一导电部件电连接到所述材料层中的第二导电部件，
其中，所述第二侧壁的斜率小于所述第一侧壁的斜率，
其中，所述第二侧壁为采用激光切割工艺或等离子切割工艺产生的侧壁，所述激光切割工艺或所述等离子切割工艺基本上限于所述第一器件层而没有进一步深入到所述第一衬底中，
其中，所述第一侧壁为采用机械切割工艺产生的侧壁，所述机械切割工艺限于所述第一衬底并且与所述第一器件层没有实质的物理接触，
其中，所述第一器件层包括晶体管和耦合到所述晶体管的多层互连件，其中所述多层互连件包括设置在层间介电层中的导电部件以及形成在所述第一器件层的最上部分中的金属焊盘。
19.根据权利要求18所述的堆叠半导体器件，其中，所述第二侧壁的表面粗糙度是所述第一侧壁的表面粗糙度的至少五倍。
20.根据权利要求18所述的堆叠半导体器件，其中，在所述第二侧壁与所述第一衬底的底面之间形成的角度在35°至80°的范围内。
CN201910927994.4A 2018-09-28 2019-09-27 堆叠半导体器件及其制造方法 Active CN110970358B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862738395P 2018-09-28 2018-09-28
US62/738,395 2018-09-28
US16/559,302 US11081392B2 (en) 2018-09-28 2019-09-03 Dicing method for stacked semiconductor devices
US16/559,302 2019-09-03

Publications (2)

Publication Number Publication Date
CN110970358A CN110970358A (zh) 2020-04-07
CN110970358B true CN110970358B (zh) 2023-11-10

Family

ID=69946521

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910927994.4A Active CN110970358B (zh) 2018-09-28 2019-09-27 堆叠半导体器件及其制造方法

Country Status (4)

Country Link
US (2) US11081392B2 (zh)
KR (2) KR20200037105A (zh)
CN (1) CN110970358B (zh)
TW (1) TWI721568B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11362069B2 (en) * 2019-08-28 2022-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional stacking structure and manufacturing method thereof
FR3101726B1 (fr) * 2019-10-04 2021-10-01 Commissariat Energie Atomique procédé de fabrication d’un dispositif électronique
CN110676244B (zh) * 2019-10-15 2020-06-16 杭州见闻录科技有限公司 一种芯片封装方法及封装结构
TWI757127B (zh) * 2021-02-19 2022-03-01 南亞科技股份有限公司 製造半導體裝置的方法
CN115602650A (zh) * 2021-07-09 2023-01-13 佳能株式会社（Jp） 半导体设备、装备以及半导体设备的制造方法
US11817420B2 (en) * 2021-07-19 2023-11-14 Micron Technology, Inc. Systems and methods for direct bonding in semiconductor die manufacturing
CN115704677A (zh) * 2021-08-13 2023-02-17 长鑫存储技术有限公司 一种计量标准器及其制备方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4612083A (en) * 1984-07-20 1986-09-16 Nec Corporation Process of fabricating three-dimensional semiconductor device
CN1528009A (zh) * 2001-04-13 2004-09-08 原子能委员会 可拆除基片或可拆除结构及其生产方法
US8048778B1 (en) * 2010-12-10 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of dicing a semiconductor structure
JP2012114322A (ja) * 2010-11-26 2012-06-14 Shinko Electric Ind Co Ltd 半導体ウエハの分割方法
US8361828B1 (en) * 2011-08-31 2013-01-29 Alta Devices, Inc. Aligned frontside backside laser dicing of semiconductor films
JP2014116561A (ja) * 2012-12-12 2014-06-26 Renesas Electronics Corp 半導体装置の製造方法
CN104347760A (zh) * 2013-07-24 2015-02-11 晶能光电（江西）有限公司 一种led芯片的切割方法
CN105304617A (zh) * 2014-05-30 2016-02-03 台湾积体电路制造股份有限公司 半导体器件及其制造方法
KR20160029097A (ko) * 2013-07-02 2016-03-14 어플라이드 머티어리얼스, 인코포레이티드 높은 다이 파괴 강도 및 평활한 측벽을 위한 레이저 스크라이빙 및 플라즈마 에칭
CN107210207A (zh) * 2015-11-09 2017-09-26 古河电气工业株式会社 半导体芯片的制造方法和用于该制造方法的掩模一体型表面保护带

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6314823B1 (en) * 1991-09-20 2001-11-13 Kazuhiro Okada Force detector and acceleration detector and method of manufacturing the same
JP3635219B2 (ja) * 1999-03-11 2005-04-06 新光電気工業株式会社 半導体装置用多層基板及びその製造方法
JP4018312B2 (ja) * 2000-02-21 2007-12-05 株式会社ルネサステクノロジ 無線通信装置
JP3433193B2 (ja) * 2000-10-23 2003-08-04 松下電器産業株式会社 半導体チップおよびその製造方法
KR100570514B1 (ko) * 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
US20060057777A1 (en) 2004-09-14 2006-03-16 Howell William C Separating die on a substrate to reduce backside chipping
US7582960B2 (en) * 2005-05-05 2009-09-01 Stats Chippac Ltd. Multiple chip package module including die stacked over encapsulated package
SG135074A1 (en) * 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
KR100785493B1 (ko) * 2006-05-04 2007-12-13 한국과학기술원 접착제의 수분흡습을 방지하는 플립칩용 웨이퍼 레벨패키지 제조방법
US7569421B2 (en) 2007-05-04 2009-08-04 Stats Chippac, Ltd. Through-hole via on saw streets
JP5032231B2 (ja) 2007-07-23 2012-09-26 リンテック株式会社 半導体装置の製造方法
US7750459B2 (en) * 2008-02-01 2010-07-06 International Business Machines Corporation Integrated module for data processing system
JP5221279B2 (ja) 2008-10-22 2013-06-26 株式会社ディスコ 積層デバイスの製造方法
TWI402941B (zh) * 2009-12-03 2013-07-21 Advanced Semiconductor Eng 半導體結構及其製造方法
US8012802B2 (en) * 2010-02-04 2011-09-06 Headway Technologies, Inc. Method of manufacturing layered chip package
TWI422064B (zh) 2010-05-21 2014-01-01 Lextar Electronics Corp 發光二極體晶片及其製作方法
TW201234463A (en) 2011-02-01 2012-08-16 Lextar Electronics Corp Semiconductor device and cutting method thereof
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8952413B2 (en) * 2012-03-08 2015-02-10 Micron Technology, Inc. Etched trenches in bond materials for die singulation, and associated systems and methods
US8652940B2 (en) * 2012-04-10 2014-02-18 Applied Materials, Inc. Wafer dicing used hybrid multi-step laser scribing process with plasma etch
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
JP6078376B2 (ja) 2013-02-22 2017-02-08 株式会社ディスコ ウエーハの加工方法
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
KR20150119350A (ko) * 2013-04-10 2015-10-23 미쓰비시덴키 가부시키가이샤 반도체 장치, 반도체 장치의 제조 방법
JP6246534B2 (ja) 2013-09-11 2017-12-13 株式会社ディスコ ウエーハの加工方法
JP6162018B2 (ja) * 2013-10-15 2017-07-12 株式会社ディスコ ウエーハの加工方法
JP6189208B2 (ja) 2013-12-26 2017-08-30 株式会社ディスコ ウエーハの加工方法
US9559005B2 (en) * 2014-01-24 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging and dicing semiconductor devices and structures thereof
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
JP6234312B2 (ja) 2014-04-11 2017-11-22 株式会社ディスコ 積層基板の加工方法
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9570419B2 (en) * 2015-01-27 2017-02-14 Infineon Technologies Ag Method of thinning and packaging a semiconductor chip
US10805561B2 (en) * 2015-07-27 2020-10-13 Sony Corporation Solid-state image pickup device and control method therefor, and electronic apparatus
US9922895B2 (en) * 2016-05-05 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with tilted interface between device die and encapsulating material
JP6765949B2 (ja) 2016-12-12 2020-10-07 株式会社ディスコ ウェーハの加工方法
JP6859708B2 (ja) * 2017-01-10 2021-04-14 昭和電工マテリアルズ株式会社 半導体装置を製造する方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4612083A (en) * 1984-07-20 1986-09-16 Nec Corporation Process of fabricating three-dimensional semiconductor device
CN1528009A (zh) * 2001-04-13 2004-09-08 原子能委员会 可拆除基片或可拆除结构及其生产方法
JP2012114322A (ja) * 2010-11-26 2012-06-14 Shinko Electric Ind Co Ltd 半導体ウエハの分割方法
US8048778B1 (en) * 2010-12-10 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of dicing a semiconductor structure
US8361828B1 (en) * 2011-08-31 2013-01-29 Alta Devices, Inc. Aligned frontside backside laser dicing of semiconductor films
JP2014116561A (ja) * 2012-12-12 2014-06-26 Renesas Electronics Corp 半導体装置の製造方法
KR20160029097A (ko) * 2013-07-02 2016-03-14 어플라이드 머티어리얼스, 인코포레이티드 높은 다이 파괴 강도 및 평활한 측벽을 위한 레이저 스크라이빙 및 플라즈마 에칭
CN104347760A (zh) * 2013-07-24 2015-02-11 晶能光电（江西）有限公司 一种led芯片的切割方法
CN105304617A (zh) * 2014-05-30 2016-02-03 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN107210207A (zh) * 2015-11-09 2017-09-26 古河电气工业株式会社 半导体芯片的制造方法和用于该制造方法的掩模一体型表面保护带

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
新型的3D堆叠封装制备工艺及其实验测试;范汉华等;《半导体技术》;20080503(第05期);409-413页 *

Also Published As

Publication number Publication date
KR20200037105A (ko) 2020-04-08
US20210358808A1 (en) 2021-11-18
TWI721568B (zh) 2021-03-11
CN110970358A (zh) 2020-04-07
TW202022937A (zh) 2020-06-16
US11081392B2 (en) 2021-08-03
KR20210132634A (ko) 2021-11-04
US20200105600A1 (en) 2020-04-02
KR102521267B1 (ko) 2023-04-12

Similar Documents

Publication Publication Date Title
CN110970358B (zh) 堆叠半导体器件及其制造方法
US20230207530A1 (en) Stacked Semiconductor Structure and Method
US9293369B2 (en) Three-dimensional integrated circuit (3DIC)
US9059167B2 (en) Structure and method for making crack stop for 3D integrated circuits
US8742583B2 (en) Seal ring in an integrated circuit die
US9613865B2 (en) Semiconductor die and die cutting method
US20230268300A1 (en) Bonded structures
TW201822273A (zh) 裁切半導體晶圓的方法
US8048778B1 (en) Methods of dicing a semiconductor structure
CN113523597B (zh) 晶圆切割方法
US11158593B2 (en) Structures for bonding a group III-V device to a substrate by stacked conductive bumps
US10515908B2 (en) Seal ring for bonded dies
TW202036697A (zh) 形成及封裝半導體晶粒的方法
KR20180053802A (ko) 기판 구조체 제조 방법 및 이를 이용하여 제조된 기판 구조체
TWI649815B (zh) 用於接合的多重撞擊過程
US20130049234A1 (en) Substrate Dicing
US20230402324A1 (en) Dicing method for stacked semiconductor devices
CN112750758A (zh) 集成芯片结构和其形成方法以及形成多维集成芯片的方法
CN114695136A (zh) 形成集成芯片的方法及处理工具
TWI741903B (zh) 感測器及其製造方法
CN116936534A (zh) 半导体器件及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant