TW202036697A - 形成及封裝半導體晶粒的方法 - Google Patents

形成及封裝半導體晶粒的方法 Download PDF

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TW202036697A
TW202036697A TW108130646A TW108130646A TW202036697A TW 202036697 A TW202036697 A TW 202036697A TW 108130646 A TW108130646 A TW 108130646A TW 108130646 A TW108130646 A TW 108130646A TW 202036697 A TW202036697 A TW 202036697A
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insulating film
interlayer insulating
passivation layer
silicon
semiconductor die
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TW108130646A
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TWI801656B (zh
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崔載植
鄭鎭源
宋炳受
沈東其
裵眞漢
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南韓商美格納半導體有限公司
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Abstract

提供一種用於半導體晶粒之製造及封裝方法。該方法包括：製備具有密封環區域之晶圓，在該晶圓上形成第一層間絕緣薄膜，在該第一層間絕緣薄膜中形成金屬佈線，在該第一層間絕緣薄膜中形成第二層間絕緣薄膜，在該第二層間絕緣薄膜上形成金屬襯墊，在這些金屬襯墊上形成鈍化層，移除該鈍化層之在鄰近該密封環區域之一區域中的一部分以暴露該第二層間絕緣薄膜，蝕刻該第二層間絕緣薄膜之一部分，在這些金屬襯墊上形成凸塊，藉由雷射開槽製程移除在鄰近該密封環區域之該區域中的該第一層間絕緣薄膜及該第二層間絕緣薄膜，及將該晶圓切塊成第一半導體晶粒及第二半導體晶粒。

Description

形成及封裝半導體晶粒的方法
以下描述係關於形成及封裝半導體晶粒的方法。 相關申請之交互參照
本申請案主張2019年3月28日在韓國智慧財產局提交的韓國專利申請案第10-2019-0036315號之權益，該專利申請案之全部揭露內容針對所有目的被以引用的方式併入本文中。
鑒於顯示裝置之高解析度，顯示器積體電路（IC）可能需要實施精細（fine）圖案。為了實施此精細圖案，應防止這些圖案之間的短路。亦即，隨著佈線之間的間距伴隨顯示器IC之小型化而減小，與絕緣有關之問題變為重要的課題。
為了佈線之間的絕緣，絕緣薄膜可由具有低介電常數之絕緣材料形成。可藉由增大絕緣材料中之孔（例如，空氣層）來降低絕緣薄膜之介電常數。
然而，當降低介電常數時，在藉由刀片切塊製程切割晶圓時，引起各種問題。舉例而言，結合力歸因於降低之介電常數而降低，脆性增大，且晶圓之強度降低。
此外，歸因於使用切割刀片之機械切割製程，應力集中於具有低介電常數之絕緣薄膜上，且歸因於絕緣薄膜與矽界面之間的結合力之降低，使界面可分層。
提供此發明內容以按簡化形式介紹下文在實施方式中進一步描述的概念之選擇。此發明內容並不意欲識別所主張標的之關鍵特徵或必要特徵，亦不意欲用作在判定所主張標的之範圍時之輔助。
在一般態樣中，一種半導體晶粒之製造及封裝方法包括：製備具有密封環區域之晶圓，在該晶圓上形成第一層間絕緣薄膜，在該第一層間絕緣薄膜中形成金屬佈線，在該第一層間絕緣薄膜中形成一第二層間絕緣薄膜，在該第二層間絕緣薄膜上形成金屬襯墊，在這些金屬襯墊上形成鈍化層，移除該鈍化層之在鄰近該密封環區域之一區域中的一部分以暴露該第二層間絕緣薄膜，蝕刻該第二層間絕緣薄膜之一部分，在這些金屬襯墊上形成凸塊，藉由一雷射開槽製程移除在鄰近該密封環區域之該區域中的該第一層間絕緣薄膜及該第二層間絕緣薄膜，及將該晶圓切塊成第一半導體晶粒及第二半導體晶粒。
該方法可包括製備具有輸入電線圖案及輸出電線圖案之可撓性薄膜，及藉由傳導性球將該凸塊附著至這些輸入電線圖案及這些輸出電線圖案中之至少一者。
該方法可進一步包括自該雷射開槽製程產生矽碎片，其中該矽碎片係自該第二層間絕緣薄膜之頂表面開始形成。
該矽碎片之高度可按該鈍化層之厚度來降低。
該雷射開槽製程可包括第一雷射開槽製程及第二雷射開槽製程，且該第二雷射開槽製程之脈衝寬度可大於該第一雷射開槽製程之脈衝寬度。
該第一層間絕緣薄膜之介電常數可低於3.0，且該第一層間絕緣薄膜之該介電常數可低於該第二層間絕緣薄膜之介電常數。
在一般態樣中，一種半導體晶粒之製造及封裝方法包括：製備具有劃線及密封環區域之晶圓，在該晶圓上形成層間絕緣薄膜、金屬佈線及金屬墊，在這些金屬墊及該層間絕緣薄膜上形成鈍化層，蝕刻該鈍化層，暴露這些金屬墊之一部分，蝕刻該層間絕緣薄膜，在這些金屬墊上形成凸塊，執行雷射開槽製程以在鄰近該密封區域之該經蝕刻層間絕緣薄膜上產生矽碎片，藉由該雷射開槽製程移除該劃線中之該層間絕緣薄膜，及將該晶圓切塊以形成該半導體晶粒。
該層間絕緣薄膜包含第一層間絕緣薄膜及第二層間絕緣薄膜，該第一層間絕緣薄膜之介電常數值小於該第二層間絕緣薄膜之介電常數值，該金屬佈線包含銅組件，該金屬墊包含鋁組件，且該鈍化層包含氮化矽薄膜。
在鄰近該密封環區域之一區域中可移除該鈍化層之一部分，且在鄰近該凸塊之一區域中可維持該鈍化層之一部分。
該矽碎片之底部可按該鈍化層之厚度來降低。
在一般態樣中，一種半導體晶粒之製造及封裝方法包括：在基板上形成第一層間絕緣薄膜，在該第一層間絕緣薄膜上形成第二層間絕緣薄膜，在該第二層間絕緣薄膜上形成金屬襯墊，在這些金屬襯墊上形成鈍化層，移除該鈍化層之一部分以暴露該第二層間絕緣薄膜，在這些金屬襯墊上形成凸塊，藉由一雷射開槽製程過度蝕刻(over-etch)該第二層間絕緣薄膜之一部分及該第一層間絕緣薄膜之一部分，及自該雷射開槽製程產生矽碎片，其中該矽碎片形成於該第二層間絕緣薄膜之該經過度蝕刻部分之上表面上，且其中該矽碎片之底表面定位低於該鈍化層之底表面，且該矽碎片之頂表面低於該凸塊之頂表面。
該矽碎片之底表面可定位低於該凸塊之底表面。
其他特徵及態樣將自以下詳細描述、圖式及申請專利範圍顯而易見。
提供以下詳細描述以輔助讀者獲得對本文中描述的方法、設備及/或系統之綜合理解。然而，在理解本申請案之揭露內容後，本文中描述的方法、設備及/或系統之各種改變、修改及等效內容將顯而易見。舉例而言，本文中描述的操作之順序僅為實例，且不限於本文中闡述之那些，而可加以改變，如將在理解本申請案之揭露內容後顯而易見，惟有必要按某一次序發生之操作例外。又，為了增加之清晰及簡潔性，可省略此項技術中已知的特徵之描述。
本文中描述之特徵可以不同形式具體實現，且不應被解釋為限於本文中描述之實例。相反地，本文中描述之實例已僅經提供來說明實施本文中描述的方法、設備及/或系統之許多可能方式中之一些，在理解本申請案之揭露內容後，這些方式將為顯而易見的。
雖然諸如「第一」、「第二」及「第三」之術語可在本文中用以描述各種部件、組件、區域、層或區段，但此等部件、組件、區域、層或區段不應受到此等術語限制。相反地，此等術語僅用以將一個部件、組件、區域、層或區段與另一部件、組件、區域、層或區段區分開來。因此，在不脫離這些實例之教示之情況下，在本文中描述之實例中提及之第一部件、組件、區域、層或區段亦可被稱作第二部件、組件、區域、層或區段。
本文中使用之術語僅係為了描述各種實例，且不應用來限制揭露內容。冠詞「一（a及an）」及「該（the）」亦意欲包括複數形式，除非上下文另有清晰指示。術語「包含（comprises）」、「包括（includes）」及「具有（has）」指定所陳述特徵、數目、操作、成員、要素及/或其組合之存在，但不排除一或多個其他特徵、數目、操作、成員、要素及/或其組合之存在或添加。
除非另有定義，否則本文中使用之所有術語（包括技術及科學術語）具有與所屬技術領域中具有通常知識者在理解本揭露內容後所通常理解的意義相同。諸如那些在常用詞典中定義之術語應被解釋為具有與其在相關技術及本揭露內容之情境中之意義一致的意義，且不應按理想化或過度形式化之涵義來解釋，除非本文中明確地如此定義。
提供以下描述以解決在為後續製程之各向異性傳導性薄膜（ACF）結合製程期間由ACF傳導性球引起之短路故障，該故障係歸因於在針對半導體晶粒之雷射開槽製程期間在鈍化層中形成之矽碎片。下文，本揭露內容之特徵將參考在圖式中展示之實例詳細地描述。
以下描述提供一種形成及封裝半導體晶粒之方法，其可消除針對短路故障之原因，該方法藉由在用於切割有顯示器IC安裝其中之單位晶胞之鋸切製程期間使用雷射執行開槽製程，直至在晶圓之劃線上的絕緣薄膜之下部區域，及藉由在於半導體晶粒之面板製程期間之ACF結合時使阻礙ACF傳導性球之流動的矽碎片之產生之高度最小化。
亦即，以下描述調整在雷射開槽製程期間形成矽碎片之位置，由此確保在凸塊之頂部與矽碎片之間的足夠空間。
圖1為根據本揭露內容之實例的晶圓之實例之橫截面圖。
參看圖1，晶圓1000包括第一半導體晶粒100、第二半導體晶粒200及劃線110，以及位於第一半導體晶粒100、200中之每一半導體晶粒與劃線110之間的密封環區域120、130。當將劃分成第一半導體晶粒100及第二半導體晶粒200之晶圓1000切塊時，密封環區域120、130可防止裂開。
該半導體晶粒可具有用於訊號處理之若干區域。可形成閘絕緣薄膜20、閘電極、接觸插塞、金屬佈線30、通路45、金屬襯墊50、60、80及類似者用於訊號處理。為了方便起見，將晶圓劃分成第一半導體晶粒100及第二半導體晶粒200。本文中，須注意的是，關於實例或實施例之術語「可（may）」的使用（例如，涉及實例或實施例可包括或實施之內容）意謂存在包括或實施此特徵之至少一個實例或實施例，而非所有實例及實施例限制於此。
劃線110可為形成測試圖案以測試第一半導體晶粒100及第二半導體晶粒200之效能的區域。替代地，劃線110可為在蝕刻製程後量測殘餘薄膜之厚度的區域，形成量測圖案長度或類似者之圖案，或形成用於遮罩對準之圖案。劃線110可隨後藉由鋸切製程（切塊）來移除。
在一實例中，半導體晶粒100、200中之每一者在半導體基板10上形成低介電絕緣薄膜20（或第一層間絕緣薄膜）。該低介電絕緣薄膜20可減少RC延遲。在一實例中，介電常數為3或更低之低介電層20的化合物可使用諸如SiOC、SiC、SiO2 或類似化合物。多個金屬佈線30（多層金屬：MLM）可形成於低介電絕緣薄膜20上。可將銅（Cu）金屬或鋁金屬用於金屬佈線30。可廣泛地使用銅金屬，因為它具有比鋁金屬低的電阻率。金屬佈線之最後金屬佈線30f可形成為比其他金屬佈線30還厚，以便減小電阻。
在一實例中，第二層間絕緣薄膜40沉積於半導體晶粒100、200中之最後金屬佈線30f及低介電絕緣薄膜20上。為第一層間絕緣薄膜之低介電絕緣薄膜20以及第二層間絕緣薄膜40可共同地被稱作層間絕緣薄膜。金屬通路45形成於第二層間絕緣薄膜40中以將金屬襯墊50、60及80連接至最後金屬佈線30f。
換言之，在一般態樣中的半導體晶粒100、200中之每一者之層間絕緣薄膜包括第一層間絕緣薄膜20及第二層間絕緣薄膜40。當對金屬襯墊執行線結合時，第二層間絕緣薄膜40防止水分及減輕影響。第二層間絕緣薄膜40之介電常數值可大於低介電絕緣薄膜20之介電常數。替代地，為了減少RC延遲，可將與低介電絕緣薄膜20相同之絕緣薄膜用作第二層間絕緣薄膜40。可將厚氧化矽薄膜、氮化矽薄膜或氮氧化矽薄膜用作第二層間絕緣薄膜40。
金屬襯墊50、60及80及測試襯墊70分別形成於半導體晶粒100、200及劃線110中。可將鋁（Al）金屬用於金屬襯墊50、60及80。鈍化層90可形成於低介電絕緣薄膜20、第二層間絕緣薄膜40、金屬襯墊50、60及80及測試襯墊70上。鈍化層90可保護裝置免受外部水分。可藉由使用氧化矽薄膜及氮化矽薄膜連續地沉積來形成鈍化層90。亦即，鈍化層90可為氧化矽薄膜與氮化矽薄膜之雙層薄膜。
替代地，可僅將氮化矽薄膜用作單一層。可形成鈍化層90以與第二層間絕緣薄膜40直接接觸。可形成鈍化層90以包圍金屬襯墊50、60及80及測試襯墊70。
圖2A及圖2B為在鈍化層90之圖案化後的晶圓之實例之橫截面圖。
參看圖2A及圖2B，在藉由鈍化蝕刻遮罩圖案化鈍化層90後，根據一實例之晶圓1000可暴露第二層間絕緣薄膜40、金屬襯墊50、60及80及測試襯墊70之至少部分。在圖案化在金屬襯墊50、60及80與測試襯墊70之間的鈍化層90後，可部分移除第二層間絕緣薄膜40之部分41及42。
在根據該實例之第一半導體晶粒100及第二半導體晶粒200中，這些晶粒可形成於測試襯墊70所位於的劃線110之相對側上，鈍化層90保持如原先一樣僅形成於晶粒中，且鈍化層90a之一部分保留於劃線110中之測試襯墊70上。鈍化層90a可保持部分形成於測試襯墊70上，以便保護測試襯墊70之表面免遭後續蝕刻製程。
關於移除根據該實例之鈍化層，本申請案之鈍化蝕刻遮罩可自典型鈍化蝕刻遮罩稍微調整。因此，用於半導體晶粒之現有製造方法可適用的。
圖3為在鈍化層90之圖案化後的晶圓之實例之橫截面圖。
參看圖3，在根據該實例之晶圓1000中，可完全移除測試襯墊70上之鈍化層90。因此，在第一半導體晶粒100與第二半導體晶粒200之間的區域中不存在鈍化層90。因此，進一步簡化了該製程。
當移除劃線110中之鈍化層90時，可在第二層間絕緣薄膜40之區310及320中進一步蝕刻第二層間絕緣薄膜40。經蝕刻區310及320可比圖2中之經蝕刻區41及42寬。
圖4為在形成凸塊後的晶圓之實例之橫截面圖。
如在圖4中所例示，根據該實例，可使用金材料或類似材料使第一金屬凸塊210及第二金屬凸塊220分別形成於半導體晶粒100、200上。安置於根據該實例之半導體晶粒100、200上的第一金屬凸塊210及第二金屬凸塊220可隨後藉由在COF封裝製程期間形成於聚醯亞胺上之Cu導線相互連接。金屬凸塊210及220可經形成使得其直接連接至金屬襯墊50及80。雖未在圖4中展示，但在一實例中，亦可形成金屬凸塊，使得其直接連接至金屬襯墊60。由於在金屬襯墊50及80上移除了鈍化層90，因此連接係可能的。
圖5為在第一雷射開槽製程後的晶圓之實例之橫截面圖。
使用多個雷射光源510及520之第一雷射開槽製程可實施於根據該實例之晶圓1000上。可藉由第一雷射開槽製程形成溝槽。關於部分蝕刻之第二層間絕緣薄膜41及42（圖4）可實施第一雷射開槽製程。在正在實施雷射開槽製程之區中，可藉由此製程完全移除第二層間絕緣薄膜40。另外，可移除低介電絕緣薄膜20之一部分。
因此，第二層間絕緣薄膜40及低介電絕緣薄膜20可經部分移除以形成具有具體深度之第一凹槽530及第二凹槽540。第二層間絕緣薄膜40及低介電絕緣薄膜20可被雷射照射，且藉由雷射產生之熱而溶解。
根據該實例之第一雷射開槽製程可使用具有窄脈衝寬度之多個雷射光源510及520，使得可同時形成具有小寬度之多個凹槽530及凹槽540。
可藉由雷射光輕易移除在根據該實例之晶圓1000中之第二層間絕緣薄膜40。另外，可包括諸如SiOC之碳原子的低介電絕緣薄膜20可更容易地藉由雷射光移除。雷射脈衝以聚焦於晶圓表面上來照射。雷射脈衝可連續地吸收至低介電絕緣薄膜內，且可在吸收了某一級別之熱能後即刻將低介電絕緣薄膜蒸發。
兩個淺凹槽530及540可形成於劃線110中。用於形成兩個凹槽之原因為有效地將第一半導體晶粒100與第二半導體晶粒200隔離。
另一原因係因為與使用具有較大脈衝寬度之雷射光源相比，使用具有較小脈衝寬度之雷射光源的第一開槽可減小對矽半導體晶粒100、200之影響或裂縫。使用具有非常高能量之雷射光源執行第一雷射開槽製程可易於損壞半導體晶粒100、200。因此，較佳的方式是，第一開槽製程使用具有低能量的較小脈衝寬度之雷射光源。
在一實例中，在此階段，小矽碎片550可形成於半導體晶粒100、200中。如上所提到，可產生與矽元素及諸如銅或鋁之金屬成分組合的衍生物（一種矽碎片）。
圖6為在第二雷射開槽製程後的晶圓之實例之橫截面圖。
參看圖6，根據該實例之晶圓1000可使用第二雷射光源610執行第二雷射開槽製程。可藉由第二雷射開槽製程移除形成於基板10上之低介電絕緣薄膜20。可暴露矽基板10。
第二雷射開槽製程為使用雷射在藉由第一雷射開槽製程形成之兩個凹槽530與540（圖5）之間實施的開槽製程。由於這些凹槽可最初已藉由第一雷射開槽製程形成，因此可在一定程度上易於製作額外凹槽。可使用具有比用於第一雷射開槽製程之脈衝寬度大的寬度之光源，因為應移除第一凹槽530及第二凹槽540兩者。
在此階段，可藉由在根據該實例之晶圓1000中之雷射開槽製程使矽碎片650形成得較大。根據該實例之晶圓1000之測試圖案包括銅金屬、鋁金屬及在低介電絕緣薄膜20中之類似金屬。當此等材料熔解時，可藉由組合低介電絕緣薄膜20中之矽材料來形成矽碎片650。
若矽碎片含有金屬成分（諸如，Si-Cu、Si-Al或Si-Cu-Al），則矽碎片可具有傳導性。亦即，矽碎片650可包括諸如銅或鋁之金屬成分。因此，矽碎片650可形成於第二層間絕緣薄膜40之側表面上，及藉由雷射開槽蝕刻的低介電絕緣薄膜20之側表面上，且可經形成以延伸至第二層間絕緣薄膜40之上表面。雷射開槽製程幫助可容易地移除低介電常數絕緣薄膜20之脆性區域。
圖7為在雷射開槽製程後的晶圓之實例之橫截面圖。
參看圖7，可藉由根據該實例之第一及第二雷射開槽製程暴露晶圓1000中之矽基板10。藉由雷射開槽製程形成之矽碎片750可保留於第二層間絕緣薄膜40之上表面及側表面上。具有最大高度T1之矽碎片750產生於藉由雷射開槽製程蝕刻的第二層間絕緣薄膜40之側表面及低介電絕緣薄膜20之側表面上，且可經形成以延伸至第二層間絕緣薄膜40之上表面。
在開槽製程後，可使用多個金剛石刀片710及720執行鋸切製程。
圖8A為在第一鋸切製程後的晶圓之實例之橫截面圖。
在執行雷射開槽製程後，可進行刀片切塊製程。在此實例中，可防止由刀片切塊製程引起的半導體晶粒100、200之裂開。
可藉由移除矽基板10（藉由使用金剛石刀片或類似裝置）來形成半導體晶粒100、200。亦即，可對藉由第一及第二雷射開槽製程形成之凹槽執行機械鋸切以形成個別第一半導體晶粒100及第二半導體晶粒200。
金剛石刀片切塊製程可作為第一切塊製程及第二切塊製程執行。可在比雷射開槽大之深度處執行使用該刀片之鋸切製程。在實施鋸切製程前，可將膠帶811附著至矽基板10之底表面。
第一刀片切塊製程可使用具有一寬的寬度之第一金剛石刀片710執行。因此，可藉由第一刀片切塊製程蝕刻矽基板10之一部分。
圖8B為在第二鋸切製程後的晶圓之實例之橫截面圖。
參看圖8B，可使用可具有比第一刀片窄之寬度的第二金剛石刀片720執行第二刀片切塊製程。可藉由第二刀片切塊製程蝕刻其餘矽基板10。結果，可將金剛石刀片延伸至附著至基板10之底表面的膠帶811。
圖9為在各向異性傳導性黏著劑（ACF）結合製程後的半導體晶粒之實例之橫截面圖。
ACF結合製程為主要用於使用各向異性傳導性黏著劑及撓曲箔將顯示器連接至PCB之互連技術。ACF結合主要用以在組件之間創造可撓性連接，諸如對LCD的撓曲箔及對PCB的撓曲箔。使用各向異性傳導性薄膜（ACF）在兩個組件之間創造機電連接。當施加熱及壓力時，薄膜中之傳導性粒子僅在Z方向上接觸。需要最小接觸時間以恰當地確保黏著性固化。
根據該實例之ACF結合製程將IC晶片之凸塊實體連接至形成於可撓性聚醯亞胺薄膜（COF薄膜）上之輸入/輸出電線圖案810。為了執行根據該實例之ACF結合製程，製備包括多個輸入/輸出電線圖案810之可撓性薄膜800。藉由使用包括具有第一尺寸之傳導性球910及930之各向異性傳導性薄膜，將形成於個別半導體晶粒100上之凸塊210附著至輸入/輸出電線圖案810。歸因於按壓製程，傳導性球之尺寸可變得比原始尺寸930還小的910。
輸入/輸出電線圖案810可由銅組件製成。然而，此僅為一實例，且輸入/輸出電線圖案可由不同於銅之組件製成。輸入/輸出電線圖案810亦叫作導線。凸塊210可包含多個凸塊，且可藉由輸入/輸出電線圖案810相互連接。鍍鎳粒子可由ACF傳導性球910形成，且絕緣塗層可形成於ACF傳導性球910之外側上。ACF傳導性球910可與凸塊210合作將半導體晶粒100與可撓性薄膜800電連接。可藉由將凸塊210朝向COF薄膜800按壓來壓碎在凸塊210附近之ACF傳導性球910。因此，鍍鎳粒子可經暴露以電連接半導體晶粒100與可撓性薄膜800。在其他區域中之ACF傳導性球930可在ACF結合製程期間向外逸散。
在根據該實例之ACF結合製程期間，輸入/輸出電線圖案810與矽碎片750之間的空間S1可保證比傳導性球930之尺寸大的非常寬空間S1，使得傳導性球930可經由輸入/輸出電線圖案810與個別半導體晶粒100之間的空間逸散。
矽碎片750距層間絕緣薄膜20、40之經蝕刻頂表面之最大高度H1應盡可能地低，以便確保輸入/輸出電線圖案810與矽碎片750之間的空間S1足夠容納各種尺寸之傳導性球930。因此，矽碎片750與輸入/輸出電線圖案810之間的空間S1應寬。保證空間S1可使ACF傳導性球穿過空間S1。因此，矽碎片750距層間絕緣薄膜20或40之經蝕刻頂表面之最大高度應減小以允許在ACF結合製程期間在矽碎片750與輸入/輸出電線圖案810之間的足夠空間。因此，ACF傳導性球930可易於在ACF結合製程期間向外移動。
晶圓1000包括矽基板10。第一層間絕緣薄膜20可形成於矽基板10上。第一層間絕緣薄膜20可具有低於3.0之低介電常數。第二層間絕緣薄膜40可形成於第一層間絕緣薄膜20上。鈍化層90可形成於第二層間絕緣薄膜40之上表面上，及金屬襯墊50之至少上表面及側表面上。金屬襯墊50可部分由鈍化層90圍封。鈍化層90可為單一氮化矽薄膜或堆疊氮化矽/氧化矽薄膜。如先前在圖2A及圖2B中例示，金屬襯墊50、60及80之上部部分可部分打開，且金屬凸塊210可電連接至金屬襯墊50。半導體晶粒100亦可具有密封環區域，其防止應力及水分或類似元素在晶粒與劃線之間的方向上穿透至IC晶片內。
藉由雷射開槽製程產生之矽碎片750可形成達距第一層間絕緣薄膜20及第二層間絕緣薄膜40之上表面一預定高度。亦即，在一實例中，矽碎片750之高度可藉由蝕刻在密封環區域附近之鈍化層90及第二層間絕緣薄膜40來降低。此保證足夠空間S1以易於移出ACF傳導性球930。
在鈍化蝕刻製程期間，第二層間絕緣薄膜40之一部分可經過度蝕刻，直至移除形成於金屬襯墊上的預定量之鈍化層。亦在典型製造方法中使用鈍化蝕刻遮罩來執行鈍化層90之移除。因此，可容易藉由改變鈍化蝕刻遮罩中之遮罩圖案來應用這些實例。
如上所述，當在移除鈍化層90後進行至劃線110內之雷射開槽製程時，可自第二層間絕緣薄膜40之上表面形成矽碎片750。可降低矽碎片750或矽殘渣750之最大高度H1，因為這些矽碎片可自第二層間絕緣薄膜40之經過度蝕刻之表面開始形成。若自鈍化層90之表面開始形成矽碎片，則可升高矽碎片750或矽殘渣750之頂表面，此與本實例不同。換言之，在本實例中，矽碎片750之高度可按至少鈍化層90之厚度來降低。因此，保證凸塊210之頂部與矽碎片750之間的空間S1。
在於密封環區域120附近移除鈍化層90後，可在雷射開槽製程期間自層間絕緣薄膜40之上表面產生矽碎片750。因此，若鈍化層90之厚度為3.5 μm，則將矽碎片750之最大高度減小3.5 μm。
若凸塊210之頂部與矽碎片750之間的空間S1為大約5.5 μm，則可容易地移動具有尺寸約3 μm之直徑的ACF傳導性球930。因此，可防止短路問題。
在一實例中，在半導體晶粒100中，矽碎片750之頂表面可低於凸塊210之頂表面。由於鈍化層90經過度地蝕刻，因此可暴露第二層間絕緣薄膜40。根據該實例之矽碎片750可至少部分形成於第二層間絕緣薄膜40上。該矽碎片750之底表面可定位低於該鈍化層90之底表面。該矽碎片750之底表面可定位成低於該凸塊210之底表面。該矽碎片750之最大高度可小於凸塊210之厚度之一半。
亦即，在雷射開槽製程期間，將雷射束之熱能轉移至晶圓1000。晶片中之金屬佈線、絕緣薄膜及矽材料可藉由雷射束之熱能溶解，使得在雷射開槽期間，矽碎片或毛邊按某一高度產生。如上所述，矽殘渣、矽碎片、毛邊及類似者（下文被稱作「矽碎片」）可形成於鈍化層90上。若在隨後製程期間未減小矽碎片750之高度或厚度，則可出現短路問題。
將雷射束照射至經移除鈍化層90之劃線110。在鄰近雷射開槽區域的第二層間絕緣薄膜40之上表面上，矽碎片750可按某一高度形成。在此時，矽碎片750可不自鈍化層90開始形成，而可自第二層間絕緣薄膜40之上表面上開始形成。隨著鈍化層90之厚度增大，可按鈍化層90之厚度來降低矽碎片750之頂表面。
圖10為在ACF球結合製程後的半導體晶粒之另一橫截面圖之一實例。
如在圖10中所例示，當產生矽碎片750時，矽碎片750可導致輸入/輸出電線圖案810與矽碎片750之間的窄空間S2。因此，ACF傳導性球930可能不能夠逸散至外面，且反而可聚集於在碎片750附近之區域中，從而導致短路問題。
以上提到之問題可以發生於將凸塊210、220附著至輸入/輸出電線圖案810之ACF結合製程期間，當在劃線110之端部處自鈍化層90之上表面形成矽碎片750於某一高度H2之時。
在ACF結合製程期間，ACF傳導性球930中之一些可被俘獲於矽碎片750與輸入/輸出電線圖案810之間的窄空間S2中。由於ACF傳導性球930為傳導性，且形成矽碎片750與輸入/輸出電線圖案810之間的橋，因此可導致短路故障。
當矽碎片750之高度H2大於一合乎需要之臨限值時，此問題發生。此高度H2可創造矽碎片750與輸入/輸出電線圖案810之間的窄空間。確保空間S2以使ACF傳導性球穿過空間S2。因此，應減小矽碎片750之最大高度，以便在ACF結合製程期間創造矽碎片750與輸入/輸出電線圖案810之間的足夠空間。此將允許ACF傳導性球930易於在ACF結合製程期間向外移動。
通常，鈍化層90保持在劃線中的同時，藉由雷射開槽製程照射雷射束。因此，矽碎片750自鈍化層90形成。
圖11為在圖案化具有增大之厚度的鈍化層90後的晶圓之一實例之橫截面圖。
參看圖11，某一厚度之層間絕緣薄膜20、40可形成於矽基板10上。層間絕緣薄膜20、40包括在作用區域(active region)上之低介電絕緣薄膜20。
金屬襯墊50、60及80可形成於層間絕緣薄膜40之上部部分上。鈍化層90可經形成以具有某一厚度以覆蓋金屬襯墊50、60及80。金屬襯墊50及80可經由上部部分局部打開之鈍化層90電連接至凸塊210、220。雖未在圖11中圖示，但金屬襯墊60亦可電連接至凸塊210、220。
半導體晶粒300、400為整合電子電路之IC晶片。劃線110隔離晶粒300、400。密封環區域可形成於晶粒300、400與劃線110之間。
鈍化層90可形成為比典型鈍化層還厚一厚度P。當按一預定厚度形成鈍化層90時，可基於鈍化層90之厚度使凸塊210之厚度形成得較高。在圖11中，P例示了鈍化層90之厚度形成得較厚並且凸塊210及220之高度增大了等於鈍化層90之增大厚度的一厚度P' 210a及220a之狀態。
圖12為在雷射開槽製程後的半導體晶粒之一實例之橫截面圖。
在圖12中，藉由雷射開槽製程形成於第二層間絕緣薄膜40上之矽碎片750可形成在比鈍化層90還低之位置處。即使矽碎片750經形成具有高於5 μm之高度（其為在雷射開槽製程中大致展示之高度），鈍化層90之較大厚度可輕易確保用於ACF傳導性球930移動之足夠空間。
可基於矽碎片750之高度恰當地調整鈍化層90之厚度。另外，可藉由利用現有半導體製造製程，而不利用額外製程，來進行鈍化層90之變厚。
替代使凸塊220之高度較大，凸塊220可較厚地形成。然而，因為可使用金（Au），金為構成凸塊220之貴重材料，所以使凸塊220變厚就成本而言效率低下。另外，若改變凸塊220之高度，則關於後續製程，可因凸塊220引起各種問題。
因此，本實例形成比典型鈍化層90厚之鈍化層90，以便提供增大凸塊220之高度而非使凸塊220變厚之效應。
如上所述，這些實例可完全移除在密封環區域120附近或在劃線區域110中之鈍化層90，使得矽碎片750可自層間絕緣薄膜40且非自在雷射開槽製程期間之現有鈍化層形成。因此，凸塊220之頂部與矽碎片750之間的空間可經形成得比ACF傳導性球930之尺寸足夠大，使得ACF傳導性球930可自由地移動。
根據這些實例之半導體晶粒之製造及封裝方法，可移除經提供以區分半導體晶粒中之IC晶片的劃線區域110中之鈍化層。
此外，在這些實例中，鈍化層之厚度可形成為比典型鈍化層大，以便提供增大凸塊之高度的效應。
因此，當執行用於使用雷射束輻照劃線之雷射開槽製程時，由於矽碎片係自劃線中的層間絕緣薄膜之上表面形成，因此凸塊210、220與矽碎片750之間的空間可形成為比ACF傳導性球之直徑大。
因此，ACF傳導性球可在ACF結合製程期間自由地移動，且可防止ACF傳導性球在除了凸塊所在之區之外的區中破壞，使得可消除短路故障且改良產品效能。
亦即，以上實例將顯示器IC描述為一實例，但其亦可充分地應用於劃線結構應用於之各種裝置，諸如，IGBT、MOSFET、TR及二極體晶圓。
雖然本揭露內容包括具體實例，但在理解本申請案之揭露內容後，將顯而易見，在不脫離申請專利範圍及其等效內容之精神及範圍之情況下，可在此等實例中進行形式及細節之各種改變。本文中描述之實例應僅按描述性意義來考慮，且並非用於限制之目的。在每一實例中的特徵或態樣之描述應被考慮為可適用於其他實例中之類似特徵或態樣。若按不同次序執行描述之技術，及/或若按不同方式組合在描述之系統、架構、裝置或電路中的組件及/或這些組件由其他組件或其等效物替換或補充，則可達成合適結果。因此，本揭露內容之範圍不由詳細描述定義，而是由申請專利範圍及其等效內容定義，且應將在申請專利範圍及其等效內容之範圍內的所有變化解釋為包括於本揭露內容中。
10:半導體基板 20:低介電絕緣薄膜/第一層間絕緣薄膜 30:金屬佈線 30f:最後金屬佈線 40:第二層間絕緣薄膜 41:經蝕刻區/部分蝕刻之第二層間絕緣薄膜 42:經蝕刻區/部分蝕刻之第二層間絕緣薄膜 45:通路 50:金屬襯墊 60:金屬襯墊 70:測試襯墊 80:金屬襯墊 90:鈍化層 90a:鈍化層 100:第一半導體晶粒 110:劃線 120:密封環區域 130:密封環區域 200:第二半導體晶粒 210:第一金屬凸塊 210a:凸塊 220:第二金屬凸塊 220a:凸塊 300:半導體晶粒 310:經蝕刻區 320:經蝕刻區 400:半導體晶粒 510:雷射光源 520:雷射光源 530:凹槽 540:凹槽 550:矽碎片 610:第二雷射光源 650:矽碎片 710:第一金剛石刀片 720:第二金剛石刀片 750:矽碎片 800:可撓性薄膜 811:膠帶 810:輸入/輸出電線圖案 910:ACF傳導性球 930:ACF傳導性球 1000:晶圓 T1:最大高度 H1:最大高度 H2:高度 S1:空間 S2:空間 P:厚度 P':厚度
圖1為根據一或多個實施例的晶圓之實例之橫截面圖。
圖2A及圖2B例示根據一或多個實施例的在圖案化鈍化層後的晶圓之實例之橫截面圖。
圖3為根據一或多個實施例的在圖案化鈍化層後的晶圓之實例之橫截面圖。
圖4為根據一或多個實施例的在形成凸塊後的晶圓之實例之橫截面圖。
圖5為根據一或多個實施例的在第一雷射開槽後的晶圓之實例之橫截面圖。
圖6為根據一或多個實施例的在第二雷射開槽後的晶圓之實例之橫截面圖。
圖7為根據一或多個實施例的在開槽後的晶圓之實例之橫截面圖。
圖8A為根據一或多個實施例的在第一鋸切製程後的晶圓之實例之橫截面圖。
圖8B為根據一或多個實施例的在第二鋸切製程後的晶圓之實例之橫截面圖。
圖9為根據一或多個實施例的在ACF結合製程後的半導體晶粒之實例之橫截面圖。
圖10為根據一或多個實施例的在半導體晶粒附著至導線後的該半導體晶粒之實例之另一橫截面圖。
圖11為根據一或多個實施例的在圖案化具有增大厚度之鈍化層後的晶圓之實例之橫截面圖。
圖12為根據一或多個實施例的在雷射開槽製程後的半導體晶粒之實例之橫截面圖。
遍及這些圖式及詳細描述，除非另有描述或提供，否則應理解相同圖式元件符號指相同元件、特徵及結構。這些圖式可不按比例，且圖式中的元件之相對尺寸、比例及描繪可為了清晰、例示及方便而被誇大。
10:半導體基板
20:低介電絕緣薄膜/第一層間絕緣薄膜
30:金屬佈線
30f:最後金屬佈線
40:第二層間絕緣薄膜
41:經蝕刻區/部分蝕刻之第二層間絕緣薄膜
42:經蝕刻區/部分蝕刻之第二層間絕緣薄膜
45:通路
50:金屬襯墊
60:金屬襯墊
70:測試襯墊
80:金屬襯墊
90:鈍化層
90a:鈍化層
100:第一半導體晶粒
110:劃線
120:密封環區域
130:密封環區域
200:第二半導體晶粒
210:第一金屬凸塊
220:第二金屬凸塊
1000:晶圓

Claims (12)

  1. 一種半導體晶粒之製造及封裝方法，其包含： 製備具有密封環區域之晶圓； 在該晶圓上形成第一層間絕緣薄膜； 在該第一層間絕緣薄膜中形成金屬佈線； 在該第一層間絕緣薄膜上形成第二層間絕緣薄膜； 在該第二層間絕緣薄膜上形成金屬襯墊； 在這些金屬襯墊上形成鈍化層； 移除該鈍化層之在鄰近該密封環區域之一區域中的一部分以暴露該第二層間絕緣薄膜； 蝕刻該第二層間絕緣薄膜之一部分； 在這些金屬襯墊上形成凸塊； 藉由雷射開槽製程移除在鄰近該密封環區域之該區域中的該第一層間絕緣薄膜及該第二層間絕緣薄膜；及 將該晶圓切塊成第一半導體晶粒及第二半導體晶粒。
  2. 如請求項1所述之方法，其進一步包含： 製備具有輸入電線圖案及輸出電線圖案之可撓性薄膜；及 藉由傳導性球將該凸塊附著至這些輸入電線圖案及這些輸出電線圖案中之至少一者。
  3. 如請求項1所述之方法，進一步包含： 自該雷射開槽製程產生矽碎片， 其中該矽碎片係自該第二層間絕緣薄膜之頂表面開始形成。
  4. 如請求項3所述之方法， 其中該矽碎片之高度按該鈍化層之厚度來降低。
  5. 如請求項1所述之方法， 其中該雷射開槽製程包含第一雷射開槽製程及第二雷射開槽製程，且 其中該第二雷射開槽製程之脈衝寬度大於該第一雷射開槽製程之脈衝寬度。
  6. 如請求項1所述之方法， 其中該第一層間絕緣薄膜之介電常數低於3.0，且該第一層間絕緣薄膜之該介電常數低於該第二層間絕緣薄膜之介電常數。
  7. 一種半導體晶粒之製造及封裝方法，其包含： 製備具有劃線及密封環區域之晶圓； 在該晶圓上形成層間絕緣薄膜、金屬佈線及金屬襯墊； 在這些金屬襯墊及該層間絕緣薄膜上形成鈍化層； 蝕刻該鈍化層； 暴露這些金屬襯墊之一部分； 蝕刻該層間絕緣薄膜； 在這些金屬襯墊上形成凸塊； 執行雷射開槽製程以在鄰近該密封區域之經蝕刻的該層間絕緣薄膜上產生矽碎片； 藉由該雷射開槽製程移除該劃線中之該層間絕緣薄膜；及 將該晶圓切塊以形成該半導體晶粒。
  8. 如請求項7所述之方法， 其中該層間絕緣薄膜包含第一層間絕緣薄膜及第二層間絕緣薄膜， 其中該第一層間絕緣薄膜之介電常數值小於該第二層間絕緣薄膜之介電常數值， 其中該金屬佈線包含銅成分， 其中該金屬襯墊包含鋁成分，且 其中該鈍化層包含氮化矽薄膜。
  9. 如請求項7所述之方法， 其中在鄰近該密封環區域之一區域中移除該鈍化層之一部分，且在鄰近該凸塊之一區域中維持該鈍化層之一部分。
  10. 如請求項7所述之方法， 其中該矽碎片之底部按該鈍化層之厚度來降低。
  11. 一種半導體晶粒之製造及封裝方法，其包含： 在基板上形成第一層間絕緣薄膜； 在該第一層間絕緣薄膜上形成第二層間絕緣薄膜； 在該第二層間絕緣薄膜上形成金屬襯墊； 在這些金屬襯墊上形成鈍化層； 移除該鈍化層之一部分以暴露該第二層間絕緣薄膜； 在這些金屬襯墊上形成凸塊； 藉由雷射開槽製程過度蝕刻該第二層間絕緣薄膜之一部分及該第一層間絕緣薄膜之一部分；及 自該雷射開槽製程產生矽碎片， 其中該矽碎片形成於該第二層間絕緣薄膜之過度蝕刻部分之上表面上，且 其中該矽碎片之底表面定位低於該鈍化層之底表面，且該矽碎片之頂表面低於該凸塊之頂表面。
  12. 如請求項11所述之方法，其中該矽碎片之底表面定位低於該凸塊之底表面。
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