TWI721568B - 堆疊半導體元件及其製造方法 - Google Patents

堆疊半導體元件及其製造方法 Download PDF

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TWI721568B
TWI721568B TW108134474A TW108134474A TWI721568B TW I721568 B TWI721568 B TW I721568B TW 108134474 A TW108134474 A TW 108134474A TW 108134474 A TW108134474 A TW 108134474A TW I721568 B TWI721568 B TW I721568B
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substrate
side wall
wafer
trench
layer
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TW108134474A
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TW202022937A (zh
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呂宗興
何軍
朱立寰
曹佩華
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台灣積體電路製造股份有限公司
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Abstract

一種方法包括：提供第一及第二晶圓；在第一晶圓的頂部中形成第一元件層；在第二晶圓的頂部中形成第二元件層；在第一元件層中形成第一溝槽；在第二元件層中形成第二溝槽；在形成第一及第二溝槽的至少一個之後，將第一及第二晶圓結合在一起；以及藉由切割製程切割結合的第一及第二晶圓，其中切割製程切穿第一及第二溝槽。

Description

堆疊半導體元件及其製造方法
本揭露是關於一種堆疊半導體元件及其製造方法。
積體電路(IC)工業已經歷指數增長。IC材料及設計的技術進展已產生數代IC，其中與前代相比，每代具有更小且更複雜的電路。在IC發展過程中，功能密度(亦即，單位晶片面積互連元件的數量)大體已增加而幾何大小(亦即，可以使用製造製程產生的最小部件(或接線))已減小。此按比例縮小製程大體藉由增加生產效率並降低相關成本來提供益處。
隨著半導體技術進一步進展，堆疊半導體元件(例如，3D積體電路(3D integrated circuits；3D-ICs))已經展現出進一步減小半導體元件的實體大小的有效替代方案。在堆疊半導體元件中，晶圓/晶粒在彼此頂部上堆疊並且使用貫穿連接來互連，諸如貫穿基板通孔(through-silicon-via或through-substrate-via； TSV)。例如，若在組裝之前分別測試單獨晶粒，則3D-IC的一些益處包括呈現較小佔地面積、藉由減少訊號互連的長度來減少功率消耗、以及改進良率及製造成本。然而，存在與切割堆疊半導體結構相關聯的挑戰。切割係將含晶片半導體結構(例如，晶圓上晶圓(wafer-on-wafer)結構)切成單獨晶粒的製程。機械切割(諸如使用鋸或刀刃)或雷射切割已經用於分割晶粒的行業中。當僅依賴於機械切割時，在機械切割期間的熱及機械應力可導致基板晶格畸變(distortion)並且在含電路的層中產生裂痕，這被稱為矽剝離(silicon peeling)。當僅依賴於雷射切割時，雷射輻射可產生矽碎屑，從而導致對晶粒側壁的污染。因此，需要一種在基本上不引起矽剝離和矽碎屑的情況下切割堆疊半導體元件的方法。
根據本揭露之一實施方式，提供一種堆疊半導體元件的製造方法，包含提供第一晶圓及第二晶圓；在第一晶圓的頂部中形成第一元件層；在第二晶圓的頂部中形成第二元件層；在第一元件層中形成第一溝槽；在第二元件層中形成第二溝槽；在形成第一溝槽及第二溝槽的至少一個之後，將第一晶圓及第二晶圓結合在一起；以及藉由切割製程切割結合在一起的第一晶圓及第二晶圓，其中切割製程切穿第一溝槽及第二溝槽。
根據本揭露之一實施方式，提供堆疊半導體元件的製造方法，包含提供第一結構，其具有第一基板及在第一基板上的第一元件層；提供第二結構，其具有第二基板及在第二基板上的第二元件層；在第二元件層中形成第二溝槽；將第一基板的底表面結合到第二元件層的頂表面；在結合之後，在第一元件層中形成第一溝槽；以及按順序切穿第一溝槽、第一基板、第二溝槽、及第二基板。
根據本揭露之一實施方式，提供一種堆疊半導體元件，包含第一基板、第一元件層、及材料層。第一基板具有第一側壁。第一元件層在第一基板上，具有第二側壁，其中第二側壁的表面粗糙度大於第一側壁的表面粗糙度。材料層結合到第一元件層，其中第一元件層包括第一導電特徵，第一導電特徵電氣耦接到材料層中的第二導電特徵。
10:方法
12:操作
14:操作
16:操作
24:操作
32:操作
34:操作
36:操作
38:操作
42:操作
100:第一元件
102:基板
104:元件層
106:全晶片區域
108:刻劃通道區域
110:電晶體
114:多層互連(MLI)
116:金屬襯墊
120:溝槽
124:漸縮側壁
126:切割切口
128:側壁
130:凹面
134:濾色器
138:凹槽
140:貫穿矽通孔(TSV)
142:結合線
146:貫穿矽通孔(TSV)
148:金屬襯墊
152:焊料凸塊
200:第二元件
202:基板
204:元件層
300:晶粒/半導體積體電路
302:區域
304:區域
D:寬度
D1、D1/2、D2、D2/2:深度
H:高度
R1、R2:表面粗糙度
S1、S2:斜率
T1、T2:厚度
W1、W2:
α:角度
當結合隨附圖式閱讀時，自以下詳細描述將很好地理解本揭示之實施方式。應注意，根據工業中的標準實務，各個特徵並非按比例繪製，並且僅出於說明目的而使用。事實上，出於論述清晰之目的，可任意增加或減小各個特徵之尺寸。
第1A圖、第1B圖、及第1C圖圖示了根據本揭示之一實施方式的各個態樣的用於製造堆疊半導體元件的示例性方法的流程圖。
第2圖、第3圖、第4圖、第5圖、第6圖、第7圖、第8A圖、第9圖、第10圖、第11圖、第12圖、第13圖、第14圖、第15圖、第16圖、第17圖、第18圖、第19圖、第20圖、第21圖、及第22圖係根據本揭示之一實施方式的各個態樣的示例性元件的橫截面圖。
第8B圖及第8C圖圖示了根據本揭示之一實施方式的各個態樣的第8A圖中的示例性堆疊半導體元件的邊緣的斜率及表面粗糙度的特性。
以下揭示內容提供許多不同實施例或實例，以便實施本揭露之一實施方式的不同特徵。下文描述部件及佈置的具體實例以簡化本揭示之一實施方式。當然，此等僅為實例且並不意欲為限制性。例如，以下描述中在第二特徵上方或第二特徵上形成第一特徵可包括以直接接觸形成第一特徵及第二特徵的實施例，且亦可包括在第一特徵與第二特徵之間形成額外特徵以使得第一特徵及第二特徵可不處於直接接觸的實施例。
此外，本揭示之一實施方式可在各個實例中重複元件符號及/或字母。此重複係出於簡便性及清晰的目的且本身並不指示所論述的各個實施例及/或構造之間的關係。此外，在下文本揭示之一實施方式中在另一特徵上、連接到另一特徵、及/或耦接到另一特徵而形成特徵可包括以直接接觸形成特徵的實施例，且亦可包括插入此等特徵中而 形成額外特徵以使得此等特徵可不處於直接接觸的實施例。此外，空間相對性術語，例如，「下部」、「上部」、「水平」、「垂直」、「之上」、「上方」、「之下」、「下方」、「上」、「下」、「頂部」、「底部」等以及其衍生詞(例如，「水平地」、「向下地」、「向上地」等)係為了方便一個特徵與另一特徵的關係的本揭示之一實施方式而使用。空間相對性術語意欲涵蓋包括特徵的元件的不同定向。再者，除非另外聲明，當用「約」、「大約」、及類似者描述一數量或數量範圍時，此術語意欲涵蓋在所描述數量的+/- 10%內的數量。例如，術語「約5nm」涵蓋從4.5nm至5.5nm的尺寸範圍。
在完成堆疊半導體製造之後，結合製程將第一晶圓實體地接合到第二晶圓，從而產生晶圓上晶圓結構。晶圓上晶圓結構包括藉由刻劃通道分離的較大數量的重複半導體元件。各種技術用於將已處理晶圓沿著刻劃通道分為單獨晶粒，其中每個晶粒表示特定半導體晶片。目前在工業中採用的風行晶圓切割技術包括機械切割及雷射切割。
機械切割採用鋸切製程，諸如使用金剛石刀刃或金剛石刀刃鋸。在機械切割為單一化晶粒期間，完全切穿刻劃通道。或者，刻劃通道可在機械切割(亦即，預裂痕製程)期間實質上切穿，接著沿著預裂痕的刻劃通道機械裂開為以單一化晶粒。鋸切製程沿著切割的邊緣餘留微裂痕。此等裂痕可以輕易地經由不期望的裂痕路徑在晶圓上傳播，亦稱為矽剝離，這可導致顯著元件破壞並且導致元件良率損 失。對具有微型晶粒大小的元件的晶圓而言，良率損失可變得日漸嚴重。伴隨鋸切操作的振動、剪切、及搖晃的影響可加劇裂痕及產生更多元件破壞及良率損失。此外，鋸或刀刃的實體尺寸限制晶圓上的刻劃通道的進一步縮放，這抑制按比例縮小晶圓上的刻劃通道尺寸的普遍趨勢，並且在阻礙在進階處理技術中為功能半導體元件呈現最大的可能晶圓面積。
另一方面，雷射切割採用高能雷射束及對刻劃通道的脈衝撞擊，從而毀壞晶圓結晶材料的微結構並且形成切割切口。當使用雷射切割時，高能雷射對晶圓表面的衝擊可在環境中產生大量晶圓材料顆粒，亦稱為矽碎屑。此等顆粒可再次沉積回晶圓上並且導致嚴重的顆粒污染。除此之外，由於晶圓結晶材料的局部高熱，高能雷射束亦可導致微裂痕。
本揭示之一實施方式涉及切割半導體元件的方法，並且更特定而言，涉及利用混合切割製程來切割堆疊半導體元件(諸如晶圓上晶圓結構)的方法。在一些實施例中，混合切割製程包括在結合之前雷射開槽及隨後接著機械切割。雷射開槽實質上限於元件層，而不進一步進入到矽基板中。由於元件層主要包括介電材料及金屬跡線，在雷射開槽期間將產生較少矽碎屑。同時，機械切割限於矽基板而不鋸切元件層，由此防止微裂痕從矽基板傳播到元件層中。由此，混合切割製程在切割堆疊半導體元件(諸如與習知晶圓切割方法相關聯的微裂痕及矽碎屑再次沉積)期間可顯著減 輕有害影響。由此，混合切割製程將減少切割有關的元件破壞並且改進產品良率。在論述如第1A圖至第22圖中例示的本揭示的各個實施例之後，此等及其他益處將變得明顯。
第1A圖、第1B圖、及第1C圖示出了根據一些實施例的用於切割堆疊半導體元件(諸如晶圓上晶圓結構)的方法10的流程圖。方法10僅係實例，並且不意欲將本揭示之一實施方式限制為超出在申請專利範圍中明確記載的內容。額外的操作可以在方法10之前、期間及之後提供，並且所描述的一些操作可以經替換、消除或前後移動來獲得本方法的額外實施例。方法10在下文結合第2圖至第22圖描述。第2圖至第22圖示出了在根據方法10的製造步驟期間堆疊半導體元件的各種橫截面圖及相關聯的邊緣輪廓。
在操作12中，方法10(第1A圖)提供了第一元件100(第2圖)、或具有此第一元件100。在一實施例中，第一元件100係晶圓，諸如具有300μm至約800μm的厚度以及約100、125、150、200mm或更大的直徑的硼摻雜矽晶圓。第一元件100包括基板102以及在基板102頂部形成的元件層104。基板102可係半導體基板，諸如矽或陶瓷基板。替代或額外地，半導體基板包括：元素半導體，包括鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP、或其組合。此外，基板102亦可係絕緣體上半導體(SOI)。
在一些實施例中，元件層104磊晶生長並且接著執行各種操作，例如，用於形成半導體元件的主動區域或感測區域。元件層104的厚度T1可以為約1.5μm至約30μm或更厚。為了簡化描述，將元件層104圖示為單層，但實際上，元件層104可包括其中形成主動元件的基板102上方的主動層、與形成功能電路的元件耦接的互連金屬層、以及覆蓋的保護性鈍化層。元件層104包括多個區域，此等區域包括複數個全晶片區域106及位於全晶片區域106的相鄰對之間的刻劃通道區域108。每個全晶片區域106構成半導體積體電路，此半導體積體電路將隨後沿著刻劃通道區域108中的刻劃通道被切割為單一晶片。在一些實施例中，半導體積體電路為感光IC，並且每個全晶片區域106包括感光區域。在一些進一步實施例中，半導體積體電路包括邏輯電路，並且每個全晶片區域106進一步包括電晶體區域及金屬化層。在一些實施例中，刻劃通道區域108亦包括金屬化層(未圖示)，此等金屬化層電氣耦接到半導體積體電路，這允許在切割之前偵測晶片缺陷。
仍參見第2圖，元件層104包括設置於其中及/或其上的各種特徵。例如，元件層104可包括各種電晶體，諸如電晶體110。在各個實施例中，電晶體110可係金屬氧化物半導體場效電晶體(MOSFET，諸如CMOS電晶體)、鰭式場效電晶體(FinFET)、雙極接面電晶體(BJT)、高壓電晶體、高頻電晶體、p通道及/或n通道場效電晶體(PFET/NFET)。
元件層104進一步包括耦接到電晶體110的多層互連(MLI)114。多層互連114包括各種導電特徵，此等導電特徵可係垂直互連(諸如觸點及/或通孔)及/或水平互連(諸如導電接線)。各種導電特徵包括導電材料，諸如金屬。在一實例中，可使用包括鋁、鋁/矽/銅合金、鈦、氮化鈦、鎢、多晶矽、金屬矽化物、或其組合的金屬，並且各種導電特徵可被稱為鋁互連。鋁互連可藉由包括物理氣相沉積(PVD)、化學氣相沉積(CVD)、或其組合的製程形成。用於形成各種導電特徵的其他製造技術可包括光微影處理及蝕刻以圖案化導電材料，用於形成垂直及水平連接。可實施其它製造製程以形成多層互連114，諸如實施熱退火以形成金屬矽化物。在多層互連中使用的金屬矽化物可包括矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀、或其組合。或者，各種導電特徵可係銅多層互連，此等銅多層互連包括銅、銅合金、鈦、氮化鈦、鉭、氮化鉭、鎢、多晶矽、金屬矽化物、或其組合。銅互連可藉由包括物理氣相沉積、化學氣相沉積、或其組合的製程形成。多層互連114不限於所描繪的導電特徵的數量、材料、大小、及/或尺寸，並且因此，多層互連114可包括任何數量、材料、大小、及/或尺寸的導電特徵，這取決於元件層104的設計需求。在所示出的實施例中，多層互連114進一步包括金屬襯墊116，此等金屬襯墊在元件層104的最上部分中形成。金屬襯墊116的橫向尺寸可以係約10μm至約200μm的數量級。
多層互連114的各種導電特徵設置在層間(或層級間)介電(ILD)層中。層間介電層可包括二氧化矽、氮化矽、氮氧化矽、TEOS氧化物、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、氟化石英玻璃(FSG)、碳摻雜的氧化矽、非晶氟化碳、聚對二甲苯、雙-苯并環丁烯(BCB)、聚醯亞胺、其他適宜材料、或其組合。層間介電層可具有多層結構。層間介電層可藉由包括旋轉塗佈、化學氣相沉積、濺鍍、或其他適宜製程的製程形成。在一實例中，多層互連114及層間介電層可在包括鑲嵌製程(諸如雙鑲嵌製程或單鑲嵌製程)的整合製程中形成。
在操作14中，方法10(第1A圖)提供第二元件200(第3圖)、或具有此第二元件200。與第一元件100不同，第二元件200為單獨製備。在一實施例中，第二元件200及第一元件100均為具有相同直徑的晶圓。第二元件200的各種材料組成、主動及被動區域、互連金屬層類似於上文參考第2圖中的第一元件100所述，並且將出於簡便緣故在下文簡單敘述。元件符號為了便於理解而重複。第二元件200包括基板202以及在基板202頂部形成的元件層204。基板202可係半導體基板，包括矽或其他適宜半導體材料。元件層204的厚度T2可以為約1.5μm至約30μm或更厚。元件層204包括多個區域，此等區域包括複數個全晶片區域106及位於全晶片區域106的相鄰對之間的刻劃通道區域108。每個全晶片區域106構成半導體積體電路，此半導體積體電路將隨後沿著刻劃通道區域108中的刻劃通道 被切割為單一晶片。全晶片區域106可包括電晶體區域及金屬化層，諸如多層互連114，以將電晶體110的信號通過金屬襯墊116向外部傳送。
在操作16中，方法10(第1A圖)形成複數個溝槽120，此等溝槽120穿過第一元件100的元件層104並且視情況進入到基板102的上部中(第4圖)。這些溝槽120沿著刻劃通道區域108形成，此等刻劃通道區域108對應於相鄰的一對半導體晶片之間的橫向邊界。在一些實施例中，操作16採用雷射束或脈衝以形成溝槽120，這亦稱為雷射開槽製程。在各個實施例中，雷射係固態雷射、釔鋁石榴石(YAG)雷射、釹-YAG雷射、或其他適當雷射。或者，開槽製程可使用與雷射不同的其他適宜的非機械切割方法，諸如電漿切割製程。藉由移除對全晶片區域106具有選擇性的刻劃通道區域108的中心部分或全部來貫穿元件層104形成溝槽120。換言之，刻劃通道區域108要能在不移除全晶片區域106的部分的情況下，提供足夠的寬度以供溝槽120形成。溝槽120的開口寬度W1可以為約5μm至約100μm或更寬。在一些實施例中，開口寬度W1為元件層104的厚度T1的約1.5至約10倍。在一具體實施例中，溝槽120具有約55μm的開口寬度W1以及約15μm的深度D1。溝槽120的底部可在基板102的頂表面處終止，或視情況略微延伸到基板102中。由此，深度D1可構成兩部分，第一部分係元件層104的厚度T1，並且第二部分係延伸到基板102中的溝槽120的底部的深度，其中第一部分(T1)與第二部分(D1-T1)的比率 可以為約5：1至約20：1，諸如約8：1。若T1/(D1-T1)大於約20：1，則這意味著延伸到基板102中的溝槽120的底部可以是淺(shallow)的，使得機械誤差可能導致一些其他溝槽沒有完全延伸穿過元件層104。若T1/(D1-T1)小於約5：1，則這意味著溝槽120的底部可能過深地延伸到基板102中，使得雷射輻射可產生過多的矽碎屑。穿過元件層104的雷射溝槽在後續切割操作中避免由刀鋸的機械或熱應力對此層的破壞。雷射溝槽亦實質上限於元件層104，此元件層避免由雷射輻射到基板102中導致的矽碎屑污染。
在形成溝槽120之後，待切割的半導體積體電路(亦即，全晶片區域106)的邊緣包含漸縮側壁124。漸縮側壁124基本上包括雷射開槽輪廓的一半(約減去後文待論述的機械切割的切割寬度)。漸縮側壁124從元件層104的頂表面延伸到基板102的頂表面或視情況在基板102的頂表面之下。漸縮側壁124可具有圓底或尖底。在漸縮側壁124的不同位置處的斜率可以變化。基準是在溝槽深度的一半(D1/2)處量測點P處的斜率，如第4圖所示。將斜率定義為穿過點P在基板102的頂表面與漸縮側壁124的切線之間形成的角度α的正切。在一些實施例中，角度α為約35°至約80°，諸如約45°。角度α被稱為由個別側壁形成的角度。漸縮側壁124的表面粗糙度(以RMS量測)表示為R1。在具體實例中，R1可以為約20nm至約100nm。如將在後文示出，雷射開槽輪廓的表面粗糙度經常大於機械切割輪廓的表面粗糙度，諸如在一些實施例中約為至少五倍。
在操作24中，方法10(第1A圖)形成複數個溝槽120，此等溝槽120穿過第二元件200的元件層204並且視情況進入到基板202(第5圖)的上部中。操作24的態樣實質上類似於如上文參考第4圖論述的操作16。為了便於理解，元件符號在第5圖中重複。類似地，在元件層204中溝槽120的深度D2可等於或略微大於元件層204的厚度T2。在深度D2的一半處的漸縮側壁124的角度α為約35°至約80°，諸如約45°。若角度α小於35°，開口寬度W1可以大於刻劃通道區域108可以提供的寬度。若角度α大於80°，則開口寬度W1可能過窄，而使機械切割工具(將在下文論述)無法在不觸碰漸縮側壁124的情況下通過。
在操作32中，方法10(第1A圖)藉由結合製程將第一元件100實體地(physically)接合到第二元件200以形成堆疊半導體元件。在第6圖中示出結合製程的一個實施例。在所示出的實施例中，將第二元件200翻轉，並且元件層204直接面對第一元件100的元件層104。在一實施例中，結合製程為熱壓結合(thermal compression)製程，由此將第一元件100及第二元件200放置在兩個熱板(未圖示)之間，並且施加熱及力以實體地結合兩個元件。在此種技術中，將兩個元件加熱至大於約150℃的溫度，諸如約350℃，同時施加在約1Mpa與約100Mpa之間(諸如約20Mpa)的壓力。在所示出的實施例中，第一元件100的溝槽120(下部溝槽)直接在第二元件200的溝槽120(上部溝槽)下方。未對準(Misalignment)可導致上部溝槽及下部溝槽的中心 位置橫向偏移。只要下部溝槽的一部分直接在上部溝槽的一部分下方，兩個溝槽的空間關係就仍稱為「直接在下方」。在結合之後，一對上部溝槽及下部溝槽接合並且形成從上部溝槽持續延伸到下部溝槽的較大孔隙。
或者，在結合製程的一實施例中，第一元件100的元件層104及第二元件200的元件層204對準並且經由金屬襯墊116結合在一起。結合的金屬襯墊116提供從第一元件層104到第二元件層204的訊號路徑。在一實施例中，結合媒介(諸如銅、鎢、銅錫合金、金錫合金、銦金合金、鉛錫合金、或類似者)施加在待結合的金屬襯墊116上的結合觸點之間。在進一步實施例中，結合製程可以為回焊製程。在此種製程中，在金屬襯墊116的位置處施加焊料，隨後將第一元件100及第二元件200放置在兩個熱板之間，並且將溫度升高到適宜溫度，使得焊料將回焊。此回焊將外部導體結合在一起。在又一實例中，結合製程可以為近紅外(NIR)回焊製程。在此製程中，可引導近紅外輻射而非引導加熱，以導致焊料回焊並且結合外部導體。除了熱壓接合之外，可替代地利用回焊製程、NIR回焊製程、或任何其他適宜的結合製程。
在操作42中，方法10(第1A圖)利用與雷射不同的切割技術(諸如機械切割)沿著刻劃通道區域108切割，以將結合的半導體結構分為兩個或多個晶粒300(第7圖)。在一些實施例中，機械切割採用鋸或刀刃(未圖示)以按順序切穿基板202、上部溝槽120、下部溝槽120、及 基板102。在一些替代實施例中，鋸或刀刃不完全切穿基板102，但接著執行機械開裂製程(mechanical cleaving process)以將結合的半導體元件斷裂為晶粒。鋸或刀刃可附接到固持馬達的殼體，該馬達驅動固定鋸或刀刃的轉子(rotor)。在特定實例中，機械切割採用圓形刀刃，該刀刃具有鎳金剛石切割表面。
在機械切割期間，並且在完全實體分離晶粒300之前，機械切割製程形成切割切口126，此切割切口126具有在其向溝槽120的開口處量測的寬度W2，此寬度W2小於溝槽120的開口的寬度W1。在一些實施例中，寬度W1為寬度W2的約兩倍至約二十倍，諸如約五倍。在各個實施例中，機械切割形成筆直切口，諸如切割切口126的側壁128是實質上垂直的。在本文中，「實質上垂直」指的是在側壁128與對應基板的頂表面之間形成的角度大於80°。
由於機械切割穿過溝槽120，並且不具有與元件層104及204的實質實體接觸，在切割期間的熱及機械應力主要限制於基板102及202中，這減輕對元件層104及204的破壞。例如，矽剝離(若有的話)較不可能傳播到元件層104及204中，這減小元件缺陷率。
參見第8A圖，示出了在結合雷射開槽及機械切割的混合切割製程之後的已切割的半導體積體電路300。具體而言，半導體積體電路300包括第一元件100的基板102及元件層104(包括全晶片區域中的電晶體及金屬層)以及第二元件200的元件層204(包括全晶片區域中的電晶體及 金屬層)及基板202。在元件層104及204中的電路可透過結合的金屬襯墊116彼此電氣耦接。半導體積體電路300的邊緣包含實質上垂直的上部側壁128、上部漸縮側壁124、下部漸縮側壁124、及實質上垂直的下部側壁128。在所示出的實施例中，側壁124及128形成連續的側壁輪廓。上部及下部側壁128的各者基本上包括機械切割切口輪廓的一半。上部及下部漸縮側壁124的各者基本上包括雷射開槽輪廓的一半(減去機械切割切割寬度的約一半)。上部及下部漸縮側壁124形成朝向半導體晶片300的中心彎曲的凹面130。凹面130的寬度D定義為從上部側壁128與上部漸縮側壁124的交叉點到下部側壁128與下部漸縮側壁124的另一交叉點的長度。凹面130的高度H定義為從元件層104及204的界面處的邊緣點到上文定義的交叉點的任一個的橫向距離。凹面130的寬度D等於或略微大於元件104及204的厚度的總和。在一些實施例中，寬度D為約3μm至約80μm。凹面的高度H粗略地為溝槽寬度W1的一半減去機械切割切口寬度W2的一半((W1-W2)/2)。在一些實施例中，高度H為1μm至約50μm。在一些實施例中，比率H/D為約0.01至約20。在具體實施例中，凹面130具有約30μm的寬度D以及約28μm的高度H。
第8B圖及第8C圖圖示了半導體積體電路300的邊緣的特性。具體而言，在第8B圖中，垂直軸表示邊緣的斜率，並且水平軸z表示沿著垂直方向距基板102的底表面的距離；在第8C圖中，垂直軸表示邊緣的表面粗糙度， 並且水平軸z表示沿著垂直方向距基板102的底表面的距離。參見第8B圖，由於實質上垂直的側壁128，在基板102及202中的斜率具有最大值S1。根據一些實施例，斜率輪廓在元件層與基板之間的界面處或附近具有轉向點。斜率在基板102及202內是實質上平坦的，在界面處下降至接近零，並且隨後增加到值S2，其中S2小於S1。在一些實施例中，S1對應於大於80°的角度的正切，而S2對應於在約35°與約80°之間(諸如約45°)的角度的正切。參見第8C圖，在一些實施例中，漸縮側壁124(覆蓋元件104及204的邊緣並且視情況略微到基板102及202中)的表面粗糙度R1(以RMS量測)大於機械切割輪廓的表面粗糙度。換言之，由於機械切割產生的側壁128通常比由於雷射開槽產生的側壁124更為光滑。在一些實施例中，側壁128(覆蓋基板102及202的大部分或整個邊緣)的表面粗糙度R2(以RMS量測)小於R1的約五分之一。
在一些情況下，在結合期間的未對準可導致在第一元件100與第二元件200之間的橫向偏移。如第9圖所示，溝槽對(pair)的漸縮側壁124由於橫向偏移而不連續並且形成階梯輪廓。在元件層104與204之間的界面的一個邊緣處的區域302中，暴露出元件層204向下的表面。在元件層104與204之間的界面的另一邊緣處的區域304中，暴露出元件層104向上的表面。在一些實施例中，取決於橫向偏移的距離，元件層104及204的任一表面可暴露達約0.1μm至約20μm。
在一些情況下，成對的溝槽可具有不同開口寬度，從而在已切割的半導體積體電路300的邊緣處亦導致階梯輪廓。在第10圖中，在切割之前元件層104中的下部溝槽具有與元件層204中的上部溝槽相比較小的開口。因此，在區域302及304中，暴露出元件層104的頂表面，並且漸縮側壁124是不連續的且形成階梯輪廓。不同溝槽開口寬度可由在開槽期間不同的雷射強度導致或由於不同的元件層厚度導致，如通常元件層越薄，溝槽將越淺且越窄。在半導體積體電路300的任一邊緣上，元件層104的頂表面可暴露達約0.1μm至約20μm。
回到方法10(第1A圖)的操作32，結合製程的又一替代實施例是將一個元件的基板結合到另一元件的元件層，而不翻轉其中一個或另一個。如第11圖所示，在結合之前，第二元件200的基板202的底表面直接面對第一元件100的元件層104的頂表面。第一元件100中的溝槽120直接在第二元件200中的對應溝槽120下方，但藉由在其之間的基板202分離。在結合之前，第二元件200可進一步具有在基板202中形成的貫穿矽通孔(TSV)140，以將元件層204中的電路訊號路由到基板202的底表面。貫穿矽通孔140可藉由穿過基板202蝕刻垂直孔，並且用導電材料(諸如銅)填充孔來形成。金屬襯墊116亦可藉由適宜方法(諸如單鑲嵌製程或雙鑲嵌製程)在基板202的最底部處形成。結合製程可實質上類似於上文關於第6圖所論述者。熱壓縮結合、回焊製程、或NIR回焊製程、或其他適宜結合製程可 用於實體接合第一元件100及第二元件200。在結合之後，元件層204中的電路穿過貫穿矽通孔140及結合的金屬襯墊116電氣耦接到元件層104中的電路。
回到操作42，方法10(第1A圖)利用與雷射不同的切割技術(諸如機械切割方法)沿著刻劃通道區域108切割，以將結合的半導體結構分為兩個或多個晶粒300(第12圖)。在各個實施例中，機械切割實質上類似於上文關於第7圖論述者。區別之一是在機械切割中採用的鋸或刀刃按順序切穿上部溝槽120、基板202、下部溝槽120、及基板102。在基板202中的切割切口126連接上部及下部溝槽120。
在第13圖中示出了在結合雷射開槽及機械切割的混合切割製程之後，來自結合的替代實施例的已切割的半導體積體電路300。半導體積體電路300的邊緣包含五個區段，亦即按順序為上部漸縮側壁124、來自穿過基板202的機械切割的上部側壁128、基板202的底表面、下部漸縮側壁124、及來自穿過基板102的機械切割的下部側壁128。機械切割導致的側壁128通常比雷射開槽導致的漸縮側壁124更為光滑。在各個實施例中，漸縮側壁124的表面粗糙度(以RMS量測)是側壁128的表面粗糙度的至少五倍。在一些實施例中，參考半導體積體電路300的底表面，側壁128形成大於80°的角度，並且漸縮側壁124形成在約35°與約80°之間的角度，諸如約45°。
參見第1B圖，在方法10的一些其他實施例中，將第一及第二元件結合在一起的操作32，可以在第二元件層中形成溝槽的操作24之前。如第14圖所示，溝槽120在第一元件100的刻劃通道區域108中形成，但不在第二元件200中形成。熱壓縮結合、回焊製程、或NIR回焊製程、或其他適宜結合製程可用於實體接合第一元件100及第二元件200。在結合之後，第二元件200的基板202覆蓋第一元件100的元件層104中的溝槽120。貫穿矽通孔140及金屬襯墊116提供用於電氣連接元件層104及204中的電路的訊號路徑。
在操作24中，在結合之後，方法10(第1B圖)形成溝槽120，此等溝槽120穿過第二元件200的元件層204並且視情況進入到基板202(第15圖)的上部中。開槽製程實質上類似於上文關於第5圖所論述。元件層204中的溝槽120直接在元件層104中的對應溝槽120之上。
隨後，在操作42中，方法10(第1B圖)利用與雷射不同的切割技術(諸如機械切割方法)沿著刻劃通道區域108切割，以將結合的半導體結構分為兩個或多個晶粒300(第16圖)。在一些實施例中，機械切割採用鋸或刀刃(未圖示)以按順序切穿上部溝槽120、基板202、下部溝槽120、及基板102。在基板202中的切割切口126連接上部及下部溝槽120。機械切割實質上類似於上文關於第12圖所論述。
參見第1C圖，方法10可視情況包括其他操作。在一些實施例中，在結合第一元件100及第二元件200的操作32之後，方法10繼續進行到操作34至基板厚度減小製程(第17圖)。執行基板厚度減小製程(亦稱為薄化製程)以減小一或兩個基板的厚度。在所示出的實施例中，薄化第二元件200的基板202。例如，從約厚度約700μm至厚度約5μm。在一些實施例中，將粗略研磨及精細研磨施加到基板202的後側。在粗略研磨步驟中，移除基板202的大部分但並非整個厚度。在此粗略研磨步驟中移除的材料量部分藉由在粗略研磨及額外製程步驟之後矽表面的總粗糙度決定，在粗略研磨步驟期間產生的粗糙度及損壞需要由額外製程步驟來消除。粗略研磨的表面的平均粗糙度可使用表面輪廓儀來量測確定，此平均粗糙度為在一平方厘米面積上量測而得的。為了移除在粗略研磨步驟中產生的粗糙度及破壞，基板202的表面經歷第二研磨步驟，亦即，精細研磨步驟。針對精細研磨，可使用網格精整磨輪。
在操作36中，方法10(第1C圖)在薄化基板(第17圖)上形成濾色器及/或透鏡。在所示出的實施例中，濾色器134設置在薄化基板202的後側上方，並且與全晶片區域106內部的感光區域對準。濾色器134被設計為使得此濾色器濾過某一預定波長的光。例如，濾色器134可濾過紅色波長、綠色波長、或藍色波長的可見光至感測區域。濾色器134包括任何適宜材料。在一實例中，濾色器134包括基於染料(或基於顏料)的聚合物，用於濾掉特定頻率的頻帶(例 如，期望波長的光)。或者，濾色器134包括具有彩色顏料的樹脂或其他基於有機物的材料。透鏡(未圖示)可設置在基板202的後側上方，特別是設置在濾色器134上方，並且亦與感光區域對準。透鏡可與感測區域及濾色器134處於各種位置佈置，使得透鏡將入射輻射聚焦在感測區域上。透鏡包括適宜材料並且可具有各種形狀及大小，這取決於用於透鏡的材料的折射率及/或在透鏡與感測區域之間的距離。或者，濾色器134及透鏡層的位置可反過來，使得透鏡設置在薄化基板202與濾色器134之間。
在操作38中，方法10(第1C圖)形成凹槽138以暴露金屬襯墊116(第18圖)。在所示出的實施例中，凹槽138經圖案化且由基板202的後側表面蝕刻、穿過基板202及元件層204、並且到達被設計以用於接收結合接線的金屬襯墊116。凹槽138可以被視為貫穿矽通孔(TSV)，並且金屬襯墊116可以被視為結合襯墊。
在操作42中，方法10(第1A圖)利用與雷射不同的切割技術(諸如機械切割)沿著刻劃通道區域108切割，以將結合的半導體結構分為兩個或多個晶粒300(第19圖)。在一些實施例中，機械切割採用鋸或刀刃(未圖示)以按順序切穿薄化基板202、上部溝槽120、下部溝槽120、及基板102。在一些替代實施例中，鋸或刀刃不完全切穿基板102，但接著機械開裂製程以將結合的半導體結構斷裂為晶粒。
方法10(第1C圖)可進一步進行到其他操作以完成半導體積體電路300，諸如，通過溝槽138在結合襯墊116上著陸結合線142，以將元件層104及204中的電路電氣耦接到外部電路，諸如引線框架(第20圖)。
第21圖示出了形成倒裝晶片結合(flip chip bonding)以從晶片底部路由單個路徑的半導體積體電路300的另一實施例。在所示出的實施例中，貫穿矽通孔146在基板102中形成，並且金屬襯墊148在基板102的底表面上形成。焊料凸塊(或銅凸塊)152隨後沉積在金屬襯墊148上。第22圖示出了在元件層204的頂表面上形成接線結合的半導體積體電路300的又一實施例。在所示出的實施例中，在結合製程中基板202直接面對元件層104。基板202中的貫穿矽通孔140提供從元件層204到元件層104的訊號路徑。元件層204的金屬襯墊116在半導體積體電路300的頂表面上暴露來為結合線142提供著陸襯墊。結合線142將元件層104及204中的電路電氣耦接到外部電路，諸如耦接到引線框架。
儘管未限制，本揭示的一或多個實施例提供對堆疊半導體元件及其製造方法的改進。例如，本揭示的實施例提供一種混合切割製程，包括在結合之前的雷射開槽製程，以及隨後接著執行機械切割，這在堆疊半導體元件切割期間減輕有害影響，諸如與習知晶圓切割方法相關的微裂痕及矽碎屑再沉積，由此減少與切割有關的元件破壞，並且改 進產品良率。此外，堆疊半導體元件的形成可以簡單地整合到現有的半導體製造製程中。
由此，本揭示之實施方式提供了用於製造半導體元件的許多不同實施例。在一個示例性態樣中，本揭示之實施方式涉及一種方法。此方法包括：提供第一及第二晶圓；在第一晶圓的頂部中形成第一元件層；在第二晶圓的頂部中形成第二元件層；在第一元件層中形成第一溝槽；在第二元件層中形成第二溝槽；在形成第一及第二溝槽的至少一個之後，將第一晶圓與第二晶圓結合在一起；以及藉由切割製程來切割結合的第一及第二晶圓，其中切割製程切穿第一及第二溝槽。在一些實施例中，第一及第二溝槽的每一個藉由雷射開槽製程形成。在一些實施例中，切割製程包括利用鋸或刀刃的機械切割。在一些實施例中，在結合之後，第二溝槽直接在第一溝槽下方。在一些實施例中，第一溝槽完全延伸穿過第一元件層，並且第二溝槽完全延伸穿過第二元件層。在一些實施例中，在結合第一晶圓及第二晶圓之後，第一元件層面對第二元件層，使得孔隙從第一溝槽持續延伸到第二溝槽。在一些實施例中，第一元件層包括第一結合襯墊，且第二元件層包括第二接合襯墊，並且其中結合第一晶圓及第二晶圓將第一結合襯墊實體地接合到第二結合襯墊。在一些實施例中，此方法進一步包括在結合第一晶圓及第二晶圓之前，在第二晶圓中形成貫穿基板通孔(TSV)，使得穿貫基板通孔在第二晶圓的底表面處將第二元件層電氣耦接到結合襯墊。在一些實施例中，在結合第一晶圓及第二 晶圓之後，第二元件層面對第一晶圓的底表面。在一些實施例中，此方法進一步包括在結合第一晶圓及第二晶圓之前，在第一晶圓中形成貫穿基板通孔(TSV)，使得在結合第一晶圓及第二晶圓之後，貫穿基板通孔將第一元件層電氣耦接到第二元件層。在一些實施例中，第一溝槽具有第一側壁，藉由切割製程製成的切口具有第二側壁，並且第一側壁具有小於第二側壁的斜率。
在另一示例性態樣中，本揭示之實施方式涉及一種製造堆疊半導體元件的方法。此方法包括：提供第一結構，具有第一基板及在第一基板上的第一元件層；提供第二結構，具有第二基板及在第二基板上的第二元件層；在第二元件層中形成第二溝槽；將第一基板的底表面結合到第二元件層的頂表面；在結合之後，在第一元件層中形成第一溝槽；以及按順序切穿第一溝槽、第一基板、第二溝槽、及第二基板。在一些實施例中，第一及第二溝槽的每一個藉由雷射開槽製程形成。在一些實施例中，切割包括利用鋸或刀刃的機械切割。在一些實施例中，第一溝槽延伸到第一基板的頂部中，並且第二溝槽延伸到第二基板的頂部中。在一些實施例中，第一及第二溝槽的每一個係沿著刻劃通道。在一些實施例中，第一溝槽具有第一側壁，第一基板具有藉由切割形成的第二側壁，並且第一側壁具有大於第二側壁的表面粗糙度。
在又一示例性態樣中，本揭示之實施方式涉及一種堆疊半導體元件。此堆疊半導體元件包括：第一基板， 具有第一側壁；在第一基板上的第一元件層，具有第二側壁，其中第二側壁的表面粗糙度大於第一側壁的表面粗糙度；以及材料層，結合到第一元件層，其中第一元件層包括第一導電特徵，此第一導電特徵電氣耦接到材料層中的第二導電特徵。在一些實施例中，第二側壁的表面粗糙度係第一側壁的表面粗糙度的至少五倍。在一些實施例中，第二側壁的斜率小於第一側壁的斜率。
上文概述若干實施例的特徵，使得熟習此項技術者可更好地理解本揭示之一實施方式的態樣。熟習此項技術者應瞭解，可輕易使用本揭示之一實施方式作為設計或修改其他製程及結構的基礎，以便實施本文所介紹的實施例的相同目的及/或實現相同優點。熟習此項技術者亦應認識到，此類等效構造並未脫離本揭示之一實施方式的精神及範疇，且可在不脫離本揭示之一實施方式的精神及範疇的情況下產生本文的各種變化、取代及更改。
100:第一元件
102:基板
104:元件層
116:金屬襯墊
124:漸縮側壁
128:側壁
130:凹面
200:第二元件
202:基板
204:元件層
300:晶粒
D:寬度
H:高度

Claims (10)

  1. 一種堆疊半導體元件的製造方法，包含：提供一第一晶圓及一第二晶圓；在該第一晶圓的一頂部中形成一第一元件層；在該第二晶圓的一頂部中形成一第二元件層；在該第一元件層中形成一第一溝槽；在該第二元件層中形成一第二溝槽；在形成該第一溝槽及該第二溝槽的至少一個之後，將該第一晶圓及該第二晶圓結合在一起；以及藉由一切割製程切割結合在一起的該第一晶圓及該第二晶圓，其中該切割製程切穿該第一溝槽及該第二溝槽。
  2. 如請求項1所述之方法，其中該第一溝槽及該第二溝槽藉由一雷射開槽製程形成。
  3. 如請求項2所述之方法，其中該切割製程包括利用一鋸或一刀刃的機械切割。
  4. 如請求項1所述之方法，其中在結合該第一晶圓及該第二晶圓之後，該第一元件層面對該第二元件層，使得一孔隙從該第一溝槽連續地延伸到該第二溝槽。
  5. 如請求項1所述之方法，其中該第一溝槽具有一第一側壁，藉由該切割製程製成的一切口具有一第 二側壁，並且該第一側壁一斜率具有小於該第二側壁的一斜率。
  6. 一種堆疊半導體元件的製造方法，包含：提供一第一結構，該第一結構具有一第一基板及在該第一基板上的一第一元件層；提供一第二結構，該第二結構具有一第二基板及在該第二基板上的一第二元件層；在該第二元件層中形成一第二溝槽；將該第一基板的一底表面結合到該第二元件層的一頂表面；在該結合之後，在該第一元件層中形成一第一溝槽；以及按順序切穿該第一溝槽、該第一基板、該第二溝槽、及該第二基板。
  7. 如請求項6所述之方法，其中該第一溝槽及該第二溝槽藉由一雷射開槽製程形成。
  8. 如請求項6所述之方法，其中該第一溝槽具有一第一側壁，該第一基板具有藉由該切割形成的一第二側壁，並且該第一側壁具有大於該第二側壁的一表面粗糙度。
  9. 一種堆疊半導體元件，包含： 一第一基板，具有一第一側壁，該第一側壁包括一第一部份和一第二部份；一第一元件層在該第一基板上，具有一第二側壁，其中該第二側壁和該第一側壁的該第一部份為連續的，該第二側壁和該第一側壁的該第一部份的一表面粗糙度大於該第一側壁的該第二部份的一表面粗糙度，且該第二側壁和該第一側壁的該第一部份的一斜率小於該第一側壁的該第二部份的一斜率；以及一材料層，結合到該第一元件層，其中該第一元件層包括一第一導電特徵，該第一導電特徵電氣耦接到該材料層中的一第二導電特徵。
  10. 如請求項9所述之堆疊半導體元件，其中該第二側壁的該表面粗糙度為該第一側壁的該第二部份的表面粗糙度的至少五倍。
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US11081392B2 (en) 2021-08-03
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