CN1104042C - 半导体器件的制造方法 - Google Patents
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Abstract
本发明公开了一种制造能改善电阻率半导体器件的方法,包括以下步骤:在衬底上淀积绝缘膜;在绝缘膜第一区上形成第一导电类型的多晶硅层;在绝缘膜第二区上形成第二导电类型的多晶硅层;在第一和第二导电类型的多晶硅层上形成防扩散膜;在防扩散膜上形成晶体的金属硅化物层;通过将离子注入晶体的金属硅化物层中,将晶体的金属硅化物层变成非晶金属硅化物层;通过热处理非晶金属硅化物层使其结晶;及腐蚀晶体的金属硅化物层、第一和第二多晶硅层,和绝缘膜,形成CMOS晶体管。
Description
技术领域
本发明涉及半导体器件,特别涉及能改善电阻率的半导体器件的制造方法。
背景技术
一般来说,随着半导体器件高度集成,半导体器件内的连线宽度减小,必然导致连线的电阻增加,产生诸如操作速度下降等的问题。随着连线宽度的减小,为防止连线薄层电阻率增加而形成较厚的连线,但由于连线的台阶覆盖更大,产生器件的制造工艺变得更复杂并且产量更低的问题。为了解决这些问题,如硅化钨(WSix)、硅化钛(TiSi2),或硅化钴(CoSi2)等的难熔金属硅化物形成在多晶硅层上,意在防止电阻率的增加。(以下将形成在多晶硅层上的难熔金属硅化物称做“polycide”)。然而,虽然这可在某种程度上改善电阻率和台阶覆盖,但仍需要一种可进一步改善电阻率和台阶的形成polycide的方法。
下面结合附图介绍制造半导体器件的常规方法。图1A-1C显示了制造半导体器件的第一个常规方法的工艺步骤剖面图,图2A-2C显示了制造半导体器件的第二个常规方法的工艺步骤剖面图。用于减小半导体器件内电阻率和台阶覆盖的polycide制造工艺适用于形成栅电极或字线的工艺。
下面介绍制造半导体器件的第一个常规方法的工艺步骤,其中使用polycide制造工艺形成栅电极。
参考图1A,工艺开始于在半导体衬底1上淀积第一氧化膜2,和在第一氧化膜2上淀积多晶硅层3。多晶硅3掺杂P型杂质并能溶于水。淀积多晶硅层3完成后,多晶硅层3的掺杂可通过离子注入,或淀积POCl3,或在淀积多晶硅层的同时连续注入如PH3的掺杂气体进行。为除去在图1B所示的形成多晶硅层3的工艺期间留在多晶硅层3上的自然氧化膜(或玻璃),将工艺所得结构浸泡在HF溶液中进行清洗。用具有六氟化钨(WF6)气体的SiH4或SiH2Cl2化学汽相淀积形成硅化钨层4,以形成polycide层。如图1C所示,用形成栅电极使用的掩膜对硅化钨层4、多晶硅层3和第一氧化膜2进行光刻,各向异性腐蚀层2、3和4,最终形成栅盖帽硅化物层4a、栅电极3a和栅氧化膜2a。轻掺杂的漏(LDD)区5形成在半导体衬底1上栅电极3a的两侧。第二氧化膜淀积在整个表面,并进行各向异性腐蚀除去第二氧化膜,在栅盖帽硅化物层4a、栅电极3a和栅氧化膜2a的两侧形成侧壁绝缘膜6。除了栅电极3a下的部分,对在侧壁绝缘膜6外的那部分半导体衬底1进行重掺杂,以在其中形成源/漏区7。
下面介绍制造半导体器件的第二个常规方法的工艺步骤,其中使用polycide制造工艺形成位线。
参见图2A,工艺起始于在部分P型的半导体衬底1内形成N型杂质掺杂的层8。进行化学汽相淀积在半导体衬底1上形成层间绝缘层9,选择性除去层间绝缘层9形成接触孔10,露出N型杂质掺杂的层8。如图2B所示,在整个表面上形成多晶硅层11。多晶硅层11掺杂P型杂质并能溶于水。淀积多晶硅层11完成后,多晶硅层11的掺杂可通过离子注入,或淀积POCl3,或在淀积多晶硅层的同时连续注入如PH3的掺杂气体进行。为除去在图2C所示的形成多晶硅层11的工艺期间留在多晶硅层11上的自然氧化膜(或玻璃),将工艺所得结构浸泡在HF溶液中进行清洗。用具有六氟化钨(WF6)气体的SiH4或SiH2Cl2化学汽相淀积在多晶硅层11上形成硅化钨层12,对硅化钨层12进行选择性构图形成polycide层的位线。
然而,制造半导体器件的常规方法存在以下问题。
由于根据常规方法通过在多晶硅层上淀积硅化钨在半导体器件内形成的栅电极或位线显示出硅化钨不是非晶态,也具有小的粒状尺寸,在减小多晶硅层的电阻率方面,栅电极或位线存在着限制。由于这些原因,在尺寸低于0.25m的高度封装的器件中,制造半导体器件的常规方法不能减小多晶硅层的电阻率。
因此,本发明提供一种制造半导体器件的方法,可基本上避免由于现有技术的限制和不足引起的几个问题。
发明内容
本发明的目的是提供一种制造能改善电阻率的半导体器件的方法。
本发明的其它特征和优点将在下面的说明部分中进行阐述,部分从说明部分中可明显看出,或可通过本发明的实践得到。在书面的说明书及权利要求书以及附图中具体地指出的结构可以实现和得到本发明的目的及其它优点。
为达到这些和其它优点,根据本发明的目的,正如概括和概要地描述,制造半导体器件的方法包括以下步骤:在衬底上形成硅层,在硅层上形成晶体的金属硅化物层,通过注入离子到晶体的金属硅化物层形成非晶金属硅化物层,以及通过热处理非晶金属硅化物使非晶金属硅化物结晶。
本发明提供一种制造半导体器件的方法,包括以下步骤:在衬底上淀积绝缘膜;在绝缘膜的第一区上形成第一导电类型的多晶硅层;在绝缘膜的第二区上形成第二导电类型的多晶硅层;在第一和第二导电类型的多晶硅层上形成防扩散膜;在防扩散膜上形成晶体的金属硅化物层;通过将离子注入到晶体的金属硅化物层中,将晶体的金属硅化物层转变成非晶金属硅化物层,形成非晶金属硅化物层;通过热处理非晶金属硅化物层使非晶金属硅化物层结晶;以及腐蚀晶体的金属硅化物层、第一和第二多晶硅层,和绝缘膜,形成CMOS晶体管。
应该理解以上的概述和以下的详细说明均为示例性和解释性的,意在为所要求的发展提供进一步的说明。
构成进一步理解本发明的本说明书的一部分的附图图示了本发明的实施例,并和描述部分一起介绍了本发明的基本原则。
附图的简要说明
图1A-1C显示了制造半导体器件的第一个常规方法的工艺步骤剖面图;
图2A-2C显示了制造半导体器件的第二个常规方法的工艺步骤剖面图;
图3A-3C显示了根据本发明的第一优选实施例制造半导体器件的工艺步骤剖面图;
图4A-4F显示了根据本发明的第二优选实施例制造半导体器件的工艺步骤剖面图;
图5显示了本发明掺杂的硅化钨层的非晶特性的图形;
图6显示了本发明的硅化钨层的离子剂量与电阻率的图形;
图7显示了在900℃进行30分钟热处理后,本发明的硅化钨层的离子剂量与电阻率的图形;
图8显示了当使用P离子作掺杂剂时,本发明不同厚度的硅化钨层的线宽与电阻率的图形;
图9显示了与图8相同的条件下形成的0.25m线宽的栅电极的电阻率图形。
具体实施方式的详细描述
现在详细介绍本发明的优选实施例,例子显示在附图中。图3A-3C显示了根据本发明的第一优选实施例制造半导体器件的工艺步骤剖面图,其中难熔金属硅化物形成在半导体器件内,图4A-4F显示了根据本发明的第二优选实施例制造半导体器件的工艺步骤剖面图。
减小半导体器件电阻率的polycide制造工艺可用于形成栅电极或位线。下面介绍根据本发明使用polycide制造工艺形成栅电极的例子。
参照图3A,根据本发明的第一优选实施例制造半导体器件的工艺步骤起始于在半导体衬底20上淀积第一氧化膜21,随后使用ICT(集成的工具组(Integrated ClusterTool)),在80Torr和660℃下在第一氧化膜21上淀积1000厚的掺杂的多晶硅层22。然后,在掺杂的多晶硅层22上淀积约200厚的未掺杂的多晶硅层23。在掺杂的多晶硅层22的淀积中,使用混有50%的SiH4和1%的PH3的H2作源气。使用WF6和SiH2Cl2或WF6和SiH4作源气在未掺杂的多晶硅层23上形成硅化钨层24。掺杂的多晶硅层22和未掺杂的多晶硅层23位于硅化钨层24之下,以防止在以后的步骤中通过注入离子将硅化钨层24转换成非晶的硅化钨层时注入到硅化钨层的离子的损失。掺杂的多晶硅层22可以淀积到约800厚,未掺杂的多晶硅层23可以淀积到约200厚,硅化钨层24可以淀积到约1000厚。或者,可选地,掺杂的多晶硅层22可以淀积到约300厚,未掺杂的多晶硅层23可以淀积到约200厚,硅化钨层24可以淀积到约2000厚。即,形成的硅化钨层24的厚度范围为1000-2000。如图3B所示,能量为50KeV且剂量为1×1015~8×1015cm-3的N型磷离子注入到硅化钨层24中,将硅化钨层24转换为非晶态。此时,磷离子注入能量为80KeV。在约900℃下进行30分钟的热处理使非晶硅化钨层24再结晶,形成大尺寸晶粒的硅化钨层24a。进行热处理的温度范围为400~1100℃。此时,代替N型磷离子,注入剂量为1×1015-8×1015cm-3能量分别为70KeV或20KeV的N型砷离子(As)或P型硼(B)离子,通过热处理形成大尺寸晶粒的硅化钨层24a。如图3C所示,为了形成栅电极,在各向异性腐蚀第一氧化膜、掺杂的多晶硅层22、未掺杂的多晶硅层23、大尺寸晶粒的硅化钨层24a的叠层中使用掩膜,形成栅盖帽硅化物层24b、栅电极22a和23a和栅氧化膜21a。LDD(轻掺杂的漏)区26形成在栅电极22a和23a两侧的半导体衬底20内,在整个表面上淀积第二氧化膜并进行各向异性腐蚀选择性地除去第二氧化膜,以在栅盖帽硅化物层24b、栅电极22a和23a和栅氧化膜21a两侧形成侧壁垫25。然后,除了栅电极22a和23a,重掺杂侧壁垫25两侧的半导体衬底20内的部分,形成源/漏区27。硅化钨层24也可以在淀积和以HF清除掺杂多晶硅层之后淀积。
下面介绍当剂量为5×1015cm-3离子注入形成1000厚的硅化钨层24时的非晶相位。图5为当注入不同的离子时硅化钨层24的XRD(X射线衍射)分析数据图,其中(a)为没有离子注入的情况,(b)为磷离子(P)注入的情况,(c)为硼离子(B)注入的情况,(d)为砷离子注入的情况,(e)为氩离子注入的情况。从硅化钨层的2(角)为30℃和约40℃时X射线更强的事实可以知道X射线在硅化钨为(111)晶向的这些角度处衍射,这意味着硅化钨层为晶体性的。此外,可以知道在氩(Ar)和磷(P)的情况下,硅化钨层24已完全转变成非晶态,在硼(B)和砷(As)的情况下,硅化钨层24没有完全转变成非晶态。如图6所示,当剂量不同时,如果剂量超过1×1015cm-3时,在所有的情况下,硅化钨层24的电阻率急剧减小,既使在剂量不断增加的情况下,电阻率也逐渐减小,这意味着在剂量为1×1015cm-3时,几乎硅化钨层24的所有部分都转变为非晶态。如图7所示的为在900℃下掺杂并热处理30分钟硅化钨层24的剂量与电阻率的关系,图中显示出对于砷(As)、硼(B)和磷(P)离子的情况下,随着剂量的增加电阻率减少,在磷(P)离子的情况下,在注入能量为80KeV时减小量最大,但在砷(As)和硼(B)离子注入时形成化合物。另一方面,在氩(Ar)离子注入时,随着剂量的增加电阻率增加,是由于在热处理过程中惰性气体氩(Ar)分解在硅化钨层24中形成空隙。从这些实验数据可以得出,优选剂量为5×1015cm-3的磷(P)离子注入。接下来,如图8和9所示,如果在淀积厚度为1000并注入50KeV的磷(P)离子的硅化钨层和淀积厚度为1500并注入80KeV的磷(P)离子的硅化钨层的情况下比较栅电极22a和23a的电阻率,当栅电极22a和23a的最小线宽设置为0.25m并且其它条件和以上相同时,可以看出淀积厚度为1500并注入80KeV的磷(P)离子的硅化钨层的电阻率最低。
下面介绍根据本发明的第二实施例制造半导体器件的方法。本发明的第二实施例适用于根据形成具有双栅极的CMOS晶体管的第一实施例形成的非晶硅化钨层的情况。
参考图4A,根据本发明的第二实施例制造半导体器件的工艺步骤起始于在半导体衬底30上淀积50厚的第一氧化膜31,随后在第一氧化膜31上淀积约1000厚的未掺杂的多晶硅层32。如图4b所示,将第一光刻胶膜33涂在未掺杂的多晶硅层32上,并进行选择性构图露出将要形成NMOS晶体管的未掺杂的多晶硅层32的部分。使用构图的光刻胶膜33作掩膜将N型磷(P)离子注入到未掺杂的多晶硅层32的部分中,形成N型多晶硅层32a。如图4C所示,除去第一光刻胶膜33,并涂敷第二光刻胶膜34,然后进行曝光和显影以选择性构图第二光刻胶膜34,在N型多晶硅层32a的边上露出将要形成PMOS晶体管的未掺杂的多晶硅层32的部分。将P型砷(As)或硼(B)离子注入到未掺杂的多晶硅层32的露出部分,形成P型多晶硅层32b。然后,除去第二光刻胶膜34。如图4D所示,在N型多晶硅层32a和P型多晶硅层32b上淀积约100厚的氮化钛(TiN),形成防扩散膜35。在淀积100的氮化钛时,淀积50的氮化钛后再淀积50的氮化钛,以使两膜的晶粒间界不匹配,以提高防扩散能力。除了氮化钛(TiN),还可淀积氮化钨(WNx)、钨硅氮化物(WSiN)、钽硅氮化物(TaSiN)或类似物作为防扩散膜35。然后,使用WF6和SiH2Cl2或WF6和SiH4作源气在防扩散膜35上形成厚度为1000-2000的硅化钨层36。形成防扩散膜35后形成硅化钨层36是为了形成双栅极,而不影响具有栅盖帽硅化物层36b的双栅极CMOS器件,该栅盖帽硅化物层36b是由非晶硅化钨层36在以后的步骤中形成的。如图4E所示,将能量为80KeV剂量为1×1015-8×1015cm-3,而优选为多于5×1015cm-3的N型磷(P)离子注入到硅化钨层36中,将硅化钨转变为非晶态,在约900℃下进行约30分钟的热处理使非晶硅化钨再结晶,形成大尺寸晶粒的硅化钨层36a。此时,进行热处理的温度范围为400-1100℃。注入和上述相同的剂量能量分别为70KeV或20KeV的N型砷离子(As)或P型硼(B)离子,通过热处理形成大尺寸晶粒的硅化钨层36a。如图4f所示,为了形成NMOS晶体管的栅电极,在各向异性腐蚀第一氧化膜31、N型多晶硅层32a和大尺寸晶粒的硅化钨层36a的层叠中使用掩膜,形成栅盖帽硅化物层36b、第一栅电极32c和栅氧化膜31a。为了形成PMOS晶体管的栅电极,在各向异性腐蚀第一氧化膜31、P型多晶硅层32b和大尺寸晶粒的硅化钨层36a的层叠中使用掩膜,形成栅盖帽硅化物层36b、第二栅电极32d和栅氧化膜31a。可供选择地,可以在形成防扩散膜35之后,通过溅射WSi2.2形成靶以形成非晶硅化钨层,并在没有离子注入的条件下,在900℃热处理该非晶硅化钨层,从而可以形成大粒子尺寸的硅化钨层36a。
在第一或第二实施例中,可用难熔金属硅化物的硅化钛层或硅化钽层代替硅化钨层。在形成硅化钛层时,可使用TiCl4、TiI2、SiH4,或SiH2Cl2作源气形成TiSi2,在形成硅化钽层时,可使用TaCl5、SiH4,或SiH2Cl2作源气形成TaSi2。
以上介绍的本发明的制造半导体器件的方法具有以下优点。
首先,借助再结晶在栅电极上形成大尺寸晶粒的硅化钨层使栅电极的电阻率减小,提高了器件的性能。
其次,在N型和P型掺杂的多晶硅上形成防扩散膜35改善了双栅极器件的可靠性。
对于本领域的技术人员来说很显然在本发明的制造半导体器件的方法中做出不同的修改和变形并不脱离本发明的精神或范围。因此,本发明意在由权利要求及其等同物的范围覆盖本发明的修改和变形。
Claims (12)
1.一种制造半导体器件的方法,包括以下步骤:
(1)在衬底上淀积绝缘膜;
(2)在绝缘膜的第一区上形成第一导电类型的多晶硅层;
(3)在绝缘膜的第二区上形成第二导电类型的多晶硅层;
(4)在第一和第二导电类型的多晶硅层上形成防扩散膜;
(5)在防扩散膜上形成晶体的金属硅化物层;
(6)通过将离子注入到晶体的金属硅化物层中,将晶体的金属硅化物层转变成非晶金属硅化物层,形成非晶金属硅化物层;
(7)通过热处理非晶金属硅化物层使非晶金属硅化物层结晶;以及
(8)腐蚀晶体的金属硅化物层、第一和第二多晶硅层,和绝缘膜,形成CMOS晶体管。
2.根据权利要求1的方法,其中防扩散膜由氮化钛(TiN)、氮化钨(WNx)、钨硅氮化物(WSiN)、或钽硅氮化物(TaSiN)形成。
3.根据权利要求1的方法,其中晶体的金属硅化物层由钨(W)、钛(Ti)、或钽(Ta)形成。
4.根据权利要求1的方法,其中通过注入磷(P)、硼(B)、或砷(As)的离子将晶体的金属硅化物层转变成非晶态。
5.根据权利要求4的方法,其中磷(P)、硼(B)、或砷(As)的离子剂量范围为1×1015-8×1015cm-3。
6.根据权利要求1的方法,其中形成的晶体的金属硅化物层的厚度范围为1000-2000。
7.根据权利要求3的方法,其中使用WF6和SiH4或WF6和SiH2Cl2作源气用钨形成晶体的金属硅化物层。
8.根据权利要求1的方法,其中在400-1100℃下进行非晶金属硅化物的热处理。
9.根据权利要求1的方法,其中形成非晶金属硅化物层包括形成防扩散膜,和
在防扩散膜上溅射金属硅化物层,代替步骤(4)、(5)和(6)。
10.根据权利要求1的方法,其中形成的防扩散膜的厚度数量级为100。
11.根据权利要求10的方法,其中分两次淀积防扩散膜,每次淀积50厚,以提高防扩散特性。
12.根据权利要求1的方法,其中形成第一和第二导电多晶硅层的步骤(2)和(3)包括
在绝缘膜上形成未掺杂的多晶硅层,
在硅层的第一区上形成第一导电类型的多晶硅层,
在硅层的第二区上形成第二导电类型的多晶硅层。
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-
1997
- 1997-09-29 KR KR1019970049799A patent/KR100425147B1/ko not_active IP Right Cessation
- 1997-10-13 TW TW086114924A patent/TW349247B/zh not_active IP Right Cessation
- 1997-10-14 US US08/009,493 patent/US6096630A/en not_active Expired - Lifetime
- 1997-11-27 CN CN97126460A patent/CN1104042C/zh not_active Expired - Fee Related
-
1998
- 1998-02-02 DE DE69832134T patent/DE69832134T2/de not_active Expired - Lifetime
- 1998-02-02 EP EP98101749A patent/EP0905753B1/en not_active Expired - Lifetime
- 1998-02-24 JP JP10041728A patent/JP2945967B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR19990027358A (ko) | 1999-04-15 |
TW349247B (en) | 1999-01-01 |
CN1213163A (zh) | 1999-04-07 |
EP0905753A2 (en) | 1999-03-31 |
DE69832134D1 (de) | 2005-12-08 |
EP0905753A3 (en) | 1999-04-28 |
EP0905753B1 (en) | 2005-11-02 |
JPH11111616A (ja) | 1999-04-23 |
US6096630A (en) | 2000-08-01 |
KR100425147B1 (ko) | 2004-05-17 |
DE69832134T2 (de) | 2006-07-20 |
JP2945967B2 (ja) | 1999-09-06 |
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