CN1989597A - 薄硅化钨层沉积和栅金属集成 - Google Patents
薄硅化钨层沉积和栅金属集成 Download PDFInfo
- Publication number
- CN1989597A CN1989597A CNA2005800243869A CN200580024386A CN1989597A CN 1989597 A CN1989597 A CN 1989597A CN A2005800243869 A CNA2005800243869 A CN A2005800243869A CN 200580024386 A CN200580024386 A CN 200580024386A CN 1989597 A CN1989597 A CN 1989597A
- Authority
- CN
- China
- Prior art keywords
- layer
- tungsten silicide
- substrate
- tungsten
- silicide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 title claims abstract description 90
- 229910021342 tungsten silicide Inorganic materials 0.000 title claims abstract description 90
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 21
- 239000002184 metal Substances 0.000 title claims abstract description 21
- 230000008021 deposition Effects 0.000 title claims description 62
- 230000010354 integration Effects 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 124
- 229920005591 polysilicon Polymers 0.000 claims abstract description 120
- 238000000151 deposition Methods 0.000 claims abstract description 79
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 70
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 70
- 239000010703 silicon Substances 0.000 claims abstract description 70
- 238000000034 method Methods 0.000 claims abstract description 44
- 238000012545 processing Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 93
- 229910052721 tungsten Inorganic materials 0.000 claims description 57
- 239000010937 tungsten Substances 0.000 claims description 57
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 41
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 32
- 229910000077 silane Inorganic materials 0.000 claims description 32
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 20
- -1 tungsten nitride Chemical class 0.000 claims description 15
- 206010010144 Completed suicide Diseases 0.000 claims description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 237
- 239000007789 gas Substances 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000012159 carrier gas Substances 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 4
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 125000001153 fluoro group Chemical group F* 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910004014 SiF4 Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 150000003657 tungsten Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开了一种用于沉积栅极层的方法。该方法包括沉积掺杂多晶硅层、薄硅化钨层和金属层。一方面,在集成处理系统内沉积该掺杂多晶硅层和薄多晶硅层。另一方面,沉积该薄硅化钨层包括将多晶硅层暴露于硅源中、沉积硅化钨层,并将该硅化钨层暴露于硅源中。
Description
技术领域
本发明的实施方式涉及沉积栅极层的方法。
背景技术
集成电路由诸如晶体管、电容器和电阻器等上百万的多种器件组成。晶体管,诸如场效应晶体管,一般包括源极、漏极和栅层叠。栅层叠一般包括诸如硅衬底的衬底、位于衬底上的诸如二氧化硅的栅电介质,以及位于栅电介质上的栅极。
已用于栅极的材料包括诸如铝的金属和多晶硅。由于掺杂的多晶硅的阈值电压低于铝,因此掺杂的多晶硅已成为用于栅极的优选材料。阈值电压为在连接晶体管源极和漏极的栅极下形成沟道所需的电压值。由于低阈值电压可以降低晶体管所需的功率值并提高晶体管的速度,因此较低的阈值电压为更可取的阈值电压。
另外,现已研发了包括位于多晶硅层上的钨(W)层叠或者氮化钨(WN)/钨层的栅极。在多晶硅层上可以形成包括钨层叠或者氮化钨/钨层的栅极从而使得栅极具有低电阻,这对于90nm以及更小的晶体管的研发来说正在变得越来越重要。然而,已发现用诸如退火的后续处理步骤处理栅极会导致钨或氮化钨层和多晶硅层之间产生不期望的相互作用。例如,当进行退火处理时,多晶硅层和钨或氮化钨层之间可能形成不均匀的氮化硅(SiN)或者硅化钨(WSix)层。多晶硅层和钨或氮化钨层之间的反应还可能影响栅极的电阻和器件的可靠性。
因此,需要具有低电阻及稳定的化学和电学特性的栅极。
发明内容
本发明的实施方式主要提供一种在衬底上沉积栅极层的方法,其包括在衬底上沉积多晶硅层,在该多晶硅层上沉积具有厚度约20到约80之间的硅化钨层,以及在该硅化钨层上沉积金属层以形成栅极层。在一实施方式中,该多晶硅层为掺杂多晶硅层,并且富含多晶硅层沉积在该掺杂多晶硅层上。
本发明的实施方式还提供一种在衬底上沉积栅极层的方法,其包括在衬底上沉积多晶硅层、在该多晶硅层上沉积厚度约20和约80之间的硅化钨层,其中沉积该硅化钨层包括将该多晶硅层暴露于硅烷中,使包括二氯硅烷和六氟化钨的气体混合物发生反应以沉积硅化钨层,并且将该硅化钨层暴露于硅烷中,接着在该硅化钨上沉积金属层以形成栅极层。在一实施方式中,将该多晶硅层暴露于硅烷中包括在该多晶硅层上沉积薄硅层,以及将该硅化钨层暴露于硅烷中包括在该硅化钨层上沉积薄硅层。
在另一实施方式中,提供一种处理衬底的方法包括在集成处理系统的第一腔室中在衬底上沉积多晶硅层,以及在集成处理系统的第二腔室中在多晶硅层上沉积具有厚度约20和约80之间的硅化钨层,其中在沉积该多晶硅层之后和沉积该硅化钨层之前,不将该衬底暴露于集成处理系统的外部环境中。
在另一实施方式中,提供一种在衬底上沉积栅极层的方法,其包括在衬底上沉积多晶硅层,在足以提供该层约等于或大于2500Ω/cm2面电阻的条件下,在该层上沉积厚度约20和约80之间的层,并且在该层上沉积金属层。
附图说明
因此为了更详细地理解本发明的以上所述特征,将参照附图中示出的实施例对以上简要所述的本发明进行更具体描述。然而,应该注意,附图中只示出了本发明典型的实施例,因此不能认为是对本发明范围的限定,本发明可以允许其他等同的有效实施例。
图1为根据本发明实施方式掺杂多晶硅层和沉积在其上的富含多晶硅层中磷浓度的曲线图;
图2为集成处理系统的俯视图;
图3为根据本发明实施方式包括含有栅极的多层的结构的截面图;
图4为描述本发明一实施方式的流程图;
图5为包括根据本发明一实施方式形成的栅极的器件的截面图;
图6为位于根据本发明不同的实施方式沉积的多晶硅层和硅化钨层之间的交界处的氧浓度曲线图。
具体实施方式
本发明的实施方式涉及一种用于在衬底上沉积栅极层的方法。本发明的实施方式提供一种在多晶硅层和金属层之间沉积薄层的方法,其中该薄层具有约等于或大于2500Ω/cm2的面电阻。在一实施方式中,这些层包括多晶硅层、硅化钨(WSix)层和金属层。这些层提供具有预期面电阻的栅极层叠以及层叠的层与层之间的良好粘性。硅化钨层为薄粘附层或粘接层,其改善金属层和多晶硅层之间的粘性并防止金属层和多晶硅层之间发生的不期望的反应。由于硅化钨层很薄,即厚度约20到约80,因此硅化钨层不会明显增加栅极层叠的电阻。根据本发明实施方式得到如在非掺杂硅衬底上测得的具有至少约2500Ω/cm2面电阻的硅化钨层。
在一实施方式中,在衬底上沉积多晶硅层。该衬底可为硅或含硅的衬底。如这里所限定,硅衬底包括诸如硅晶圆的单层硅衬底,或者包括位于一个或多个其他层的顶表面上的硅层的结构。一般地,该衬底具有形成于其上的薄栅氧化层。该栅氧化层可为通过将衬底暴露于含有氧的环境中以氧化衬底的顶表面形成的氧化硅层。
该多晶硅层可为约500到约2000厚。在一方案中,该多晶硅层为掺杂多晶硅层,诸如磷掺杂多晶硅层。可通过在热化学气相沉积工艺中使包含诸如硅烷(SiH4)或乙硅烷(Si2H6)的硅源和诸如磷化氢的掺杂源的气体混合物发生反应而沉积该多晶硅层。热化学气相沉积工艺可在Polycide Centura@的POLYgenTM腔室中执行。该气体混合物还可包括诸如氮气、或诸如氩气或氦气的惰性气体的载气。多晶硅层的典型沉积条件包括气压在约50Torr和约300Torr之间,以及衬底支架温度在约570℃和约750℃之间,进入工艺腔室的硅源流速在约30sccm和约200sccm之间。一般地,衬底的温度小于衬底支架温度约30℃。应当注意以上和整个申请中提供的工艺条件为用于300mm衬底的工艺条件,并且该工艺条件对于其他尺寸的衬底可进行相应地调节。
在替代的实施方式中,掺杂多晶硅层可通过沉积未掺杂多晶硅层并接着将该未掺杂多晶硅层暴露于掺杂源中形成。
在该掺杂多晶硅层沉积之后,富含多晶硅层可沉积在该掺杂多晶硅层上。如这里所限定,富含多晶硅层为含有较低浓度掺杂物的掺杂多晶硅或者无掺杂的多晶硅的多晶硅层。例如,掺杂多晶硅层可具有约1×1020到约1×1021atom/cm3之间的掺杂浓度,而富含多晶硅层在它的上表面具有约1×1019atom/cm3的掺杂浓度从而富含多晶硅层具有比多晶硅层更低的掺杂浓度。富含多晶硅层可在用于沉积掺杂多晶硅的同一腔室中沉积,从而在原位置执行掺杂多晶硅层和富含多晶硅层的沉积,即在沉积这两层之间不将衬底暴露于腔室外部环境的条件下在同一腔室中进行沉积。富含多晶硅层可通过终止掺杂源通入腔室并继续将硅源流入腔室中沉积该富含多晶硅层。在另一实施方式中,终止掺杂源和硅源通入腔室并且在重新将硅源通入腔室以沉积富含多晶硅层之前,诸如利用载气流清洗腔室。
可选地,可在与用于沉积多晶硅层的不同腔室中沉积富含多晶硅层。用于沉积多晶硅的腔室和用于沉积富含多晶硅层的腔室可为集成处理系统的部分从而在沉积该两层之间,可在不破坏真空并且不将衬底暴露于集成处理系统外部环境中的情况下沉积所述两层。
如图1所示,富含多晶硅层可具有掺杂物的浓度梯度,在沉积富含多晶硅层期间随着残余的掺杂源从腔室移去,掺杂物的浓度降低。图1示出了在其上沉积有具有富含多晶硅层的掺杂多晶硅层的磷浓度曲线图。富含多晶硅层的表面具有约3×1019atom/cm3的磷浓度。富含多晶硅层的磷浓度随着富含多晶硅层的深度增加直到其浓度与掺杂多晶硅层的磷浓度基本相同为止(约2×1020atom/cm3)。
一般认为沉积富含多晶硅层改善后续沉积的硅化钨层的成核化,原因在于已观察到用于掺杂多晶硅层的诸如磷化氢的掺杂源可削弱来自用于沉积硅化钨层的硅源的硅作用。
在沉积掺杂多晶硅层和富含多晶硅层之后,在其上沉积硅化钨。可通过在热化学气相沉积工艺中使包含诸如二氯硅烷(SiH2Cl2)或者硅烷(SiH4)的硅源和诸如六氟化钨(WF6)的钨源的气体混合物反应而进行沉积该硅化钨层。该气体混合物还可包括诸如氮气或惰性气体的载气。用于硅化钨层的示例性沉积条件包括在腔室气压为约0.8Torr和约2Torr之间,以及衬底支架温度为约400℃和约650℃之间,硅源以约30sccm和约100sccm之间的流速进入工艺腔室、钨源以约1sccm和约3sccm之间的流速进入腔室。衬底支架温度可根据使用的硅源而不同。例如,当二氯硅烷用作硅源时,优选的衬底支架温度在约500℃和650℃之间,而当硅烷用作硅源时,优选的衬底支架温度在约400℃和约500℃之间。硅化钨层可具有约20到约80之间的厚度,并且硅与钨的比例为约2.1∶1和约3.0∶1之间。硅与钨的比例为可调的,诸如通过调节硅源和钨源的流速的比例调整硅与钨的比例。
在优选的实施方式中,在将包含硅源和钨源的气体混合物发生反应以在多晶硅层上沉积硅化钨层之前,沉积硅化钨层包括将多晶硅层即掺杂多晶硅层或在如上所述的掺杂多晶硅层上的富含多晶硅层暴露于诸如硅烷的硅源中。可将多晶硅层暴露于与用于沉积硅化钨层的相同腔室的硅源中。载气可在硅源之前引入腔室中。以约300sccm和约1200scmm之间的流速,诸如约700sccm将硅源引入腔室,腔室气压约5Torr和约10Torr之间,并且位于腔室中的衬底支架加热至400℃和约650℃之间的温度,诸如约550℃。在足以在多晶硅层上沉积薄硅层的时间周期向腔室流入硅源,该薄硅层诸如几个原子的硅层,即具有厚度约5和约10之间的1-2个原子层。例如,硅源可以以约300sccm到约1200sccm之间的速率通入腔室中约20秒到约50秒。一般认为薄硅层的沉积改善硅化钨层的成核化并且有助于形成具有硅/钨比例为约等于或大于2的硅化钨层。根据本发明实施方式在多晶硅上沉积的50硅化钨层具有如通过X射线光电子光谱(XPS)测得的硅/钨的比例约为2.4∶1。
具有硅/钨比例等于或大于2的硅化钨层为优选的,原因在于已观察到在诸如退火处理的后续衬底处理步骤期间,具有较低硅/钨比例的硅化钨层会提供过多的钨自由基,该钨自由基与下方多晶硅层发生反应,并在多晶硅层和硅化钨层之间形成具有不均匀电阻率及物理特性的交界面。具有硅/钨比例等于或大于2的硅化钨层为优选的,原因在于已发现具有较低硅/钨比例的硅化钨层有分层倾向。
在以上所述的实施例中将多晶硅层暴露于硅源中以沉积薄硅层之后,将二氯硅烷引入腔室中。在腔室中形成二氯硅烷的稳定流速。例如,可以采用30sccm和约100sccm之间,诸如60sccn的二氯硅烷流速以及约1到约1.2Torr之间的腔室压力。接着,在约0.8Torr到2Torr,诸如约1到1.2Torr的腔室气压下将六氟化钨以约1sccm和约3sccm,诸如约2sccm的流速引入腔室中。在腔室中二氯硅烷和六氟化钨发生反应以沉积硅化钨层。在硅化钨层沉积期间,在腔室中衬底支撑构件可加热至约400℃和约650℃之间,诸如550℃的温度。如上所述,温度可根据采用的气源而不同。可选地,在硅化钨层沉积之后,保持二氯硅烷的气流与载气流以清洗腔室。
在硅化钨层沉积之后,可将该硅化钨层暴露于诸如硅烷的硅源气流中。也可使用载气。在衬底支架构件温度约500℃和约600℃之间,以及腔室气压约0.8Torr到约2Torr之间,诸如约1到约1.2Torr的条件下,硅烷可以以约100sccn和约700sccm的流速进入腔室。将硅化钨层暴露于硅烷气流中能除去不需要的氟原子,其可能与硅化钨层结合作为来自用于沉积该层的诸如WF6的含氟前驱物的残留。硅烷分解并且与氟原子结合从而形成排出到腔体外部的HF和SiF4。将硅化钨层暴露于硅烷中还可在硅化钨层上形成富含硅的覆盖,该富含硅的覆盖可被氧化以形成保护以下层的氧化硅覆盖。
在另一实施方式中,可在集成处理系统的不同腔室中执行将多晶硅层暴露于硅源中,沉积硅化钨层以及将硅化钨层暴露于硅源中的步骤,从而使得从将多晶硅层暴露于硅源中到将硅化钨层暴露于硅源中的过程中,衬底不会暴露于该集成处理系统的外部环境中。
可选地,在将硅化钨层暴露于硅烷中之后,氨气(NH3)气流进入腔室中以在硅化钨层的表面形成钨-氮键并促进其上氮化钨层的沉积。
在根据这里所述任意实施方式沉积硅化钨之后,在该硅化钨层上沉积金属层。该金属层可为钨层、氮化钨层或者其组合,诸如接着钨层的氮化钨层。可通过例如CVD、物理气相沉积(PVD)或者原子层沉积(ALD)沉积该钨层和氮化钨层。在2002年2约26日递交的发明名称为“Cyclical Deposition ofTungsten Nitride for Metal Oxide Gate Electrode”的共同转让的美国专利申请号No.10/084,767中描述了用于沉积钨和氮化钨层的示例性工艺条件在此引入其全部作为和本发明所述公开和要求保护的范围一致的内容的参考。
集成处理顺序
在一实施方式中,提供一种在集成处理系统内在衬底上沉积栅极层的方法,该层包括多晶硅层和厚度约20到约80的硅化钨层。在图2中示意性示出可采用的集成处理系统100示例,该系统为Polycide Centura@系统,其可从加利福尼亚(CA),Santa Clara的应用材料公司(Applied Materials,Inc)购买得到。集成处理系统100可包括中心传送腔室102、输送机械手103、真空交换腔104、106和处理腔室110、114、116和118。处理腔室110、114、116和118为热化学气相沉积腔室。在一实施方式中,处理腔室110和116为POLYgenTM腔室,以及处理腔室114和118为DCS(二氯硅烷)xZ300腔室,它们都可从应用材料公司购买得到。POLYgenTM腔室为低压化学气相沉积(LPCVD)腔室,其可用于沉积本发明实施方式的掺杂层和富含多晶硅层。DCS xZ 300腔室为化学气相沉积腔室,其可用于根据本发明实施方式沉积硅化钨层。
在替代实施方式(未示出)中,可使用只具有两个处理腔室的PolycideCentura@系统,其中一个处理腔室为POLYgenTM腔室以及另一处理腔室为DCSxZ 300腔室。
以下将参照图2-图4描述一种在衬底上沉积栅极层的方法的实施例,其中该方法包括集成处理顺序。图3为包括栅极层的结构200的截面图。图4为概述该实施例的处理顺序的流程图。
在图3所示的实施方式中,如步骤302所示(图4),衬底202进入集成处理系统100中。衬底202包括其上的栅氧化层204。衬底202通过真空交换腔104或106进入集成处理系统100。衬底202通过输送机械手103传送至处理腔室110。如步骤304所示,在处理腔室110中在栅氧化层204上沉积掺杂多晶硅层206。接着如步骤306所示,在处理腔室110中在该掺杂多晶硅层206上沉积富含多晶硅层208。如步骤308所示,衬底202通过输送机械手103传送至处理腔室118中。如步骤310所示,在处理腔室118中的衬底202和其上各层暴露于硅烷中。衬底202和其上各层可暴露于硅烷中一段时间足以在其上沉积薄硅层210。接着如步骤312所示,在处理腔室118中沉积硅化钨层212。接下来,如步骤314所示在处理腔室114中的衬底202和其上各层暴露于硅烷中。衬底202和其上各层可暴露于硅烷一段时间足以形成富含硅的覆盖214。接着,如步骤316所示,从集成处理系统100移除衬底202。如步骤318所示,在衬底上各层的顶部沉积金属层216。该金属层可为钨层、氮化钨层或其组合。
虽然在本发明的一些实施方式中,多晶硅层沉积在衬底上并接着在衬底不暴露于空气的情况下,硅化钨层沉积在该多晶硅层上,而在其他实施方式中,在多晶硅层沉积之后和硅化钨层沉积之前,衬底可能暴露于空气中。在这些实施方式中,在多晶硅层沉积之后和硅化钨层沉积之前,可以通过将衬底暴露于氢氟酸(HF)中清洗衬底,例如采用HF冲洗衬底。
图5所示为根据本发明实施方式包括栅极层的半导体器件的示例。图5示出了包括具有源区504和漏区506的衬底502的NMOS晶体管500。衬底具有形成在其上并位于源区504和漏区506之间的栅氧化层508。栅极510包括根据本发明任意实施方式形成的栅极层(未示出)。隔离层512围绕栅氧化层508和栅极510。
进一步通过以下实施例描述本发明实施方式,如下实施例并非用于限定本发明要求保护的范围
实施例
将其上形成有氧化层的300mm衬底引入包括POLYgenTM和DCS xZ 300腔室的Polycide Centura@系统中。在POLYgenTM腔室中利用来自包括硅烷和用氢稀释的1%磷化氢的气体混合物执行热化学气相沉积工艺在衬底上沉积掺杂多晶硅层。在150Torr的气压和衬底支架温度600℃以及衬底温度约558℃下,并以磷化氢流速99sccm和乙硅烷流速50sccm通入约55秒的情况下,沉积掺杂多晶硅层。在沉积之前氮气流入腔室中并在沉积期间和之后持续通入。接着气压150Torr以及衬底支架温度约600℃和衬底温度约558℃的情况下以约80sccm流速通入乙硅烷约25秒,在该掺杂多晶硅层上沉积未掺杂多晶硅层。然后,衬底移入至DCS xZ 300腔室中。氩气以1000sccm通过二氯硅烷源端口进入腔室中并还以1000sccm通过六氟化钨源端口进入腔室中,同时在整个沉积硅化钨层过程中保持以该流速冲入氩气。接着,衬底暴露于流速300sccm的硅烷中35秒钟。然后在六氟化钨以流速2sccm引入腔室之前以流速60sccm通向腔室通入二氯硅烷10秒钟,并且二氯硅烷的气流和六氟化钨的气流一起维持20秒钟以沉积50硅化钨层。在衬底支架温度550℃和衬底温度约443℃以及气压1.2Torr的情况下,沉积硅化钨层。停止六氟化钨气流,并且维持二氯硅烷气流10秒钟。接着在气压2Torr,衬底支架温度550℃及衬底温度约443℃的条件下,将衬底暴露于流速100sccm的硅烷中10秒钟。
在沉积多晶硅层和硅化钨层的步骤之间,通过在不从集成处理系统移去衬底的情况下沉积多晶硅层和硅化钨层,使多晶硅层和硅化钨层之间由暴露于氧中引起的界面氧化最小化。在多晶硅层和硅化钨层沉积之间,衬底通过集成处理系统的传送腔室在腔室之间进行传送时,传送腔室通常维持在氮气环境中从而衬底在集成处理系统中期间最小化衬底在氧气中暴露量。传送腔室可具有的气压约2.5到约5Torr,诸如约3Torr。如图6所示,可在集成处理系统内(图6的相同条件集成线)沉积多晶硅层和硅化钨层,从而多晶硅层和硅化钨层之间界面处的氧浓度小于多晶硅层在第一处理腔室中沉积以及硅化钨层暴露于外部环境中,并且三小时后在第二处理腔室中沉积(空闲时间3小时线)的条件下该多晶硅层和硅化钨层之间界面处的氧浓度。虽然可通过用氢氟酸(HF)清洗衬底降低暴露在外部环境中的衬底的多晶硅层和硅化钨层之间界面处的氧浓度,但是优选地为在集成处理系统中沉积该多晶硅层和硅化钨层。
虽然以上主要描述了本发明的实施方式,但在不偏离本发明的精神范围内可对本发明的实施方式进行改进,并且其范围由以下的权利要求书限定。
Claims (20)
1.一种在衬底上沉积栅极层的方法,包括:
在衬底上沉积多晶硅层;
在所述多晶硅层上沉积具有厚度约20和约80之间的硅化钨层;以及
在所述硅化钨层上沉积金属层。
2.根据权利要求1所述的方法,其特征在于,沉积所述硅化钨层包括在热化学气相沉积工艺中使包括硅源和钨源的气体混合物发生反应。
3.根据权利要求2所述的方法,其特征在于,所述硅源为二氯硅烷以及所述钨源为六氟化钨。
4.根据权利要求2所述的方法,其特征在于,所述硅源为硅烷以及所述钨源为六氟化钨。
5.根据权利要求2所述的方法,其特征在于,沉积所述硅化钨层还包括在所述气体混合物发生反应之前在所述多晶硅层上沉积具有约5和10之间厚度的硅层。
6.根据权利要求5所述的方法,其特征在于,还包括将所述沉积的硅化钨层暴露于硅烷中。
7.根据权利要求1所述的方法,其特征在于,对所述多晶硅层进行掺杂,并且在所述硅化钨层沉积之前在所述多晶硅层上沉积包含低于所述多晶硅层掺杂浓度的富含多晶硅层。
8.根据权利要求1所述的方法,其特征在于,所述硅化钨层具有的硅与钨比例为约2.1∶1和约3.0∶1之间。
9.根据权利要求1所述的方法,其特征在于,所述金属层为钨层、氮化钨层或其组合。
10.根据权利要求1所述的方法,其特征在于,还包括在沉积所述多晶硅层之后和沉积所述硅化钨层之前清洗衬底,其中清洗衬底包括将所述衬底暴露于氢氟酸中。
11.一种在衬底上沉积栅极层的方法,包括:
在衬底上沉积多晶硅层;
在所述多晶硅层上沉积具有厚度约20和约80之间的硅化钨层,其中沉积所述硅化钨层包括:
将所述多晶硅层暴露于硅烷中;
反应包括二氯硅烷和六氟化钨的气体混合物以沉积所述硅化钨层;以及
将所述硅化钨层暴露于硅烷中;以及
在所述硅化钨层上沉积金属层。
12.根据权利要求11所述的方法,其特征在于,在衬底处理腔室中沉积所述硅化钨层,并且将所述硅化钨层暴露于硅烷中包括在约0.8Torr和约2Torr之间的气压条件下,以约100sccm和约700sccm之间的流速将硅烷导入衬底处理腔室中。
13.根据权利要求11所述的方法,其特征在于,将所述多晶硅层暴露于硅烷中包括在约5Torr和约10Torr之间的气压条件下,以流速约300sccm和约1200sccm之间将硅烷导入衬底处理腔室中。
14.根据权利要求11所述的方法,其特征在于,还包括在所述沉积硅化钨层之前,在所述掺杂多晶硅层上沉积富含多晶硅层,其中对所述多晶硅层进行掺杂,并且所述富含多晶硅层具有低于所述掺杂多晶硅层的掺杂浓度。
15.根据权利要求11所述的方法,其特征在于,在沉积所述硅化钨层期间,在加热至温度约400℃和约650℃之间的衬底支架构件上支撑所述衬底。
16.根据权利要求11所述的方法,其特征在于,还包括在沉积所述多晶硅层之后和沉积所述硅化钨层之前清洗所述衬底,其中清洗所述衬底包括将所述衬底暴露于氢氟酸中。
17.一种处理衬底的方法,包括:
在集成处理系统的第一腔室中的衬底上沉积多晶硅层;以及
在所述集成处理系统的第二腔室中的所述多晶硅层上沉积具有厚度在约20和约80之间的硅化钨层,其中在沉积所述多晶硅层之后和沉积所述硅化钨层之前衬底不暴露于所述集成处理系统的外部环境中。
18.根据权利要求17所述的方法,其特征在于,还包括在所述硅化钨层上沉积金属层,其中所述多晶硅层、硅化钨层和金属层构成衬底上的栅极层。
19.根据权利要求18所述的方法,其特征在于,所述金属层为钨层、氮化钨层或其组合。
20.根据权利要求17所述的方法,其特征在于,所述硅化钨层包括:将所述多晶硅层暴露于硅烷中;
使包括二氯硅烷或硅烷和六氟化钨的气体混合物发生反应以沉积所述硅化钨层;以及
将所述硅化钨层暴露于硅烷中。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US59258504P | 2004-07-30 | 2004-07-30 | |
US60/592,585 | 2004-07-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1989597A true CN1989597A (zh) | 2007-06-27 |
Family
ID=35429287
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2005800243869A Pending CN1989597A (zh) | 2004-07-30 | 2005-07-07 | 薄硅化钨层沉积和栅金属集成 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20060024959A1 (zh) |
JP (1) | JP2008508721A (zh) |
KR (1) | KR100871006B1 (zh) |
CN (1) | CN1989597A (zh) |
WO (1) | WO2006019603A2 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102939657A (zh) * | 2010-06-10 | 2013-02-20 | 应用材料公司 | 具有增强的离子化和rf功率耦合的低电阻率钨pvd |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7405158B2 (en) | 2000-06-28 | 2008-07-29 | Applied Materials, Inc. | Methods for depositing tungsten layers employing atomic layer deposition techniques |
US7964505B2 (en) * | 2005-01-19 | 2011-06-21 | Applied Materials, Inc. | Atomic layer deposition of tungsten materials |
US7732327B2 (en) | 2000-06-28 | 2010-06-08 | Applied Materials, Inc. | Vapor deposition of tungsten materials |
US7211144B2 (en) * | 2001-07-13 | 2007-05-01 | Applied Materials, Inc. | Pulsed nucleation deposition of tungsten layers |
US20030029715A1 (en) * | 2001-07-25 | 2003-02-13 | Applied Materials, Inc. | An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems |
US6833161B2 (en) * | 2002-02-26 | 2004-12-21 | Applied Materials, Inc. | Cyclical deposition of tungsten nitride for metal oxide gate electrode |
US7279432B2 (en) | 2002-04-16 | 2007-10-09 | Applied Materials, Inc. | System and method for forming an integrated barrier layer |
JP2007523994A (ja) * | 2003-06-18 | 2007-08-23 | アプライド マテリアルズ インコーポレイテッド | バリヤ物質の原子層堆積 |
US7550381B2 (en) | 2005-07-18 | 2009-06-23 | Applied Materials, Inc. | Contact clean by remote plasma and repair of silicide surface |
US8821637B2 (en) * | 2007-01-29 | 2014-09-02 | Applied Materials, Inc. | Temperature controlled lid assembly for tungsten nitride deposition |
US7910446B2 (en) * | 2007-07-16 | 2011-03-22 | Applied Materials, Inc. | Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices |
WO2009042713A1 (en) * | 2007-09-28 | 2009-04-02 | Applied Materials, Inc. | Vapor deposition of tungsten materials |
KR100940161B1 (ko) * | 2007-12-27 | 2010-02-03 | 주식회사 동부하이텍 | 모스트랜지스터 및 그 제조방법 |
US9230815B2 (en) | 2012-10-26 | 2016-01-05 | Appled Materials, Inc. | Methods for depositing fluorine/carbon-free conformal tungsten |
US11043386B2 (en) | 2012-10-26 | 2021-06-22 | Applied Materials, Inc. | Enhanced spatial ALD of metals through controlled precursor mixing |
KR102441431B1 (ko) * | 2016-06-06 | 2022-09-06 | 어플라이드 머티어리얼스, 인코포레이티드 | 표면을 갖는 기판을 프로세싱 챔버에 포지셔닝하는 단계를 포함하는 프로세싱 방법 |
WO2019093206A1 (ja) * | 2017-11-09 | 2019-05-16 | 国立研究開発法人産業技術総合研究所 | 半導体装置及びその製造方法 |
Family Cites Families (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4374700A (en) * | 1981-05-29 | 1983-02-22 | Texas Instruments Incorporated | Method of manufacturing silicide contacts for CMOS devices |
US4445266A (en) * | 1981-08-07 | 1984-05-01 | Mostek Corporation | MOSFET Fabrication process for reducing overlap capacitance and lowering interconnect impedance |
US4701423A (en) * | 1985-12-20 | 1987-10-20 | Ncr Corporation | Totally self-aligned CMOS process |
US4847111A (en) * | 1988-06-30 | 1989-07-11 | Hughes Aircraft Company | Plasma-nitridated self-aligned tungsten system for VLSI interconnections |
JP2558931B2 (ja) * | 1990-07-13 | 1996-11-27 | 株式会社東芝 | 半導体装置およびその製造方法 |
US5500249A (en) * | 1992-12-22 | 1996-03-19 | Applied Materials, Inc. | Uniform tungsten silicide films produced by chemical vapor deposition |
US5643633A (en) * | 1992-12-22 | 1997-07-01 | Applied Materials, Inc. | Uniform tungsten silicide films produced by chemical vapor depostiton |
US5997950A (en) * | 1992-12-22 | 1999-12-07 | Applied Materials, Inc. | Substrate having uniform tungsten silicide film and method of manufacture |
US5482749A (en) * | 1993-06-28 | 1996-01-09 | Applied Materials, Inc. | Pretreatment process for treating aluminum-bearing surfaces of deposition chamber prior to deposition of tungsten silicide coating on substrate therein |
JPH07176484A (ja) * | 1993-06-28 | 1995-07-14 | Applied Materials Inc | 窒化アルミニューム面を有するサセプタをサセプタの浄化後珪化タングステンで処理することによって半導体ウエハ上に珪化タングステンを一様に堆積する方法 |
US6090706A (en) * | 1993-06-28 | 2000-07-18 | Applied Materials, Inc. | Preconditioning process for treating deposition chamber prior to deposition of tungsten silicide coating on active substrates therein |
US5565382A (en) * | 1993-10-12 | 1996-10-15 | Applied Materials, Inc. | Process for forming tungsten silicide on semiconductor wafer using dichlorosilane gas |
US5480837A (en) * | 1994-06-27 | 1996-01-02 | Industrial Technology Research Institute | Process of making an integrated circuit having a planar conductive layer |
EP0704551B1 (en) * | 1994-09-27 | 2000-09-06 | Applied Materials, Inc. | Method of processing a substrate in a vacuum processing chamber |
JPH08264660A (ja) * | 1995-03-24 | 1996-10-11 | Nec Corp | 半導体装置の製造方法 |
US5480830A (en) * | 1995-04-04 | 1996-01-02 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of making depleted gate transistor for high voltage operation |
EP0746027A3 (en) * | 1995-05-03 | 1998-04-01 | Applied Materials, Inc. | Polysilicon/tungsten silicide multilayer composite formed on an integrated circuit structure, and improved method of making same |
EP0785574A3 (en) * | 1996-01-16 | 1998-07-29 | Applied Materials, Inc. | Method of forming tungsten-silicide |
US5710454A (en) * | 1996-04-29 | 1998-01-20 | Vanguard International Semiconductor Corporation | Tungsten silicide polycide gate electrode formed through stacked amorphous silicon (SAS) multi-layer structure. |
US5804499A (en) * | 1996-05-03 | 1998-09-08 | Siemens Aktiengesellschaft | Prevention of abnormal WSix oxidation by in-situ amorphous silicon deposition |
US5728615A (en) * | 1996-07-18 | 1998-03-17 | Vanguard International Semiconductor Corporation | Method of manufacturing a polysilicon resistor having uniform resistance |
US5705438A (en) * | 1996-10-18 | 1998-01-06 | Vanguard International Semiconductor Corporation | Method for manufacturing stacked dynamic random access memories using reduced photoresist masking steps |
US6297152B1 (en) * | 1996-12-12 | 2001-10-02 | Applied Materials, Inc. | CVD process for DCS-based tungsten silicide |
KR100425147B1 (ko) * | 1997-09-29 | 2004-05-17 | 주식회사 하이닉스반도체 | 반도체소자의제조방법 |
TW379371B (en) * | 1997-12-09 | 2000-01-11 | Chen Chung Jou | A manufacturing method of tungsten silicide-polysilicon gate structures |
US6291868B1 (en) * | 1998-02-26 | 2001-09-18 | Micron Technology, Inc. | Forming a conductive structure in a semiconductor device |
US6083815A (en) * | 1998-04-27 | 2000-07-04 | Taiwan Semiconductor Manufacturing Company | Method of gate etching with thin gate oxide |
US6524954B1 (en) * | 1998-11-09 | 2003-02-25 | Applied Materials, Inc. | Reduction of tungsten silicide resistivity by boron ion implantation |
US6110812A (en) * | 1999-05-11 | 2000-08-29 | Promos Technologies, Inc. | Method for forming polycide gate |
KR20010008590A (ko) * | 1999-07-02 | 2001-02-05 | 김영환 | 반도체장치의 게이트전극 제조방법 |
KR100393205B1 (ko) * | 2000-05-30 | 2003-07-31 | 삼성전자주식회사 | 자기정렬 콘택구조를 가진 메모리영역과 샐리사이디드된듀얼 게이트 구조의 로직영역이 병합된 mml 반도체소자 및 그 제조방법 |
US6350684B1 (en) * | 2000-06-15 | 2002-02-26 | Stmicroelectronics, Inc. | Graded/stepped silicide process to improve MOS transistor |
US20020008294A1 (en) * | 2000-07-21 | 2002-01-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing same |
KR100351907B1 (ko) * | 2000-11-17 | 2002-09-12 | 주식회사 하이닉스반도체 | 반도체 소자의 게이트 전극 형성방법 |
DE10115228B4 (de) * | 2001-03-28 | 2006-07-27 | Samsung Electronics Co., Ltd., Suwon | Steuerung des anormalen Wachstums bei auf Dichlorsilan (DCS) basierenden CVD-Polycid WSix-Filmen |
JP2002328775A (ja) * | 2001-04-27 | 2002-11-15 | Alps Electric Co Ltd | 座標入力装置 |
US20020162500A1 (en) * | 2001-05-02 | 2002-11-07 | Applied Materials, Inc. | Deposition of tungsten silicide films |
US6562675B1 (en) * | 2001-08-17 | 2003-05-13 | Cypress Semiconductor Corp. | Adjustment of threshold voltages of selected NMOS and PMOS transistors using fewer masking steps |
US20030040171A1 (en) * | 2001-08-22 | 2003-02-27 | Weimer Ronald A. | Method of composite gate formation |
US6699777B2 (en) * | 2001-10-04 | 2004-03-02 | Micron Technology, Inc. | Etch stop layer in poly-metal structures |
JP3781666B2 (ja) * | 2001-11-29 | 2006-05-31 | エルピーダメモリ株式会社 | ゲート電極の形成方法及びゲート電極構造 |
US20030123216A1 (en) * | 2001-12-27 | 2003-07-03 | Yoon Hyungsuk A. | Deposition of tungsten for the formation of conformal tungsten silicide |
US6833161B2 (en) * | 2002-02-26 | 2004-12-21 | Applied Materials, Inc. | Cyclical deposition of tungsten nitride for metal oxide gate electrode |
KR20040016696A (ko) * | 2002-08-19 | 2004-02-25 | 삼성전자주식회사 | 반도체장치의 전극형성방법 및 장치 |
JP2004087877A (ja) * | 2002-08-28 | 2004-03-18 | Fujitsu Ltd | 電界効果型半導体装置及びその製造方法 |
US20040061190A1 (en) * | 2002-09-30 | 2004-04-01 | International Business Machines Corporation | Method and structure for tungsten gate metal surface treatment while preventing oxidation |
US7534709B2 (en) * | 2003-05-29 | 2009-05-19 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP2005235987A (ja) * | 2004-02-19 | 2005-09-02 | Toshiba Corp | 半導体記憶装置及び半導体記憶装置の製造方法 |
-
2005
- 2005-07-07 WO PCT/US2005/024163 patent/WO2006019603A2/en active Application Filing
- 2005-07-07 CN CNA2005800243869A patent/CN1989597A/zh active Pending
- 2005-07-07 JP JP2007523590A patent/JP2008508721A/ja not_active Withdrawn
- 2005-07-07 KR KR1020077004146A patent/KR100871006B1/ko not_active IP Right Cessation
- 2005-07-12 US US11/179,274 patent/US20060024959A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102939657A (zh) * | 2010-06-10 | 2013-02-20 | 应用材料公司 | 具有增强的离子化和rf功率耦合的低电阻率钨pvd |
CN102939657B (zh) * | 2010-06-10 | 2016-08-10 | 应用材料公司 | 具有增强的离子化和rf功率耦合的低电阻率钨pvd |
Also Published As
Publication number | Publication date |
---|---|
KR20070037645A (ko) | 2007-04-05 |
JP2008508721A (ja) | 2008-03-21 |
WO2006019603A2 (en) | 2006-02-23 |
US20060024959A1 (en) | 2006-02-02 |
WO2006019603A3 (en) | 2006-07-13 |
KR100871006B1 (ko) | 2008-11-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1989597A (zh) | 薄硅化钨层沉积和栅金属集成 | |
US11908736B2 (en) | Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures | |
US7691742B2 (en) | Atomic layer deposition of tantalum-containing materials using the tantalum precursor TAIMATA | |
US7585762B2 (en) | Vapor deposition processes for tantalum carbide nitride materials | |
TWI661080B (zh) | 金屬矽化物的選擇性形成 | |
CN101540294B (zh) | 制造具有界面阻挡层的半导体器件的方法 | |
CN101308794A (zh) | 钨材料的原子层沉积 | |
US7358188B2 (en) | Method of forming conductive metal silicides by reaction of metal with silicon | |
TWI798582B (zh) | 第六族金屬沈積方法 | |
US7989339B2 (en) | Vapor deposition processes for tantalum carbide nitride materials | |
CN112510013A (zh) | 半导体装置及其制造方法 | |
US6908852B2 (en) | Method of forming an arc layer for a semiconductor device | |
JPH04348557A (ja) | 半導体装置の製造方法 | |
TWI283006B (en) | Method for forming tungsten nitride film | |
CN113851584A (zh) | 半导体结构的制备方法及半导体结构 | |
US20080171437A1 (en) | Methods of Forming Titanium-Containing Materials | |
JP7542046B2 (ja) | バリア層なしのタングステン堆積物 | |
JPH10189491A (ja) | 欠陥密度の低いTi−Si−N及びTi−B−Nベースの絶縁保護性障壁膜の製法 | |
JP2024513402A (ja) | 低温堆積プロセス |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |