CN110120388A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN110120388A
CN110120388A CN201910095219.7A CN201910095219A CN110120388A CN 110120388 A CN110120388 A CN 110120388A CN 201910095219 A CN201910095219 A CN 201910095219A CN 110120388 A CN110120388 A CN 110120388A
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Prior art keywords
chip
signal pad
semiconductor
package substrate
area
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CN201910095219.7A
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CN110120388B (zh
Inventor
金容勋
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体封装，包括：封装基板；封装基板上的逻辑芯片；封装基板上的存储器堆叠结构，包括沿第一方向堆叠的第一导体芯片和第二半导体芯片；以及封装基板和存储器堆叠结构之间的第一凸块。逻辑芯片和存储器堆叠结构沿着与第一方向交叉的第二方向在封装基板上间隔开。第一半导体芯片包括：电连接到第二半导体芯片的穿通孔、连接到穿通孔的芯片信号焊盘、以及电连接到芯片信号焊盘且具有与第一凸块接触的边缘信号焊盘的第一再分布层。沿第二方向的逻辑芯片和边缘信号焊盘之间的距离小于逻辑芯片和芯片信号焊盘之间的距离。

Description

半导体封装
相关申请的交叉引用
于2018年2月6日在韩国知识产权局提交的标题为“Semiconductor Package”的韩国专利申请No.10-2018-0014677通过引用整体并入本文中。
技术领域
实施例涉及一种半导体封装，更具体地，涉及其中逻辑芯片和存储器堆叠结构并排在基板上的半导体封装。
背景技术
通常，半导体封装包括安装在印刷电路板(PCB)上的半导体芯片以及将半导体芯片电连接到印刷电路板的接合线或凸块。
发明内容
根据示例性实施例，半导体封装可以包括：封装基板、封装基板上的逻辑芯片、封装基板上的存储器堆叠结构、以及封装基板与存储器堆叠结构之间的第一凸块。存储器堆叠结构可以包括第一半导体芯片、以及沿第一方向堆叠在第一半导体芯片上的第二半导体芯片。存储器堆叠结构可以沿第二方向与逻辑芯片间隔开，第二方向与第一方向交叉。第一半导体芯片可以包括：穿通孔，电连接到第二半导体芯片；芯片信号焊盘，连接到穿通孔；以及第一再分布层，电连接到芯片信号焊盘，并具有与第一凸块接触的边缘信号焊盘。沿第二方向的逻辑芯片和边缘信号焊盘之间距离小于逻辑芯片和芯片信号焊盘之间的距离。
根据示例性实施例，半导体封装可以包括：
包括路由线的封装基板、封装基板上的逻辑芯片、以及
封装基板上的存储器堆叠结构。存储器堆叠结构可以包括第一半导体芯片、以及沿第一方向堆叠在第一半导体芯片上的第二半导体芯片。存储器堆叠结构可以沿第二方向与逻辑芯片间隔开，第二方向与第一方向交叉。逻辑芯片的第一侧壁可以沿第二方向面对第一半导体芯片的第二侧壁。逻辑芯片可以包括与第一侧壁相邻的逻辑信号焊盘。第一半导体芯片可以包括：穿通孔，电连接到第二半导体芯片；芯片信号焊盘，连接到穿通孔；以及第一再分布层，电连接到芯片信号焊盘，并具有与第二侧壁相邻的边缘信号焊盘。逻辑信号焊盘和边缘信号焊盘可以通过路由线彼此电连接。
根据示例性实施例，半导体封装可以包括：封装基板；逻辑芯片，在封装基板上，并且包括多个第一信号焊盘；以及存储器堆叠结构，在封装基板上并且包括沿第一方向堆叠的多个半导体芯片，多个半导体芯片通过多个穿通孔彼此连接。存储器堆叠结构可以具有沿与第一方向交叉的第二方向与逻辑芯片相邻的第一区域、以及存储器堆叠结构的中心处的第二区域。存储器堆叠结构还可以包括：第一区域上的且沿第二方向与第二区域间隔开的多个第二信号焊盘；以及封装基板与第一信号焊盘和第二信号焊盘之间的多个凸块，多个凸块沿第二方向与第二区域间隔开。
附图说明
通过参考附图详细描述示例性实施例，特征对于本领域技术人员将变得显而易见，在附图中：
图1示出了示出根据示例性实施例的半导体封装的平面图。
图2是示出了示出根据示例性实施例的半导体封装的沿着图1的线I-I’截取的横截面图。
图3示出了示出图2的部分M的放大横截面图。
图4示出了示出根据示例性实施例的半导体封装的沿着图1的线I-I’截取的横截面图。
图5是示出了示出根据示例性实施例的半导体封装的沿着图1的线I-I’截取的横截面图。
图6示出了示出根据示例性实施例的半导体封装的平面图。
图7示出了示出根据示例性实施例的半导体封装的沿着图6的线I-I′截取的横截面图。
具体实施方式
图1示出了示出根据示例性实施例的半导体封装的平面图。图2示出了沿着图1的线I-I′截取的横截面图。图3示出了示出图2的部分M的放大横截面图。
参考图1至图3，可以在封装基板100上提供逻辑芯片210和存储器堆叠结构SS。逻辑芯片210和存储器堆叠结构SS可以在封装基板100上沿着z方向并排(例如，沿x方向间隔开)安装在封装基板100的顶表面上。例如，封装基板100可以是印刷电路板(PCB)或再分布基板。外部连接构件102(例如，焊球)可以设置在封装基板100的沿着z方向的与顶表面相对的底表面上。封装基板100可以在其顶表面上设置有着陆焊盘LDP。路由线(routing line)RL和至少一个通孔VI可以包括在封装基板100中。
逻辑芯片210可以在其中包括中心处理单元(CPU)、物理层区域和/或控制器。逻辑芯片210可以包括第一侧壁至第四侧壁S11、S12、S13和S14。逻辑芯片210的第一侧壁S11和第三侧壁S13可以沿x方向彼此相对。逻辑芯片210的第二侧壁S12和第四侧壁S14可以沿y方向彼此相对。逻辑芯片210可以包括与第一侧壁S11相邻的第一区域A11。第一区域A11可以沿y方向沿着第一侧壁S11延伸。第一区域A11可以是与逻辑芯片210的中心区域间隔开的边缘区域。
逻辑芯片210可以具有面对封装基板100的第一表面210a、和沿着z方向与第一表面210a相对的第二表面210b。逻辑芯片210可以包括与第一表面210a相邻的有源层202。有源层202可以包括逻辑芯片210的基板上的晶体管、和晶体管上的布线层。逻辑电路可以由有源层202中的晶体管和布线层构成。逻辑芯片210可以以面朝下的状态安装在封装基板100上，其中有源层202面对封装基板100。
逻辑芯片210的有源层202可以在其上设置有逻辑焊盘LP和逻辑信号焊盘LSP。逻辑信号焊盘LSP可以选择性地设置在逻辑芯片210的第一区域A11上。例如，逻辑信号焊盘LSP可以在逻辑芯片210的第一区域A11上，而可以不在任何其他区域(例如，逻辑芯片210的中心区域)上。逻辑焊盘LP可以选择性地设置在除了逻辑芯片210的第一区域A11之外的任何其他区域上。逻辑芯片210可以通过逻辑信号焊盘LSP接收或发送命令信号、访问信号和数据信号中的一个或多个。
凸块BP可以在逻辑芯片210和封装基板100之间。凸块BP可以在逻辑芯片210的逻辑焊盘LP与封装基板100的着陆焊盘LDP之间。凸块BP可以在逻辑芯片210的逻辑信号焊盘LSP与封装基板100的着陆焊盘LDP之间。凸块BP可以用于以倒装式接合方式将逻辑芯片210安装在封装基板100上。底部填充树脂层可以填充在逻辑芯片210和封装基板100之间。
存储器堆叠结构SS可以包括沿着z方向顺序堆叠在封装基板100上的第一半导体芯片至第四半导体芯片310、320、330和340。第一半导体芯片至第四半导体芯片310、320、330和340可以是存储器芯片。例如，第一半导体芯片至第四半导体芯片310、320、330和340中的每一个可以是低功率双倍数据速率同步动态随机存取存储器(LPDDR)，例如LPDDR1、LPDDR2、LPDDR3、LPDDR3E等。
第一半导体芯片至第四半导体芯片310、320、330和340在平面图中可以具有(例如，沿x方向和y方向)基本相同的形状和大小。第四半导体芯片340的厚度(例如，沿z方向)可以大于第一半导体芯片至第三半导体芯片310、320和330的厚度。第一半导体芯片310还可以包括附加的再分布层305，再分布层305不被包括在第二半导体芯片至第四半导体芯片320、330和340中。
第一半导体芯片至第四半导体芯片310、320、330和340中的每一个可以具有面对封装基板100的第一表面300a、和与第一表面300a相对直立的第二表面300b。第一半导体芯片至第四半导体芯片310、320、330和340中的每一个可以包括与第一表面300a相邻的有源层302。有源层302可以包括第一半导体芯片至第四半导体芯片310、320、330和340中的每一个的基板300上的晶体管、以及晶体管上的布线层。存储器电路可以由有源层302中的晶体管和布线层形成。例如，第一半导体芯片310可以以面朝下的状态安装在封装基板100上，其中有源层302面对封装基板100的顶表面。
第一半导体芯片至第三半导体芯片310、320和330中的每一个可以包括：穿通孔TV，其沿着z方向穿过第一半导体芯片至第三半导体芯片310、320和330并且电连接到有源层302。第四半导体芯片340可以不包括穿通孔TV。
第一半导体芯片至第四半导体芯片310、320、330和340中的每一个可以包括有源层302上的芯片信号焊盘CISP。芯片信号焊盘CISP可以是第一半导体芯片至第四半导体芯片310、320、330和340的命令输入/输出焊盘、访问输入/输出焊盘和/或数据输入/输出焊盘。例如，第一半导体芯片至第四半导体芯片310、320、330和340的芯片信号焊盘CISP可以(例如，沿z方向)彼此垂直重叠。
第一半导体芯片310可以包括：再分布层305，其覆盖有源层302上的芯片信号焊盘CISP。再分布层305可以包括边缘信号焊盘ESP、边缘电源焊盘EPP和导电线CL。
边缘信号焊盘ESP和边缘电源焊盘EPP可以位于再分布层305的下部上。导电线CL中的至少一个可以将芯片信号焊盘CISP和边缘信号焊盘ESP彼此电连接。每个边缘电源焊盘EPP可以是提供有电源电压或接地电压的电源焊盘。
第一半导体芯片310可以包括第一侧壁至第四侧壁S21、S22、S23和S24。第一半导体芯片310的第一侧壁S21和第三侧壁S23可以沿x方向彼此相对。第一半导体芯片310的第二侧壁S22和第四侧壁S24可以沿y方向彼此相对。逻辑芯片210的第一侧壁S11可以沿x方向与第一半导体芯片310的第一侧壁S21相邻并且间隔开。逻辑芯片210的第一侧壁S11可以面对第一半导体芯片310的第一侧壁S21。逻辑芯片210的第一侧壁S11和第一半导体芯片310的第一侧壁S21可以沿y方向彼此平行地延伸。
第一半导体芯片310可以包括与第一侧壁S21相邻的第一区域A21、第二区域A22、以及与第三侧壁S23相邻的第三区域A23。第二区域A22可以沿x方向插入在第一区域A21和第三区域A23之间。第二区域A22可以是第一半导体芯片310的中心区域。第一区域A21和第三区域A23中的每一个可以是沿x方向与第一半导体芯片310的中心区域间隔开的边缘区域。
由于逻辑芯片210的第一侧壁S11与第一半导体芯片310的第一侧壁S21相邻，因此逻辑芯片210的第一区域A11可以与第一半导体芯片310的第一区域A21相邻。
边缘信号焊盘ESP可以选择性地设置在第一半导体芯片310的第一区域A21上。芯片信号焊盘CISP可以选择性地设置在第一半导体芯片310的第二区域A22上。边缘电源焊盘EPP可以选择性地设置在第一半导体芯片310的第三区域A23上。
导电线CL将第一半导体芯片310的第二区域A22上的芯片信号焊盘CISP连接到第一半导体芯片310的第一区域A21上的边缘信号焊盘ESP。例如，导电线CL可以将第一半导体芯片310的输入/输出焊盘从第二区域A22再分布到第一区域A21。
将参考图3进一步详细讨论第一半导体芯片310的再分布层305。再分布层305可以包括第一绝缘层至第四绝缘层IL1、IL2、IL3和IL4，第一绝缘层至第四绝缘层IL1、IL2、IL3和IL4沿x方向朝向封装基板100的顶表面顺序地堆叠在第一半导体芯片310的有源层302上。芯片信号焊盘CISP可以位于第一绝缘层IL1中。第二绝缘层IL2可以具有：接触孔CTH，其暴露芯片信号焊盘CISP中的至少一个。
第二绝缘层IL2可以包括填充接触孔CTH并电连接到芯片信号焊盘CISP的导电线CL。导电线CL可以具有从第一半导体芯片310的第二区域A22沿x方向朝向第一半导体芯片310的第一区域A21延伸的线性形状。导电线CL可以包括阻挡层BL和阻挡层BL上的导电层ML。阻挡层BL可以在第二绝缘层IL2和导电层ML之间。阻挡层BL可以防止金属材料从导电层ML朝向有源层302扩散。例如，阻挡层BL可以包括钛(Ti)、氮化钛(TiN)或其组合。导电层ML可以包括铜(Cu)或铝(Al)。
导电线CL可以包括填充接触孔CTH的接触部分CNP、和沿x方向从接触部分CNP朝向边缘信号焊盘ESP延伸的线部分CLP。接触部分CNP可以与芯片信号焊盘CISP接触，并且线部分CLP可以与边缘信号焊盘ESP接触。
第三绝缘层IL3和第四绝缘层IL4可以覆盖导电线CL。边缘信号焊盘ESP可以位于导电线CL上的第四绝缘层IL4中。
返回参考图1至图3，凸块BP可以在第一半导体芯片至第四半导体芯片310、320、330和340之间。一个或多个底部填充树脂层可以填充在第一半导体芯片至第四半导体芯片310、320、330和340之间。凸块BP可以连接到第一半导体芯片至第三半导体芯片310、320和330的穿通孔TV。第一半导体芯片至第四半导体芯片310、320、330和340可以通过凸块BP和穿通孔TV彼此电连接。
例如，穿通孔TV可以连接到第一半导体芯片至第四半导体芯片310、320、330和340中的每一个的芯片信号焊盘CISP。通过芯片信号焊盘CISP和穿通孔TV、第一半导体芯片至第四半导体芯片310、320、330和340可以相互传送命令信号、访问信号和/或数据信号。
凸块BP可以在第一半导体芯片310和封装基板100之间。凸块BP可以在第一半导体芯片310的边缘信号焊盘ESP与封装基板100的着陆焊盘LDP之间。凸块BP可以在第一半导体芯片310的边缘电源焊盘EPP与封装基板100的着陆焊盘LDP之间。
在封装基板100与第一半导体芯片310的第二区域A22之间没有凸块BP。凸块BP可以与第一半导体芯片310的第二区域A22间隔开。例如，封装基板100和第一半导体芯片310的第二区域A22可以包括位于其间的绝缘材料(例如，底部填充树脂层或空气)。
凸块BP可以以倒装式接合的方式将第一半导体芯片310安装在封装基板100上。底部填充树脂层可以填充在第一半导体芯片310和封装基板100之间。
封装基板100中的路由线RL可以将逻辑芯片210的逻辑信号焊盘LSP电连接到第一半导体芯片310的边缘信号焊盘ESP。例如，路由线RL可以设置在一个布线层中。替代地，路由线RL可以设置在两个或更多个堆叠布线层中。第一通路VI1可以在路由线RL与电连接到逻辑芯片210的逻辑信号焊盘LSP的封装基板100的着陆焊盘LDP之间。第二通路VI2可以在路由线RL与电连接到第一半导体芯片310的边缘信号焊盘ESP的封装基板100的着陆焊盘LDP之间。
逻辑芯片210和存储器堆叠结构SS可以通过逻辑芯片210的逻辑信号焊盘LSP、封装基板100的路由线RL、再分布层305的边缘信号焊盘ESP、导电线CL和芯片信号焊盘CISP相互传送输入/输出信号。
由于逻辑芯片210的第一区域A11与第一半导体芯片310的第一区域A21相邻，所以逻辑信号焊盘LSP可以沿x方向与边缘信号焊盘ESP间隔开相对小的距离。例如，沿x方向，将逻辑信号焊盘LSP连接到边缘信号焊盘ESP的至少一个路由线RL的最小长度可以类似于逻辑芯片210的第一侧壁S11与第一半导体芯片310的第一侧壁S21之间的距离。
当在平面图中观察时，逻辑芯片210可以沿x方向与边缘信号焊盘ESP之一间隔开第一距离D1(参见图1)。当在平面图中观察时，逻辑芯片210可以沿x方向与芯片信号焊盘CISP之一间隔开第二距离D2(参见图1)。第一距离D1可以小于第二距离D2。
逻辑信号焊盘LSP和边缘信号焊盘ESP可以通过凸块BP和路由线RL以相对小的距离(例如，第一距离D1)连接，这可以增加逻辑芯片210和存储器堆叠结构SS之间的信号传输速度。因此，根据示例性实施例的半导体封装可以改善电特性并提高操作速度。逻辑芯片210和存储器堆叠结构SS可以并排安装在封装基板100上，该布置可以减小沿着根据示例性实施例的半导体封装的z方向的厚度。
图4示出了示出根据示例性实施例的半导体封装的沿着图1的线I-I’截取的横截面图。在下面的实施例中，将省略与上面参照图1至图3讨论的技术特征重复的技术特征的详细描述，并且将详细解释其间的差异。
参照图1和图4，存储器堆叠结构SS的第一半导体芯片至第四半导体芯片310、320、330和340中的每一个可以包括基板300和基板300上的再分布层305。再分布层305可以设置在有源层302上，以电连接到有源层302中的存储器电路。
再分布层305可以包括边缘信号焊盘ESP、中心信号焊盘CSP、边缘电源焊盘EPP和导电线CL。边缘信号焊盘ESP、中心信号焊盘CSP和边缘电源焊盘EPP可以通过导电线CL电连接到有源层302。边缘信号焊盘ESP、中心信号焊盘CSP和边缘电源焊盘EPP可以设置在再分布层305的下部上。
边缘信号焊盘ESP可以选择性地设置在第一半导体芯片310的第一区域A21上。中心信号焊盘CSP可以选择性地设置在第一半导体芯片310的第二区域A22上。边缘电源焊盘EPP可以选择性地设置在第一半导体芯片310的第三区域A23上。
第二半导体芯片至第四半导体芯片320、330和340中的每一个可以包括与第一半导体芯片310的再分布层305基本相同的再分布层305。因此，除了中心信号焊盘CSP之外，第二半导体芯片至第四半导体芯片320、330和340中的每一个因此可以包括边缘信号焊盘ESP。第四半导体芯片340的沿z方向的厚度可以与第一半导体芯片至第三半导体芯片3210、320和330的厚度相同。
在一些实施例中，凸块BP可以位于第二半导体芯片至第四半导体芯片320、330和340中的每一个的中心信号焊盘CSP上。在第二半导体芯片至第四半导体芯片320、330和340中的每一个的边缘信号焊盘ESP上可以不设置凸块BP。例如，第二半导体芯片至第四半导体芯片320、330和340中的每一个的边缘信号焊盘ESP可以是虚设焊盘。
在一些实施例中，可以在第一半导体芯片310的中心信号焊盘CSP上不设置凸块BP。凸块BP可以设置在第一半导体芯片310的边缘信号焊盘ESP上。例如，第一半导体芯片310的中心信号焊盘CSP可以是虚设焊盘。
第一半导体芯片310的边缘信号焊盘ESP可以比中心信号焊盘CSP更靠近逻辑芯片210。对于连接到封装基板100的第一半导体芯片310，除了中心信号焊盘CSP之外，凸块BP可以选择性地设置在边缘信号焊盘ESP上。在这样的配置中，可以减小逻辑芯片210和存储器堆叠结构SS之间的电连接路径。
图5示出了示出根据示例性实施例的半导体封装的沿着图1的线I-I’截取的横截面图。在下面的实施例中，将省略与上面参照图1至图3讨论的技术特征重复的技术特征的详细描述，并且将详细解释其间的差异。
参考图1和图5，存储器堆叠结构SS可以包括第一半导体芯片至第四半导体芯片310、320、330和340，并且还可以包括连接基板350。连接基板350可以设置在第一半导体芯片310和封装基板100之间。连接基板350可以包括边缘信号焊盘ESP、中心信号焊盘CSP、边缘电源焊盘EPP和导电线CL。连接基板350可以与再分布层305基本相同，但是沿z方向与第一基板310间隔开。
连接基板350可以包括第一侧壁至第四侧壁S21、S22、S23和S24，类似于第一半导体芯片至第四半导体芯片310、320、330和340。连接基板350的第一侧壁S21和第三侧壁S23可以沿x方向彼此相对。连接基板350的第二侧壁S22和第四侧壁S24可以沿y方向彼此相对。逻辑芯片210的第一侧壁S11可以与连接基板350的第一侧壁S21相邻。逻辑芯片210的第一侧壁S11可以面对连接基板350的第一侧壁S21。
连接基板350可以包括与第一侧壁S21相邻的第一区域A21、第二区域A22、以及与第三侧壁S23相邻的第三区域A23。第二区域A22可以在第一区域A21和第三区域A23之间。第二区域A22可以是连接基板350的中心区域。第一区域A21和第三区域A23中的每一个可以是沿x方向与连接基板350的中心区域间隔开的边缘区域。
连接基板350的边缘信号焊盘ESP可以选择性地设置在连接基板350的第一区域A21上。连接基板350的导电线CL可以将输入/输出信号从连接到第一半导体芯片310的中心信号焊盘CSP发送给边缘信号焊盘ESP。例如，连接基板350可以将第一半导体芯片310的输入/输出焊盘从第二区域A22再分布到第一区域A21。
连接基板350的边缘信号焊盘ESP可以相对靠近逻辑芯片210。在这样的配置中，在逻辑芯片210和存储器堆叠结构SS之间的电连接路径可以减小。
图6示出了示出根据示例性实施例的半导体封装的平面图。图7示出了沿着图6的线I-I′截取的横截面图。在下面的实施例中，将省略与上面参照图1至图3讨论的技术特征重复的技术特征的详细描述，并且将详细解释其间的差异。
参考图6和图7，第一半导体芯片至第四半导体芯片310、320、330和340中的每一个可以包括有源层302上的芯片信号焊盘CISP。第一半导体芯片至第四半导体芯片310、320、330和340中的每一个的芯片信号焊盘CISP不仅可以在第二区域A22上，而且可以在第一区域A21和第三区域A23上。例如，芯片信号焊盘CISP可以均匀地分布在第一半导体芯片至第四半导体芯片310、320、330和340中的每一个的整个区域上。第一半导体芯片至第四半导体芯片310、320、330和340的芯片信号焊盘CISP可以(例如，沿着z方向)彼此垂直地重叠。芯片信号焊盘CISP可以是第一半导体芯片至第四半导体芯片310、320、330和340的命令输入/输出焊盘、访问输入/输出焊盘和/或数据输入/输出焊盘。
穿通孔TV可以连接到第一半导体芯片至第四半导体芯片310、320、330和340中的每一个的芯片信号焊盘CISP。因此，穿通孔TV不仅可以设置在第二区域A22上，而且可以设置在第一区域A21和第三区域A23上。
第一半导体芯片310可以包括有源层302上的再分布层305、和芯片信号焊盘CISP。再分布层305可以包括边缘信号焊盘ESP、边缘电源焊盘EPP和导电线CL。
边缘信号焊盘ESP和边缘电源焊盘EPP可以设置在再分布层305的下部上。导电线CL中的至少一个可以将第一半导体芯片310的芯片信号焊盘CISP电连接到再分布层305的边缘信号焊盘ESP。每个边缘电源焊盘EPP可以是提供有电源电压或接地电压的电源焊盘。
再分布层305可以将分布在第一半导体芯片310的第一区域至第三区域A21、A22和A23上的芯片信号焊盘CISP连接到集中在与逻辑芯片210相邻的第一区域A21上的边缘信号焊盘ESP。例如，再分布层305可以以这样的方式再分布第一半导体芯片310的输入/输出焊盘：再分布的输入/输出焊盘可以集中在第一区域A21上。
根据一个或多个实施例，半导体封装具有在逻辑芯片与存储器堆叠结构之间的快速信号传输，从而改善电特性并提高操作速度。逻辑芯片和存储器堆叠结构可以并排布置，以减小半导体封装沿堆叠方向的大小。
本文已经公开了示例实施例，并且尽管采用了特定术语，但是它们仅用于且将被解释为一般的描述性意义，而不是为了限制的目的。在一些情况下，如提交本申请的本领域普通技术人员应认识到，除非另有明确说明，否则结合特定实施例描述的特征、特性和/或元件可以单独使用或与其他实施例描述的特征、特性和/或元件相结合使用。因此，本领域技术人员将理解，在不脱离如所附权利要求中阐述的本发明的精神和范围的前提下，可以进行形式和细节上的各种改变。

Claims (20)

1.一种半导体封装，包括：
封装基板；
所述封装基板上的逻辑芯片；
所述封装基板上的存储器堆叠结构，所述存储器堆叠结构包括第一半导体芯片、以及沿第一方向堆叠在所述第一半导体芯片上的第二半导体芯片，所述存储器堆叠结构沿第二方向与所述逻辑芯片间隔开，所述第二方向与所述第一方向交叉；以及
所述封装基板与所述存储器堆叠结构之间的第一凸块，
其中，所述第一半导体芯片包括：
穿通孔，电连接到所述第二半导体芯片；
芯片信号焊盘，连接到所述穿通孔；以及
第一再分布层，电连接到所述芯片信号焊盘，并具有与所述第一凸块接触的边缘信号焊盘，
其中，沿所述第二方向，所述逻辑芯片与所述边缘信号焊盘之间的距离小于所述逻辑芯片与所述芯片信号焊盘之间的距离。
2.根据权利要求1所述的半导体封装，其中：
所述第一半导体芯片具有与所述逻辑芯片相邻的第一区域、以及在所述第一半导体芯片的中心处的第二区域，
所述边缘信号焊盘在所述第一区域上，并且
所述芯片信号焊盘在所述第二区域上。
3.根据权利要求2所述的半导体封装，其中：
所述芯片信号焊盘包括多个芯片信号焊盘，
所述多个芯片信号焊盘中的第一信号焊盘在所述第一区域上，并且
所述多个芯片信号焊盘中的第二信号焊盘在所述第二区域上。
4.根据权利要求2所述的半导体封装，其中：
所述第一半导体芯片还具有第三区域，
所述第三区域沿所述第二方向在所述第一区域与所述第二区域之间，
所述第一再分布层还包括边缘电源焊盘，所述边缘电源焊盘连接到所述封装基板并被提供有电源电压或接地电压，
所述边缘电源焊盘在所述第三区域上。
5.根据权利要求1所述的半导体封装，其中，所述第一再分布层沿所述第一方向与所述存储器堆叠结构间隔开。
6.根据权利要求1所述的半导体封装，其中，所述第一再分布层还包括：导电线，所述导电线沿所述第二方向从所述芯片信号焊盘朝向所述边缘信号焊盘延伸，并且将所述芯片信号焊盘和所述边缘信号焊盘彼此电连接。
7.根据权利要求1所述的半导体封装，其中，所述封装基板包括路由线，通过所述路由线在所述逻辑芯片与所述边缘信号焊盘之间传输输入/输出信号。
8.根据权利要求1所述的半导体封装，其中：
所述第二半导体芯片包括第二再分布层，所述第二再分布层的结构与所述第一再分布层的结构基本相同，并且
所述第二再分布层的边缘信号焊盘为虚设焊盘。
9.根据权利要求8所述的半导体封装，其中：
所述存储器堆叠结构还包括所述第一半导体芯片与所述第二半导体芯片之间的第二凸块，并且
所述第二半导体芯片的中心处的芯片信号焊盘与所述第二凸块接触，所述芯片信号焊盘沿所述第二方向与所述第二再分布层的边缘信号焊盘间隔开。
10.根据权利要求1所述的半导体封装，还包括所述封装基板与所述逻辑芯片之间的第二凸块，其中
所述逻辑芯片具有面对所述存储器堆叠结构的第一侧壁，
所述逻辑芯片包括与所述第一侧壁相邻且与所述第二凸块接触的逻辑信号焊盘，并且
所述逻辑信号焊盘和所述边缘信号焊盘通过所述封装基板彼此电连接。
11.一种半导体封装，包括：
包括路由线的封装基板；
所述封装基板上的逻辑芯片；以及
所述封装基板上的存储器堆叠结构，所述存储器堆叠结构包括第一半导体芯片、以及沿第一方向堆叠在所述第一半导体芯片上的第二半导体芯片，所述存储器堆叠结构沿第二方向与所述逻辑芯片间隔开，所述第二方向与所述第一方向交叉，其中
所述逻辑芯片的第一侧壁沿所述第二方向面对所述第一半导体芯片的第二侧壁，
所述逻辑芯片包括与所述第一侧壁相邻的逻辑信号焊盘，
所述第一半导体芯片包括：
穿通孔，电连接到所述第二半导体芯片；
芯片信号焊盘，连接到所述穿通孔；以及
第一再分布层，电连接到所述芯片信号焊盘，并具有与所述第二侧壁相邻的边缘信号焊盘，并且
所述逻辑信号焊盘和所述边缘信号焊盘通过所述路由线彼此电连接。
12.根据权利要求11所述的半导体封装，还包括所述封装基板与所述边缘信号焊盘之间的第一凸块，其中
所述第一半导体芯片具有与所述第二侧壁相邻的第一区域、以及所述第一半导体芯片的中心处的第二区域，
所述边缘信号焊盘在所述第一区域上，并且
所述第一凸块沿所述第二方向与所述第二区域间隔开。
13.根据权利要求12所述的半导体封装，还包括：所述封装基板与所述第一半导体芯片的第二区域之间的绝缘材料。
14.根据权利要求11所述的半导体封装，其中，所述第一再分布层还包括：导电线，所述导电线沿所述第二方向从所述芯片信号焊盘朝向所述边缘信号焊盘延伸，并且将所述芯片信号焊盘和所述边缘信号焊盘彼此电连接。
15.根据权利要求11所述的半导体封装，其中：
所述第二半导体芯片包括第二再分布层，所述第二再分布层的结构与所述第一再分布层的结构基本相同，并且
所述第二再分布层的边缘信号焊盘为虚设焊盘。
16.一种半导体封装，包括：
封装基板；
所述封装基板上的逻辑芯片，包括多个第一信号焊盘；
所述封装基板上的存储器堆叠结构，包括沿第一方向堆叠的多个半导体芯片，所述多个半导体芯片通过多个穿通孔彼此连接，所述存储器堆叠结构具有沿与所述第一方向交叉的第二方向与所述逻辑芯片相邻的第一区域、以及所述存储器堆叠结构的中心处的第二区域，所述存储器堆叠结构还包括在所述第一区域上且沿所述第二方向与所述第二区域间隔开的多个第二信号焊盘；以及
所述封装基板与所述第一信号焊盘和所述第二信号焊盘之间的多个凸块，所述多个凸块沿所述第二方向与所述第二区域间隔开。
17.根据权利要求16所述的半导体封装，还包括所述封装基板与所述存储器堆叠结构的第二区域之间的绝缘材料。
18.根据权利要求16所述的半导体封装，其中，所述逻辑芯片和所述存储器堆叠结构沿所述第二方向间隔开并倒装式安装在所述封装基板上。
19.根据权利要求16所述的半导体封装，其中，所述封装基板包括多个路由线，通过所述多个路由线在所述第一信号焊盘与所述第二信号焊盘之间传输信号。
20.根据权利要求16所述的半导体封装，其中，所述穿通孔在所述第二区域中并且沿所述第二方向与所述第一区域间隔开。
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