CN109473357A - Mos晶体管的制造方法 - Google Patents
Mos晶体管的制造方法 Download PDFInfo
- Publication number
- CN109473357A CN109473357A CN201811267610.2A CN201811267610A CN109473357A CN 109473357 A CN109473357 A CN 109473357A CN 201811267610 A CN201811267610 A CN 201811267610A CN 109473357 A CN109473357 A CN 109473357A
- Authority
- CN
- China
- Prior art keywords
- mos transistor
- manufacturing
- depth
- carbon
- injection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 73
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 73
- 239000007943 implant Substances 0.000 claims abstract description 44
- 238000002347 injection Methods 0.000 claims abstract description 44
- 239000007924 injection Substances 0.000 claims abstract description 44
- 238000005468 ion implantation Methods 0.000 claims abstract description 41
- 239000012535 impurity Substances 0.000 claims abstract description 38
- 125000001475 halogen functional group Chemical group 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 230000002411 adverse Effects 0.000 claims abstract description 7
- 230000000694 effects Effects 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims description 28
- 239000002019 doping agent Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- -1 hafnium silicate oxygen compound Chemical class 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 229910052735 hafnium Inorganic materials 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052712 strontium Inorganic materials 0.000 claims description 4
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 claims description 4
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 4
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052746 lanthanum Inorganic materials 0.000 claims 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000003892 spreading Methods 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 6
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 6
- 239000000203 mixture Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- DCRGHMJXEBSRQG-UHFFFAOYSA-N 1-[1-(cyclooctylmethyl)-5-(hydroxymethyl)-3,6-dihydro-2H-pyridin-4-yl]-3-ethyl-2-benzimidazolone Chemical compound O=C1N(CC)C2=CC=CC=C2N1C(CC1)=C(CO)CN1CC1CCCCCCC1 DCRGHMJXEBSRQG-UHFFFAOYSA-N 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 229910052727 yttrium Inorganic materials 0.000 description 2
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开了一种MOS晶体管的制造方法,包括步骤:步骤一、在半导体衬底表面的第二导电类型阱的表面形成栅极结构;步骤二、进行轻掺杂漏站点工艺,包括如下分步骤:步骤21、进行非结晶离子注入;步骤22、进行两次以上的碳离子注入,调节各次碳离子注入的注入角度和注入深度,从而保证各深度处的碳阻挡区的第一侧都位于后续形成的口袋注入区的第一侧的内侧,减少或防止口袋注入区的杂质向沟道侧的第二导电类型阱中扩散。步骤23、进行口袋离子注入形成口袋注入区。步骤24、进行轻掺杂漏注入。本发明能减少或防止口袋注入区的杂质向沟道侧的阱中扩散从而减少或防止对沟道产生不利影响,抑制沟道中的掺杂的随机波动,提高器件的稳定性。
Description
技术领域
本发明涉及一种半导体集成电路制造方法,特别涉及一种MOS晶体管的制造方法。
背景技术
如图1所示,是现有MOS晶体管的制造方法形成的器件结构图,现有MOS晶体管的制造方法包括如下步骤:
步骤一、在半导体衬底表面形成有第二导电类型阱101,在所述第二导电类型阱101的表面形成栅极结构,被所述栅极结构所覆盖区域的所述第二导电类型阱101表面用于形成沟道。
所述半导体衬底为硅衬底。
步骤二、进行轻掺杂漏站点工艺,包括如下分步骤:
步骤21、进行非结晶离子注入形成硅非晶化区104。
所述非结晶离子注入的注入杂质为硅或锗。
步骤22、进行一次碳离子注入形成碳阻挡区106。
步骤23、进行口袋离子注入形成所述口袋注入区107。
步骤24、进行轻掺杂漏注入形成轻掺杂漏区105。
所述轻掺杂漏区105的深度大于所述硅非晶化区104的深度,所述口袋注入区107的深度大于所述轻掺杂漏区105的深度。
所述非结晶离子注入、所述碳离子注入、所述口袋离子注入和所述轻掺杂漏注入都和所述栅极结构的侧面自对准。
还包括如下步骤:
步骤三、在所述栅极结构的侧面形成侧墙。
步骤四、以所述侧墙的侧面为自对准条件进行源漏注入在所述栅极结构的两侧形成源区108a和漏区108b。
MOS晶体管为NMOS管,所述第二导电类型为P型,所述口袋离子注入的注入杂质为P型杂质,所述轻掺杂漏注入的注入杂质为N型杂质,所述源漏注入的注入杂质为N型杂质。也能为:MOS晶体管为PMOS管,所述第二导电类型为N型,所述口袋离子注入的注入杂质为N型杂质,所述轻掺杂漏注入的注入杂质为P型杂质,所述源漏注入的注入杂质为P型杂质。
图1中的,所述栅极结构由栅介质层102和多晶硅栅103叠加而成。
MOS晶体管为28nm以下工艺节点的HKMG类型器件,步骤一中的所述栅极结构为伪栅,所述伪栅在所述源区108a和所述漏区108b形成之后被去除,之后在所述伪栅的去除区域形成HKMG。
HKMG由高介电常数层组成栅介质层102和金属栅叠加而成。
所述高介电常数层的材料包括二氧化硅,氮化硅,三氧化二铝,五氧化二钽,氧化钇,硅酸铪氧化合物,二氧化铪,氧化镧,二氧化锆,钛酸锶,硅酸锆氧化合物。
所述金属栅的材料为Al。
也能为:MOS晶体管为28nm以下工艺节点的LP类型器件即28LP类型器件,此时,所述栅介质层102为氮氧化硅层。
由图1所示可知,现有方法采用一次碳离子注入形成所述碳阻挡区106具有如下缺陷,碳阻挡区106由于是采用带角度注入实现,使得在碳阻挡区106的深度大于口袋注入区107的深度的条件下,碳阻挡区106的顶部无法保证对口袋注入区107的良好覆盖,如虚线圈109所示;这样在碳阻挡区106对口袋注入区107覆盖薄弱的区域容易产生口袋注入区107的杂质向沟道区域扩散。由口袋注入区107的掺杂类型和沟道区域中的掺杂类型相同,例如:对于NMOS管都是P型,杂质扩散后就会是沟道区域的P型掺杂增加,从而会提高器件的阈值电压;同时,由于在同一半导体衬底上会集成有多个MOS晶体管,而各区域处的口袋注入区107的杂质向沟道区域的扩散量并不会一致,这就使得口袋注入区107的杂质扩散对各区域的NMOS管的阈值电压的影响不一致,会有波动(variation),这种波动是随掺杂随机波动(random dopant fluctuation)。
发明内容
本发明所要解决的技术问题是提供一种MOS晶体管的制造方法,能减少或防止口袋注入区的杂质向沟道侧的阱中扩散从而减少或防止对沟道产生不利影响,抑制沟道中的掺杂的随机波动,提高器件的稳定性。
为解决上述技术问题,本发明提供的MOS晶体管的制造方法包括如下步骤:
步骤一、在半导体衬底表面形成有第二导电类型阱,在所述第二导电类型阱的表面形成栅极结构,被所述栅极结构所覆盖区域的所述第二导电类型阱表面用于形成沟道。
步骤二、进行轻掺杂漏站点工艺,包括如下分步骤:
步骤21、进行非结晶离子注入形成硅非晶化区。
步骤22、进行碳离子注入形成碳阻挡区,所述碳离子注入的次数至少包括两次,调节各次碳离子注入的注入角度和注入深度来调节所述碳阻挡区的深度以及各深度处的所述碳阻挡区的第一侧向所述栅极结构内侧延伸的横向距离,并保证后续形成的口袋注入区位于所述碳阻挡区的深度范围内且在各所述深度处所述碳阻挡区的第一侧都位于所述口袋注入区的第一侧的内侧,减少或防止所述口袋注入区的第一侧向所述栅极结构所覆盖区域的所述第二导电类型阱中扩散并进而减少或防止对沟道产生不利影响。
步骤23、进行口袋离子注入形成所述口袋注入区。
步骤24、进行轻掺杂漏注入形成轻掺杂漏区。
进一步的改进是,所述半导体衬底为硅衬底。
进一步的改进是,所述非结晶离子注入的注入杂质为硅或锗。
进一步的改进是,步骤22中所述碳离子注入的次数为两次,第一次碳离子注入的注入深度大于第二次碳离子注入的注入深度以及所述第一次碳离子注入的注入角度小于所述第二碳离子注入的注入角度。
进一步的改进是,所述轻掺杂漏区的深度大于所述硅非晶化区的深度,所述口袋注入区的深度大于所述轻掺杂漏区的深度。
进一步的改进是,所述非结晶离子注入、所述碳离子注入、所述口袋离子注入和所述轻掺杂漏注入都和所述栅极结构的侧面自对准。
进一步的改进是,还包括如下步骤:
步骤三、在所述栅极结构的侧面形成侧墙。
步骤四、以所述侧墙的侧面为自对准条件进行源漏注入在所述栅极结构的两侧形成源区和漏区。
进一步的改进是,MOS晶体管为NMOS管,所述第二导电类型为P型,所述口袋离子注入的注入杂质为P型杂质,所述轻掺杂漏注入的注入杂质为N型杂质,所述源漏注入的注入杂质为N型杂质。
进一步的改进是,MOS晶体管为PMOS管,所述第二导电类型为N型,所述口袋离子注入的注入杂质为N型杂质,所述轻掺杂漏注入的注入杂质为P型杂质,所述源漏注入的注入杂质为P型杂质。
进一步的改进是,所述栅极结构由栅介质层和多晶硅栅叠加而成。
进一步的改进是,MOS晶体管为28nm以下工艺节点的低功耗(low power,LP)类型器件,所述栅介质层为氮氧化硅层。
进一步的改进是,MOS晶体管为28nm以下工艺节点的HKMG类型器件,步骤一中的所述栅极结构为伪栅,所述伪栅在所述源区和所述漏区形成之后被去除,之后在所述伪栅的去除区域形成HKMG。
进一步的改进是,HKMG由高介电常数层组成栅介质层和金属栅叠加而成。
进一步的改进是,所述高介电常数层的材料包括二氧化硅,氮化硅,三氧化二铝,五氧化二钽,氧化钇,硅酸铪氧化合物,二氧化铪,氧化镧,二氧化锆,钛酸锶,硅酸锆氧化合物。
进一步的改进是,所述金属栅的材料为Al。
本发明在轻掺杂漏站点工艺中对碳阻挡层的形成工艺做了特别的设定,主要是将碳阻挡层的碳离子注入分成了两次以上,各次碳离子注入的注入角度和注入深度不同,这样能够补偿单次碳离子注入所带来的不足,使得能同时是碳阻挡层的深度和各深度处的碳阻挡区的第一侧向栅极结构内侧延伸的横向距离都得到调节,从而使得在各深度处都能实现碳阻挡区的第一侧都位于口袋注入区的第一侧的内侧,由于就能减少或防止口袋注入区的第一侧向栅极结构所覆盖区域的第二导电类型阱中扩散并进而减少或防止对沟道产生不利影响,从而能抑制沟道中的掺杂的随机波动,提高器件的稳定性。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明:
图1是现有MOS晶体管的制造方法形成的器件结构图;
图2是本发明实施例MOS晶体管的制造方法的流程图;
图3是本发明实施例MOS晶体管的制造方法形成的器件结构图。
具体实施方式
如图2所示,是本发明实施例MOS晶体管的制造方法的流程图;如图3所示,是本发明实施例MOS晶体管的制造方法形成的器件结构图,本发明实施例MOS晶体管的制造方法包括如下步骤:
步骤一、在半导体衬底表面形成有第二导电类型阱1,在所述第二导电类型阱1的表面形成栅极结构,被所述栅极结构所覆盖区域的所述第二导电类型阱1表面用于形成沟道。
所述半导体衬底为硅衬底。
步骤二、进行轻掺杂漏站点工艺,包括如下分步骤:
步骤21、进行非结晶离子注入形成硅非晶化区4。
所述非结晶离子注入的注入杂质为硅或锗。
步骤22、进行碳离子注入形成碳阻挡区6,所述碳离子注入的次数至少包括两次,调节各次碳离子注入的注入角度和注入深度来调节所述碳阻挡区6的深度以及各深度处的所述碳阻挡区6的第一侧向所述栅极结构内侧延伸的横向距离,并保证后续形成的口袋注入区7位于所述碳阻挡区6的深度范围内且在各所述深度处所述碳阻挡区6的第一侧都位于所述口袋注入区7的第一侧的内侧,减少或防止所述口袋注入区7的第一侧向所述栅极结构所覆盖区域的所述第二导电类型阱1中扩散并进而减少或防止对沟道产生不利影响。
图3所示的本发明实施例方法中,步骤22中所述碳离子注入的次数为两次,第一次碳离子注入的注入深度大于第二次碳离子注入的注入深度以及所述第一次碳离子注入的注入角度小于所述第二碳离子注入的注入角度。所述第一次碳离子注入形成的注入区为区域6a,所述第二次碳离子注入形成的注入区为区域6b;可以看出,区域6a的深度更深,但是由于所述第一次碳离子注入的注入角度更小即更加接近90度,这样在靠近所述半导体衬底的表面位置处区域6a的第一侧会位于区域6b的第一侧的外侧,这样,区域6b正好可以补偿区域6a的第一侧向栅极内部延伸距离不足的缺陷。所以使得区域6a的能保证对所述口袋注入区7的底部的内侧覆盖,以及区域6a能保证对所述口袋注入区7的顶部的内侧覆盖。
步骤23、进行口袋离子注入形成所述口袋注入区7。
步骤24、进行轻掺杂漏注入形成轻掺杂漏区5。
所述轻掺杂漏区5的深度大于所述硅非晶化区4的深度,所述口袋注入区7的深度大于所述轻掺杂漏区5的深度。
所述非结晶离子注入、所述碳离子注入、所述口袋离子注入和所述轻掺杂漏注入都和所述栅极结构的侧面自对准。
还包括如下步骤:
步骤三、在所述栅极结构的侧面形成侧墙。
步骤四、以所述侧墙的侧面为自对准条件进行源漏注入在所述栅极结构的两侧形成源区8a和漏区8b。
本发明实施例中,MOS晶体管为NMOS管,所述第二导电类型为P型,所述口袋离子注入的注入杂质为P型杂质,所述轻掺杂漏注入的注入杂质为N型杂质,所述源漏注入的注入杂质为N型杂质。在其他实施例中也能为:MOS晶体管为PMOS管,所述第二导电类型为N型,所述口袋离子注入的注入杂质为N型杂质,所述轻掺杂漏注入的注入杂质为P型杂质,所述源漏注入的注入杂质为P型杂质。
图3中的,所述栅极结构由栅介质层2和多晶硅栅3叠加而成。
本发明实施例方法中,MOS晶体管为28nm以下工艺节点的HKMG类型器件,步骤一中的所述栅极结构为伪栅,所述伪栅在所述源区和所述漏区形成之后被去除,之后在所述伪栅的去除区域形成HKMG。
HKMG由高介电常数层组成栅介质层2和金属栅叠加而成。
所述高介电常数层的材料包括二氧化硅,氮化硅,三氧化二铝,五氧化二钽,氧化钇,硅酸铪氧化合物,二氧化铪,氧化镧,二氧化锆,钛酸锶,硅酸锆氧化合物。
所述金属栅的材料为Al。
在其他实施例方法中也能为:MOS晶体管为28nm以下工艺节点的LP类型器件即28LP类型器件,此时,所述栅介质层2为氮氧化硅层。
本发明实施例在轻掺杂漏站点工艺中对碳阻挡层的形成工艺做了特别的设定,主要是将碳阻挡层的碳离子注入分成了两次以上,各次碳离子注入的注入角度和注入深度不同,这样能够补偿单次碳离子注入所带来的不足,使得能同时是碳阻挡层的深度和各深度处的碳阻挡区6的第一侧向栅极结构内侧延伸的横向距离都得到调节,从而使得在各深度处都能实现碳阻挡区6的第一侧都位于口袋注入区7的第一侧的内侧,由于就能减少或防止口袋注入区7的第一侧向栅极结构所覆盖区域的第二导电类型阱1中扩散并进而减少或防止对沟道产生不利影响,从而能抑制沟道中的掺杂的随机波动,提高器件的稳定性。
由图3所示可知,区域6a和6b能保证对口袋注入区7的底部和顶部的内侧进行良好覆盖,使得口袋注入区7的杂质向沟道区域的扩散的量减少,从而能防止器件的阈值电压产生随机波动,提高器件的稳定性。
以上通过具体实施例对本发明进行了详细的说明,但这些并非构成对本发明的限制。在不脱离本发明原理的情况下,本领域的技术人员还可做出许多变形和改进,这些也应视为本发明的保护范围。
Claims (15)
1.一种MOS晶体管的制造方法,其特征在于,包括如下步骤:
步骤一、在半导体衬底表面形成有第二导电类型阱,在所述第二导电类型阱的表面形成栅极结构,被所述栅极结构所覆盖区域的所述第二导电类型阱表面用于形成沟道;
步骤二、进行轻掺杂漏站点工艺,包括如下分步骤:
步骤21、进行非结晶离子注入形成硅非晶化区;
步骤22、进行碳离子注入形成碳阻挡区,所述碳离子注入的次数至少包括两次,调节各次碳离子注入的注入角度和注入深度来调节所述碳阻挡区的深度以及各深度处的所述碳阻挡区的第一侧向所述栅极结构内侧延伸的横向距离,并保证后续形成的口袋注入区位于所述碳阻挡区的深度范围内且在各所述深度处所述碳阻挡区的第一侧都位于所述口袋注入区的第一侧的内侧,减少或防止所述口袋注入区的第一侧向所述栅极结构所覆盖区域的所述第二导电类型阱中扩散并进而减少或防止对沟道产生不利影响;
步骤23、进行口袋离子注入形成所述口袋注入区;
步骤24、进行轻掺杂漏注入形成轻掺杂漏区。
2.如权利要求1所述的MOS晶体管的制造方法,其特征在于:所述半导体衬底为硅衬底。
3.如权利要求2所述的MOS晶体管的制造方法,其特征在于:所述非结晶离子注入的注入杂质为硅或锗。
4.如权利要求1所述的MOS晶体管的制造方法,其特征在于:步骤22中所述碳离子注入的次数为两次,第一次碳离子注入的注入深度大于第二次碳离子注入的注入深度以及所述第一次碳离子注入的注入角度小于所述第二碳离子注入的注入角度。
5.如权利要求1所述的MOS晶体管的制造方法,其特征在于:所述轻掺杂漏区的深度大于所述硅非晶化区的深度,所述口袋注入区的深度大于所述轻掺杂漏区的深度。
6.如权利要求1所述的MOS晶体管的制造方法,其特征在于:所述非结晶离子注入、所述碳离子注入、所述口袋离子注入和所述轻掺杂漏注入都和所述栅极结构的侧面自对准。
7.如权利要求1所述的MOS晶体管的制造方法,其特征在于,还包括如下步骤:
步骤三、在所述栅极结构的侧面形成侧墙;
步骤四、以所述侧墙的侧面为自对准条件进行源漏注入在所述栅极结构的两侧形成源区和漏区。
8.如权利要求7所述的MOS晶体管的制造方法,其特征在于:MOS晶体管为NMOS管,所述第二导电类型为P型,所述口袋离子注入的注入杂质为P型杂质,所述轻掺杂漏注入的注入杂质为N型杂质,所述源漏注入的注入杂质为N型杂质。
9.如权利要求7所述的MOS晶体管的制造方法,其特征在于:MOS晶体管为PMOS管,所述第二导电类型为N型,所述口袋离子注入的注入杂质为N型杂质,所述轻掺杂漏注入的注入杂质为P型杂质,所述源漏注入的注入杂质为P型杂质。
10.如权利要求1所述的MOS晶体管的制造方法,其特征在于:所述栅极结构由栅介质层和多晶硅栅叠加而成。
11.如权利要求10所述的MOS晶体管的制造方法,其特征在于:MOS晶体管为28nm以下工艺节点的LP类型器件,所述栅介质层为氮氧化硅层。
12.如权利要求10所述的MOS晶体管的制造方法,其特征在于:MOS晶体管为28nm以下工艺节点的HKMG类型器件,步骤一中的所述栅极结构为伪栅,所述伪栅在所述源区和所述漏区形成之后被去除,之后在所述伪栅的去除区域形成HKMG。
13.如权利要求12所述的MOS晶体管的制造方法,其特征在于:HKMG由高介电常数层组成栅介质层和金属栅叠加而成。
14.如权利要求13所述的MOS晶体管的制造方法,其特征在于:所述高介电常数层的材料包括二氧化硅,氮化硅,三氧化二铝,五氧化二钽,氧化钇,硅酸铪氧化合物,二氧化铪,氧化镧,二氧化锆,钛酸锶,硅酸锆氧化合物。
15.如权利要求13所述的MOS晶体管的制造方法,其特征在于:所述金属栅的材料为Al。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811267610.2A CN109473357B (zh) | 2018-10-29 | 2018-10-29 | Mos晶体管的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811267610.2A CN109473357B (zh) | 2018-10-29 | 2018-10-29 | Mos晶体管的制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109473357A true CN109473357A (zh) | 2019-03-15 |
CN109473357B CN109473357B (zh) | 2022-05-27 |
Family
ID=65666303
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811267610.2A Active CN109473357B (zh) | 2018-10-29 | 2018-10-29 | Mos晶体管的制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN109473357B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111048510A (zh) * | 2019-12-25 | 2020-04-21 | 上海华力集成电路制造有限公司 | 一种FinFET源漏外延三层结构及其形成方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1469488A (zh) * | 2002-06-24 | 2004-01-21 | ��ʿͨ��ʽ���� | 半导体器件及其制备方法 |
CN1855540A (zh) * | 2005-04-25 | 2006-11-01 | 台湾积体电路制造股份有限公司 | 半导体元件及其制造方法 |
US20070284615A1 (en) * | 2006-06-09 | 2007-12-13 | Keh-Chiang Ku | Ultra-shallow and highly activated source/drain extension formation using phosphorus |
CN101312208A (zh) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Nmos晶体管及其形成方法 |
CN101459082A (zh) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管及其形成方法 |
CN102623341A (zh) * | 2011-01-28 | 2012-08-01 | 中芯国际集成电路制造(上海)有限公司 | 一种mos晶体管的制造方法 |
US20120319210A1 (en) * | 2011-06-17 | 2012-12-20 | Texas Instruments Incorporated | Method for 1/f noise reduction in nmos devices |
JP2012256668A (ja) * | 2011-06-08 | 2012-12-27 | Panasonic Corp | 半導体装置及びその製造方法 |
CN105702582A (zh) * | 2014-11-27 | 2016-06-22 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
-
2018
- 2018-10-29 CN CN201811267610.2A patent/CN109473357B/zh active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1469488A (zh) * | 2002-06-24 | 2004-01-21 | ��ʿͨ��ʽ���� | 半导体器件及其制备方法 |
CN1855540A (zh) * | 2005-04-25 | 2006-11-01 | 台湾积体电路制造股份有限公司 | 半导体元件及其制造方法 |
US20070284615A1 (en) * | 2006-06-09 | 2007-12-13 | Keh-Chiang Ku | Ultra-shallow and highly activated source/drain extension formation using phosphorus |
CN101312208A (zh) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Nmos晶体管及其形成方法 |
CN101459082A (zh) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管及其形成方法 |
CN102623341A (zh) * | 2011-01-28 | 2012-08-01 | 中芯国际集成电路制造(上海)有限公司 | 一种mos晶体管的制造方法 |
JP2012256668A (ja) * | 2011-06-08 | 2012-12-27 | Panasonic Corp | 半導体装置及びその製造方法 |
US20120319210A1 (en) * | 2011-06-17 | 2012-12-20 | Texas Instruments Incorporated | Method for 1/f noise reduction in nmos devices |
CN105702582A (zh) * | 2014-11-27 | 2016-06-22 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111048510A (zh) * | 2019-12-25 | 2020-04-21 | 上海华力集成电路制造有限公司 | 一种FinFET源漏外延三层结构及其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
CN109473357B (zh) | 2022-05-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5998848A (en) | Depleted poly-silicon edged MOSFET structure and method | |
CN103545213B (zh) | 半导体器件及其制造方法 | |
US5811338A (en) | Method of making an asymmetric transistor | |
KR20110126760A (ko) | L 형상 스페이서를 사용하는 비대칭 전계-효과 트랜지스터의 제조 및 구조 | |
CN103426769B (zh) | 半导体器件制造方法 | |
JPS5833870A (ja) | 半導体装置 | |
CN103545218B (zh) | 用于栅极边缘二极管泄漏电流减少的袋状反向掺杂 | |
US6498085B2 (en) | Semiconductor device and method of fabricating the same | |
US20060138567A1 (en) | Semiconductor device and fabricating method thereof | |
CN106206735A (zh) | Mosfet及其制造方法 | |
CN103985634A (zh) | 一种pmos晶体管的制造方法 | |
CN102420228B (zh) | 抑制gidl效应的后栅极工艺半导体器件及其制备方法 | |
CN101661889B (zh) | 一种部分耗尽的绝缘层上硅mos晶体管的制作方法 | |
CN109473357A (zh) | Mos晶体管的制造方法 | |
CN108565212A (zh) | 一种mos晶体管的制作方法及mos晶体管 | |
CN102637600A (zh) | Mos器件制备方法 | |
CN106158657A (zh) | Mos晶体管的形成方法 | |
CN106876450B (zh) | 低栅漏电容的纵向场效应晶体管及其制造方法 | |
CN101996885A (zh) | Mos晶体管及其制作方法 | |
CN109346440B (zh) | 半导体器件的制造方法和集成电路的制造方法 | |
CN108281485A (zh) | 半导体结构及其形成方法 | |
CN102299113A (zh) | 减小半导体器件热载流子注入损伤的制造方法 | |
CN102420143A (zh) | 一种改善后栅极工艺高k栅电介质nmos hci方法 | |
CN102420226B (zh) | 一种抑制漏极感应势垒降低效应的cmos器件及其制备方法 | |
CN105870021A (zh) | 金属氧化物半导体晶体管的制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |