CN109103170A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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Publication number
CN109103170A
CN109103170A CN201711240604.3A CN201711240604A CN109103170A CN 109103170 A CN109103170 A CN 109103170A CN 201711240604 A CN201711240604 A CN 201711240604A CN 109103170 A CN109103170 A CN 109103170A
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China
Prior art keywords
electronic building
building brick
interconnection structure
certain embodiments
equal
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CN201711240604.3A
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English (en)
Inventor
陈伟铭
俞笃豪
丁国强
侯上勇
吴集锡
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN109103170A publication Critical patent/CN109103170A/zh
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Abstract

本发明实施例涉及半导体元件及其制作方法。本发明实施例涉及一种半导体装置，其包括第一电子组件、第二电子组件及多个互连结构。所述第一电子组件具有第一表面。所述第二电子组件在所述第一电子组件上方，且所述第二电子组件具有面对所述第一电子组件的所述第一表面的第二表面。所述互连结构在所述第一电子组件与所述第二电子组件之间且电连接到所述第一电子组件及所述第二电子组件，其中所述互连结构中的每一者具有沿着大体上平行于所述第一表面及所述第二表面的第一方向的长度、沿着大体上平行于所述第一表面及所述第二表面且大体上垂直于所述第一方向的第二方向的宽度，且所述互连结构中的至少一者的所述长度大于所述宽度。

Description

半导体元件及其制作方法
技术领域
本发明实施例涉及半导体装置及其制作方法。
背景技术
集成式无源装置(IPD)为以集成电路的形式制造的无源装置，例如电容器及电感器。最近，所述IPD在SOC中被采用，且构建于封装结构中。关于IPD的集成的问题可包括(例如)IPD与有源装置之间的互连结构的电阻太高，且因此不利地影响封装结构的电性能。
发明内容
根据本发明的实施例，本发明实施例涉及一种半导体装置，其包含：第一电子组件，其具有第一表面；第二电子组件，其在所述第一电子组件上方，所述第二电子组件具有面对所述第一电子组件的所述第一表面的第二表面；以及多个互连结构，其在所述第一电子组件与所述第二电子组件之间且电连接到所述第一电子组件及所述第二电子组件，其中所述互连结构中的每一者具有沿着大体上平行于所述第一表面及所述第二表面的第一方向的长度、沿着大体上平行于所述第一表面及所述第二表面且大体上垂直于所述第一方向的第二方向的宽度，且所述互连结构中的至少一者的所述长度大于所述宽度。
根据本发明的又一实施例，本发明实施例涉及一种半导体装置，其包含：第一电子组件；第二电子组件，其在所述第一电子组件上方；第三电子组件，其在所述第一电子组件下方，其中所述第二电子组件在所述第一电子组件与所述第三电子组件之间；多个第一互连结构，其在所述第一电子组件与所述第二电子组件之间且电连接到所述第一电子组件及所述第二电子组件，其中所述第一互连结构中的每一者具有沿着大体上平行于所述第一电子组件的表面的第一方向的长度及沿着大体上平行于所述表面且大体上垂直于所述第一方向的第二方向的宽度，且所述第一互连结构中的至少一者的所述长度大于所述宽度；以及多个第二互连结构，其在所述第二电子组件与所述第三电子组件之间且电连接到所述第二电子组件及所述第三电子组件。
根据本发明的再一实施例，本发明实施例涉及一种用于制作半导体装置的方法，其包含：接收第一电子组件及第二电子组件；以及形成在所述第一电子组件与所述第二电子组件之间且电连接到所述第一电子组件及所述第二电子组件的多个第一互连结构，其中所述第一互连结构中的每一者具有沿着大体上平行于所述第一电子组件的表面的第一方向的长度、沿着大体上平行于所述表面且大体上垂直于所述第一方向的第二方向的宽度，且所述第一互连结构中的至少一者的所述长度大于所述宽度。
附图说明
依据在借助附图阅读时进行的以下详细说明最优选地理解本揭露的实施例的方面。应注意，根据业内标准实践，各种特征未按比例绘制。实际上，为论述清晰起见，可任意地增加或减小各种特征的尺寸。
图1为图解说明根据本揭露的一或多个实施例的各种方面的用于制作半导体装置的方法的流程图。
图2A、图2B、图2C、图2D、图2E、图2F及图2G为在根据本揭露的一或多个实施例的制作半导体装置的各种操作中的一者时的示意图。
图3为在根据本揭露的一或多个实施例的制作半导体装置的各种操作中的一者时的示意图。
图4为在根据本揭露的一或多个实施例的制作半导体装置的各种操作中的一者时的示意图。
图5为根据本揭露的某些实施例的半导体装置的示意图。
图6A、图6B及图6C为在根据本揭露的一或多个实施例的制作半导体装置的各种操作中的一者时的示意图。
图7A、图7B及图7C为在根据本揭露的一或多个实施例的制作半导体装置的各种操作中的一者时的示意图。
图8为根据本揭露的一或多个实施例的半导体装置的示意图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的诸多不同实施例或实例。下文阐述元件及布置的具体实例以简化本揭露。当然，此些元件及布置仅仅为实例且不打算为限制性的。举例来说，在以下说明中第一特征形成于第二特征上方或上可包括其中第一及第二特征形成为直接接触的实施例，且还可包括其中额外特征可形成于第一特征与第二特征之间使得第一及第二特征可不直接接触的实施例。另外，本揭露可在各种实例中重复元件符号及/或字母。此重复是出于简单及清晰目的且自身不指示所论述的各种实施例及/或配置之间的关系。
进一步地，可为便于说明而在本文中使用空间相对术语(例如，“下面”、“下方”、“下部”、“上面”、“上部”、“上”等等)来阐述一个元件或特征与另一(些)元件或特征的关系，如各图中所图解说明。空间相对术语打算囊括除各图中所绘示的定向以外的在使用或操作中的装置的不同定向。设备可以其它方式定向(旋转90度或处于其它定向)且因此可同样地解释本文中所使用的空间相对叙词。
如本文中所使用，例如“第一”、“第二”及“第三”的术语阐述各种元件、组件、区、层及/或区段，此些元件、组件、区、层及/或区段不应受此些术语限制。此些术语可仅用于将一个元件、组件、区、层或区段与另一元件、组件、区、层或区段区分开。例如“第一”、“第二”及“第三”的术语在用于本文中时不暗指顺序或次序，除非由上下文明确指示。
如本文中所使用，术语“大致”、“大体上”、“大体”及“大约”用于阐述及解释小变化。当结合事件或情况使用时，所述术语可指其中所述事件或情况精确地发生的实例以及其中所述事件或情况近似地发生的实例。举例来说，当结合数值使用时，所述术语可指小于或等于所述数值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或者小于或等于±0.05％)的变化范围。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或者小于或等于±0.05％)，那么所述值可被视为“大体上”相同或相等。举例来说，“大体上”平行可指相对于0°的角度变化范围，所述角度变化范围小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或者小于或等于±0.05°。举例来说，“大体上”垂直可指相对于90°的角度变化范围，所述角度变化范围小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或者小于或等于±0.05°。
还可包括其它特征及程序。举例来说，可包括测试结构以辅助对3D封装或3DIC装置的验证测试。所述测试结构可包括(例如)形成于重新分配层中或衬底上的测试垫，此允许测试3D封装或3DIC、使用探针及/或探针卡等等。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可结合并入已知良好裸片的中间验证的测试方法来使用以增加良率且降低成本。
在本揭露的一或多个实施例中，提供一种包括条形互连件的半导体装置。所述条形互连件具有大于宽度的长度。所述条形互连件经配置以电连接两个或更多个电子组件。条形互连件中的每一者电连接到多个电端子，且由于其经增加区域而具有经减少电阻。因此，条形互连件帮助改进半导体装置的电性能。在本揭露的某些实施例中，互连结构覆盖多个电端子，此帮助增加电子组件之间的对准容差，且因此可增加可靠性。
图1为图解说明根据本揭露的一或多个实施例的各种方面的用于制作半导体装置的方法的流程图。方法100以操作110开始，其中接收第一电子组件及第二电子组件。所述方法以操作120继续进行，其中形成在第一电子组件与第二电子组件之间且电连接到第一电子组件及第二电子组件的多个第一互连结构。第一互连结构中的每一者具有沿着大体上平行于第一表面及第二表面的第一方向的长度、沿着大体上平行于第一表面及第二表面且大体上垂直于第一方向的第二方向的宽度，且互连结构中的至少一者的长度大于宽度。
方法100仅仅为实例，且不打算将本揭露限制为超出权利要求书中明确陈述的内容。可在方法100之前、期间及之后提供额外操作，且可针对方法的额外实施例替换、消除或移动所阐述的某些操作。
图2A、图2B、图2C、图2D、图2E、图2F及图2G为在根据本揭露的一或多个实施例的制作半导体装置的各种操作中的一者时的示意图，其中图2A、图2C及图2G为在制作半导体装置的各种操作中的一者时的剖面图，图2B及图2D为在制作半导体装置的各种操作中的一者时的俯视图，且图2E及图2F为在制作半导体装置的各种操作中的一者时的斜视图。如图2A中所绘示，接收例如第一电子组件10的电子组件。第一电子组件10包括例如第一表面10S的表面。在某些实施例中，第一电子组件10可包括集成式无源装置、有源装置、中介层、封装结构、封装衬底、印刷电路板等等。在某些实施例中，第一电子组件10可包括呈集成电路的形式的一或多个集成式无源装置，例如电容器、电感器、电阻器或其组合。在某些实施例中，第一电子组件10可包括但不限于深沟渠电容器(DTC)。如图2B中所绘示，第一电子组件10可包括电连接到第一电子组件10内侧的集成电路且从第一表面10S暴露的电端子12。通过实例的方式，电端子12可包括但不限于接合垫等等。
如图2C、图2D及图2E中所绘示，在第一电子组件10的第一表面10S上方形成例如第一互连结构14的多个互连结构。在某些实施例中，第一互连结构14中的每一者具有沿着大体上平行于第一表面10S的第一方向D1的长度L、沿着大体上平行于第一表面10S且大体上垂直于第一方向D1的第二方向D2的宽度W，且第一互连结构14中的至少一者或所有的长度L大于宽度W。在某些实施例中，第一互连结构14中的每一者的长度L大于各别第一互连结构14的宽度W。在某些实施例中，第一互连结构14中的至少一者的长度L与宽度W的比率大于或等于2、大于或等于5或者大于或等于10。在某些实施例中，第一互连结构14中的每一者的长度L与宽度W的比率大于或等于2、大于或等于5或者大于或等于10。
在某些示范性实施例中，第一互连结构14中的至少一者或所有的长度L大于或等于100微米，例如介于从大约300微米到大约1毫米的范围内，但不限于此。在某些示范性实施例中，第一互连结构14的宽度W小于或等于50微米，但不限于此。在某些实施例中，第一互连结构14覆盖第一电子组件10的电端子12中的一者以上，使得第一互连结构14电连接到第一电子组件10的电端子12中的一者以上。在某些实施例中，第一互连结构14中的每一者电连接到布置成单个列的电端子12。在某些实施例中，第一互连结构14沿第二方向D2布置，且第一互连结构14中的每一者沿着第一方向D1延伸。
在某些实施例中，第一互连结构14包括彼此堆叠的一个以上导电层。在某些实施例中，第一互连结构14包括第一导电层141及堆叠于第一导电层141上的第二导电层142。在某些实施例中，第一导电层141可包括但不限于电连接到第一电子组件10的电端子12的凸块下金属(UBM)等等。在某些实施例中，第二导电层142可包括但不限于电连接到第一导电层141的导电凸块、导电球、导电膏等等。在某些实施例中，第一导电层141及第二导电层142的长度及宽度可为大体上相同的，所述长度及所述宽度可大体上等于第一互连结构14的长度L及宽度W。在某些实施例中，第二导电层142的厚度大于第一导电层141的厚度。在某些实施例中，第二导电层142的厚度与第一导电层141的厚度的比率大于或等于2，但不限于此。通过实例的方式，第二导电层142的厚度介于从大约15微米到大约50微米的范围内，例如大约25微米，但不限于此。通过实例的方式，第一导电层141的厚度介于从大约5微米到大约15微米的范围内，例如10微米，但不限于此。如图2F中所绘示，可对第二导电层142实施回流操作。
如图2G中所绘示，接收例如第二电子组件20的另一电子组件。第二电子组件20包括例如第二表面20S的表面。在某些实施例中，第二电子组件20可包括集成式无源装置、有源装置、中介层、封装结构、封装衬底、印刷电路板等等。在某些实施例中，第二电子组件20可包括例如逻辑装置等有源装置。在某些实施例中，第二电子组件20包括形成于第二表面20S上方的第三导电层143。在某些实施例中，第三导电层143的长度及宽度大体上等于第一导电层141及第二导电层142的长度及宽度。在某些实施例中，第三导电层143可包括但不限于电连接到第二电子组件20的凸块下金属(UBM)等等。在某些实施例中，第三导电层143的厚度介于从大约3微米到大约10微米的范围内，例如大约5微米，但不限于此。在第二表面20S面对第一表面10S的情况下定向第二电子组件20及第一电子组件10。第三导电层143然后耦合到各别第二导电层142及第一导电层141以形成由第一导电层141、第二导电层142及第三导电层143堆叠的多个第一互连结构14。因此，第二电子组件20及第一电子组件10通过第一互连结构14电连接，从而形成半导体装置1。
在本揭露的某些实施例中，第一互连结构14为条形互连件，且第一互连结构14中的每一者电连接到多个电端子12。条形互连件具有垂直于第一电子组件10与第二电子组件20之间的电流流动方向(即，第三方向D3)的经增加剖面区域，且因此第一电子组件10与第二电子组件20之间的互连件的电阻减小。因此，条形互连件帮助改进半导体装置1的电性能。在本揭露的某些实施例中，第一互连结构14覆盖多个电端子12，且因此帮助增加第一电子组件10与第二电子组件20之间的对准容差。
图3为在根据本揭露的一或多个实施例的制作半导体装置的各种操作中的一者时的示意图。与图2D相比较，第一互连结构14中的每一者电连接到布置成多个列及行的阵列的电端子12，如图3中所绘示。在某些实施例中，第一互连结构14覆盖更多电端子12，且因此帮助增加第一电子组件10与第二电子组件20之间的对准容差。
图4为在根据本揭露的一或多个实施例的制作半导体装置的各种操作中的一者时的示意图。与图2D相比较，第一互连结构14中的至少一者可包括经分段互连结构，例如第一经分段互连结构14X及第二经分段互连结构14Y。在某些实施例中，第一经分段互连结构14X具有沿着第一方向D1的长度L1，且第二经分段互连结构14Y具有沿着第一方向D1的长度L2。在某些实施例中，长度L1可不同于长度L2。在某些实施例中，第一经分段互连结构14X及第二经分段互连结构14Y可彼此断开电连接。
本揭露的半导体装置及其制作方法不限于上文所提及的实施例，且可具有其它不同实施例。为简化说明且为了便于本揭露的实施例中的每一者之间的比较，用相同编号标记以下实施例中的每一者中的相同组件。为了更易于比较实施例之间的差异，以下说明将详述不同实施例之间的相异性且将不冗余地阐述相同特征。
图5为根据本揭露的某些实施例的半导体装置的示意图。如图5中所绘示，与图2G的半导体装置1相比较，半导体装置2可包括衬底上晶片上芯片(CoWoS)封装结构，且半导体装置2的第二电子组件20可包括晶片上芯片(CoW)裸片。在某些实施例中，第二电子组件20包括中介层21、一或多个半导体裸片22、导体23、底填充层24及囊封剂25。在某些实施例中，中介层21可包括电连接到安置于中介层21上方的导体23及在中介层21下方的第一互连结构14的贯穿通孔，例如贯穿衬底通孔(TSV)等等。在某些实施例中，半导体裸片22安置于中介层21上方，且通过导体23电连接到中介层21。在某些实施例中，导体23可包括但不限于导电凸块、导电膏、导电球等等。在某些实施例中，底填充层24安置于半导体裸片22与中介层21之间且封围导体23。在某些实施例中，例如模制化合物的囊封剂25可囊封半导体裸片22的至少一部分。
半导体装置2的第一互连结构14的特征可类似于半导体装置1的互连结构14的特征，且在图2D、图2E及图2F中在某些示范性实例中得以展示，或在图3及图4中在某些替代示范性实例中得以展示。在某些实施例中，第一互连结构14中的至少一者的长度L大于各别第一互连结构14的宽度W。在某些实施例中，第一互连结构14中的至少一者的长度L与宽度W的比率大于或等于2、大于或等于5或者大于或等于10。在某些示范性实施例中，第一互连结构14的长度L大于或等于100微米，例如介于从大约300微米到大约1毫米的范围内，但不限于此。在某些示范性实施例中，第一互连结构14的宽度W小于或等于50微米，但不限于此。在某些实施例中，第一互连结构14覆盖第一电子组件10的电端子12中的一者以上，使得第一互连结构14电连接到第一电子组件10的电端子12中的一者以上。在某些实施例中，第一互连结构14中的每一者电连接到布置成单个列的电端子12，如图2D中所展示。在某些实施例中，第一互连结构14中的每一者电连接到布置成多个列及行的阵列的电端子12，如图3中所绘示。在某些实施例中，第一互连结构14中的至少一者可包括经分段互连结构，如图4中所绘示。
图6A、图6B及图6C为在根据本揭露的一或多个实施例的制作半导体装置的各种操作中的一者时的示意图。在某些实施例中，可继图2G之后实施制作图6A、图6B及图6C的半导体装置。如图6A中所绘示，可在第二电子组件20的表面20S上方形成多个第一导电结构26。在某些实施例中，可在连接第二电子组件20及第一电子组件10之前形成第一导电结构26。在某些实施例中，第一导电结构26可包括但不限于电连接到第二电子组件20的接合垫、UBM、导电凸块、导电球、导电膏等等或其组合。
如图6B中所绘示，接收第三电子组件30。第三电子组件30包括例如第三表面30S的表面。在某些实施例中，第三电子组件30可包括集成式无源装置、有源装置、中介层、封装结构、封装衬底、印刷电路板等等。在某些实施例中，第三电子组件30可包括但不限于封装衬底等等。在某些实施例中，第三电子组件30可进一步包括在表面30S上方的多个第二导电结构32。在某些实施例中，第二导电结构32可包括但不限于电连接到第三电子组件30的接合垫、UBM、导电凸块、导电球、导电膏等等或其组合。
如图6C中所绘示，在第二表面20S面对第三表面30S的情况下定向第二电子组件20及第三电子组件30。第一导电结构26然后耦合到各别第二导电结构32以形成多个第二互连结构34，且第二电子组件20及第三电子组件30通过第二互连结构34电连接以形成半导体装置3。在某些实施例中，第二互连结构34的高度H2大于第一互连结构14的高度H1，使得第一电子组件10与第三电子组件30分开。
半导体装置3的第一互连结构14的特征可类似于半导体装置1的第一互连结构14的特征，且在图2D、图2E及图2F(例如)中得以展示。在某些实施例中，第一互连结构14中的至少一者的长度L大于各别第一互连结构14的宽度W。在某些实施例中，第一互连结构14中的至少一者的长度L与宽度W的比率大于或等于2、大于或等于5或者大于或等于10。在某些示范性实施例中，第一互连结构14的长度L大于或等于100微米，例如介于从大约300微米到大约1毫米的范围内，但不限于此。在某些示范性实施例中，第一互连结构14的宽度W小于或等于50微米，但不限于此。在某些实施例中，第一互连结构14覆盖第一电子组件10的电端子12中的一者以上，使得第一互连结构14电连接到第一电子组件10的电端子12中的一者以上。在某些实施例中，第一互连结构14中的每一者电连接到布置成单个列的电端子12，如图2D中所展示。在某些实施例中，第一互连结构14中的每一者电连接到布置成多个列及行的阵列的电端子12，如图3中所绘示。在某些实施例中，第一互连结构14中的至少一者可包括经分段互连结构，如图4中所绘示。
图7A、图7B及图7C为在根据本揭露的一或多个实施例的制作半导体装置的各种操作中的一者时的示意图。在某些实施例中，可继图2G之后实施制作图7A、图7B及图7C的半导体装置。如图7A中所绘示，可在第二电子组件20的表面20S上方形成多个第二互连结构34。在某些实施例中，可在连接第二电子组件20及第一电子组件10之前形成第二互连结构34。在某些实施例中，第二互连结构34可包括但不限于电连接到第二电子组件20的接合垫、UBM、导电凸块、导电球、导电膏等等或其组合。在某些实施例中，第二互连结构34的高度H2可小于第一互连结构14的高度H1。
如图7B中所绘示，接收第三电子组件30。第三电子组件30包括例如第三表面30S的表面。在某些实施例中，第三电子组件30可包括但不限于封装衬底、印刷电路等等。在某些实施例中，第三电子组件30可进一步包括在表面30S上方的多个导电结构(未展示)，所述多个导电结构经配置以电连接第二电子组件20的第二互连结构34。在某些实施例中，半导体装置4的第三电子组件30可包括腔30C，腔30C从第三表面30S凹陷且经配置以容纳第一电子组件10，使得第一电子组件10可在耦合第二电子组件20及第三电子组件30之后不与第三电子组件30接触。
如图7C中所绘示，在第二表面20S面对第三表面30S的情况下定向第二电子组件20及第三电子组件30。第二互连结构34然后耦合到且电连接到第三电子组件30以形成半导体装置4。
半导体装置4的第一互连结构14的特征可类似于半导体装置1的第一互连结构14的特征，且在图2D、图2E及图2F(例如)中得以展示。在某些实施例中，第一互连结构14中的至少一者的长度L大于各别第一互连结构14的宽度W。在某些实施例中，第一互连结构14中的至少一者的长度L与宽度W的比率大于或等于2、大于或等于5或者大于或等于10。在某些示范性实施例中，第一互连结构14的长度L大于或等于100微米，例如介于从大约300微米到大约1毫米的范围内，但不限于此。在某些示范性实施例中，第一互连结构14的宽度W小于或等于50微米，但不限于此。在某些实施例中，第一互连结构14覆盖第一电子组件10的电端子12中的一者以上，使得第一互连结构14电连接到第一电子组件10的电端子12中的一者以上。在某些实施例中，第一互连结构14中的每一者电连接到布置成单个列的电端子12，如图2D中所展示。在某些实施例中，第一互连结构14中的每一者电连接到布置成多个列及行的阵列的电端子12，如图3中所绘示。在某些实施例中，第一互连结构14中的至少一者可包括经分段互连结构，如图4中所绘示。
图8为根据本揭露的一或多个实施例的半导体装置的示意图。如图8中所绘示，半导体装置5可包括第一组14A及第二组14B的第一互连结构14。在某些实施例中，第一组14A的第一互连结构14彼此电连接，且第二组14B的第一互连结构14彼此电连接。在某些实施例中，第一组14A及第二组14B的互连结构14沿第二方向D2交替地布置，但彼此断开电连接。在某些实施例中，第一电子组件10包括多个深沟渠电容器16，且多个深沟渠电容器16中的每一者包括彼此重叠的第一电极161及第二电极162。在某些实施例中，深沟渠电容器16的第一电极161通过第一组14A的第一互连结构14电连接到第二电子组件20，而深沟渠电容器16的第二电极162通过第二组14B的第一互连结构14电连接到第二电子组件20。
在本揭露的某些实施例中，条形互连件经配置以电连接两个或更多个电子组件。条形互连件中的每一者电连接到多个电端子，且由于其经增加区域而具有经减少电阻。因此，条形互连件帮助改进半导体装置的电性能。在本揭露的某些实施例中，互连结构覆盖多个电端子，此帮助增加电子组件之间的对准容差，且因此可增加可靠性。
在一个示范性方面中，一种半导体装置包括第一电子组件、第二电子组件及多个互连结构。所述第一电子组件具有第一表面。所述第二电子组件在所述第一电子组件上方，且所述第二电子组件具有面对所述第一电子组件的所述第一表面的第二表面。所述互连结构在所述第一电子组件与所述第二电子组件之间且电连接到所述第一电子组件及所述第二电子组件，其中所述互连结构中的每一者具有沿着大体上平行于所述第一表面及所述第二表面的第一方向的长度、沿着大体上平行于所述第一表面及所述第二表面且大体上垂直于所述第一方向的第二方向的宽度，且所述互连结构中的至少一者的所述长度大于所述宽度。
在另一方面中，一种半导体装置包括第一电子组件、第二电子组件、第三电子组件、多个第一互连结构及多个第二互连结构。所述第二电子组件在所述第一电子组件上方。所述第三电子组件在所述第一电子组件下方，其中所述第二电子组件在所述第一电子组件与所述第三电子组件之间。所述第一互连结构在所述第一电子组件与所述第二电子组件之间且电连接到所述第一电子组件及所述第二电子组件，其中所述第一互连结构中的每一者具有沿着大体上平行于所述第一电子组件的表面的第一方向的长度及沿着大体上平行于所述表面且大体上垂直于所述第一方向的第二方向的宽度，且所述第一互连结构中的至少一者的所述长度大于所述宽度。所述第二互连结构在所述第二电子组件与所述第三电子组件之间且电连接到所述第二电子组件及所述第三电子组件。
在又一方面中，一种用于制作半导体装置的方法包括：接收第一电子组件及第二电子组件；以及形成在所述第一电子组件与所述第二电子组件之间且电连接到所述第一电子组件及所述第二电子组件的多个第一互连结构，其中所述第一互连结构中的每一者具有沿着大体上平行于所述第一电子组件的表面的第一方向的长度、沿着大体上平行于所述表面且大体上垂直于所述第一方向的第二方向的宽度，且所述第一互连结构中的至少一者的所述长度大于所述宽度。
前文概述数个实施例的结构使得所属领域的技术人员可更好地理解本揭露的方面。所属领域的技术人员应了解，其可容易地使用本揭露作为设计或修改其它程序及结构以用于实施相同目的及/或实现本文中介绍的实施例的相同优点的基础。所属领域的技术人员还应认识到，此些等效构造不背离本揭露的精神及范围，且其可在不背离本揭露的精神及范围的情况下在本文中做出各种改变、替代及变更。
符号说明
1 半导体装置
2 半导体装置
3 半导体装置
4 半导体装置
10 第一电子组件
10S 第一表面
12 电端子
14 第一互连结构
14A 第一组
14B 第二组
14X 第一经分段互连结构
14Y 第二经分段互连结构
16 深沟渠电容器
20 第二电子组件
20S 第二表面
21 中介层
22 半导体裸片
23 导体
24 底填充层
25 囊封剂
26 第一导电结构
30 第三电子组件
30C 腔
30S 第三表面
32 第二导电结构
34 第二互连结构
141 第一导电层
142 第二导电层
143 第三导电层
161 第一电极
162 第二电极
D1 第一方向
D2 第二方向
D3 第三方向
H1 高度
H2 高度
L 长度
L1 长度
L2 长度
W 宽度

Claims (1)

1.一种半导体装置，其包含：
第一电子组件，其具有第一表面；
第二电子组件，其在所述第一电子组件上方，所述第二电子组件具有面对所述第一电子组件的所述第一表面的第二表面；以及
多个互连结构，其在所述第一电子组件与所述第二电子组件之间且电连接到所述第一电子组件及所述第二电子组件，其中所述互连结构中的每一者具有沿着大体上平行于所述第一表面及所述第二表面的第一方向的长度、沿着大体上平行于所述第一表面及所述第二表面且大体上垂直于所述第一方向的第二方向的宽度，且所述互连结构中的至少一者的所述长度大于所述宽度。
CN201711240604.3A 2017-06-20 2017-11-30 半导体元件及其制作方法 Pending CN109103170A (zh)

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