CN108573936B - 半导体封装 - Google Patents
半导体封装 Download PDFInfo
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- CN108573936B CN108573936B CN201810171315.0A CN201810171315A CN108573936B CN 108573936 B CN108573936 B CN 108573936B CN 201810171315 A CN201810171315 A CN 201810171315A CN 108573936 B CN108573936 B CN 108573936B
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Abstract
本发明公开一种半导体封装,包括:封装基板,具有上表面和底表面;中间体,安装在所述封装基板的上表面上;第一半导体晶粒和第二半导体晶粒,以并排的方式安装在所述中间体上;以及加强环,安装在所述封装基板的上表面,其中所述加强环围绕所述第一半导体晶粒和第二半导体晶粒,所述加强环包括横跨所述中间体的加强筋。采用这种方式,使用加强环和加强筋对半导体晶粒进行加固,减少对半导体晶粒的覆盖和封闭,半导体晶粒产生的热量不会被其他阻挡物阻挡而影响半导体封装的散热,从而提高半导体封装的散热速度和散热能力。
Description
技术领域
本发明涉及半导体技术领域,尤其涉及一种半导体封装。
背景技术
在集成电路(IC,integrated circuit)的运行期间,IC芯片产生热量,从而加热了包含芯片的整个电子器件封装。由于IC芯片的性能随着温度升高而降低,并且由于高热应力(thermal stresse)降低了电子器件封装的结构完整性(structural integrity),所以这种热量必须散出。
通常,电子器件封装使用金属盖(lid)来散热。来自芯片的热量通过芯片/盖子接口传递到金属盖。然后通过对流将热量从金属盖传递到周围的空气,或者传递到安装在金属盖上的散热器。
随着每个新一代微处理器的晶粒功耗、晶粒尺寸和热密度的增加,散热成为一个挑战。
发明内容
有鉴于此,本发明提供一种半导体封装,以提高半导体封装的散热速度和散热能力。
根据本发明的第一方面,公开一种半导体封装,包括:
封装基板,具有上表面和底表面;
中间体,安装在所述封装基板的上表面上;
第一半导体晶粒和第二半导体晶粒,以并排的方式安装在所述中间体上;以及
加强环,安装在所述封装基板的上表面,其中所述加强环围绕所述第一半导体晶粒和第二半导体晶粒,所述加强环包括横跨所述中间体的加强筋。
根据本发明的第二个方面,公开一种半导体封装,包括:
封装基板,具有上表面和底表面;
中间体,安装在所述封装基板的上表面上;
第一半导体晶粒和第二半导体晶粒,以并排的方式安装在所述中间体上;
模塑料,封装所述第一半导体晶粒和所述第二半导体晶粒;以及
加强环,固定到所述封装基板的上表面,其中所述加强环包括横跨所述模塑料的加强筋。
根据本发明的第三个方面,公开一种半导体封装,包括:
封装基板,具有上表面和底表面;
中间体,安装在所述封装基板的上表面上;
第一半导体晶粒,安装在所述中间体上;
加强环,固定到所述封装基板的上表面,其中加强环围绕所述第一半导体晶粒;以及
散热器,直接接合到所述第一半导体晶粒的背面表面。
根据本发明的第四个方面,公开一种半导体封装,包括:
封装基板,具有上表面和底表面;
重分布层结构,安装在所述封装基板的上表面上;
第一半导体晶粒和第二半导体晶粒,以并排的方式安装在所述重分布层结构上;
模塑料,封装所述第一半导体晶粒和所述第二半导体晶粒;以及
加强环,固定到所述封装基板的上表面,其中所述加强环包括横跨所述模塑料的加强筋。
本发明提供的半导体封装由于包括加强环,第一半导体晶粒和第二半导体晶粒安装在中间体上,并且加强环围绕第一半导体晶粒和第二半导体晶粒,加强环包括横跨中间体的加强筋。采用这种方式,使用加强环和加强筋对半导体晶粒进行加固,减少对半导体晶粒的覆盖和封闭,半导体晶粒产生的热量不会被其他阻挡物阻挡而影响半导体封装的散热,从而提高半导体封装的散热速度和散热能力。
在阅读了随后以不同附图展示的优选实施例的详细说明之后,本发明的这些和其它目标对本领域普通技术人员来说无疑将变得明显。
附图说明
图1是根据本发明一个实施例的半导体封装的俯视示意图;
图2是沿着图1中的虚线I-I'截取的横截面示意图;
图3是沿着图2中的虚线II-II'截取的横截面示意图;
图4是根据本发明另一个实施例的半导体封装的俯视示意图;
图5是沿着图4中的虚线I-I'截取的横截面示意图;
图6是沿着图4中的虚线II-II'截取的横截面示意图;
图7是根据本发明另一个实施例的半导体封装的俯视示意图;
图8是沿着图7中的虚线I-I'截取的横截面示意图;
图9是根据本发明另一个实施例的半导体封装的俯视示意图;
图10是沿着图9中的虚线I-I'截取的横截面示意图;
图11是根据本发明另一个实施例的半导体封装的俯视示意图;
图12是沿着图11中的虚线I-I'截取的横截面示意图;
图13是沿着图11中的虚线II-II'截取的横截面示意图;
图14是根据本发明另一个实施例的半导体封装的俯视示意图;
图15是沿着图14中的虚线I-I'的截取的横截面示意图;
图16是根据本发明另一个实施例的半导体封装的俯视示意图;
图17是沿着图16中的虚线I-I'的截取的横截面示意图;
图18是根据本发明又一个实施例的半导体封装的俯视示意图,其中加强筋沿着水平方向延伸;
图19是根据本发明又一实施例的半导体封装的俯视示意图,其中加强筋与周围的加强环形成八边形结构;
图20是根据本发明另一实施例的半导体封装的俯视示意图,其中加强筋沿水平方向延伸。
图21是根据本发明又一实施例的半导体封装的俯视示意图;
图22是沿着图21中的虚线I-I'截取的横截面示意图。
具体实施方式
在说明书和随后的权利要求书中始终使用特定术语来指代特定组件。正如本领域技术人员所认识到的,制造商可以用不同的名称指代组件。本文件无意于区分那些名称不同但功能相同的组件。在以下的说明书和权利要求中,术语“包含”和“包括”被用于开放式类型,因此应当被解释为意味着“包含,但不限于...”。此外,术语“耦合”旨在表示间接或直接的电连接。因此,如果一个设备耦合到另一设备,则该连接可以是直接电连接,或者经由其它设备和连接的间接电连接。
以下描述是实施本发明的最佳设想方式。这一描述是为了说明本发明的一般原理而不是用来限制的本发明。本发明的范围通过所附权利要求书来确定。
下面将参考特定实施例并且参考某些附图来描述本发明,但是本发明不限于此,并且仅由权利要求限制。所描述的附图仅是示意性的而并非限制性的。在附图中,为了说明的目的,一些元件的尺寸可能被夸大,而不是按比例绘制。在本发明的实践中,尺寸和相对尺寸不对应于实际尺寸。
请参阅图1至图3。图1是根据本发明一个实施例的半导体封装的俯视示意图。图2是沿着图1中的虚线I-I'截取的横截面示意图。图3是沿着图1中的虚线II-II'截取的横截面示意图。
如图1至图3所示,提供一种半导体封装1a。半导体封装1a可以是2.5D半导体封装。半导体封装1a包括具有上表面10a和底表面10b的封装基板10。中间体(interposer)20安装在封装基板10的上表面10a上。根据一个实施例,中间体20可以包括硅中间体或RDL(Redistribution Layer,重分布层)中间体,但是不限于这两种方式。
在底表面10b上,可以提供多个连接元件102。例如,多个连接元件102可以是焊球(solder ball)。通过多个连接元件102,半导体封装件1a可以安装到印刷电路板(printedcircuit board)或系统板(system board),但是不限于这两种方式。
第一半导体晶粒(die)31和第二半导体晶粒32以并排(side-by-side)的方式安装在中间体20的上表面20a上。第一半导体晶粒31和第二半导体晶粒32可以是倒装芯片(flipchip),第一半导体晶粒31和第二半导体晶粒32的有源表面(active surface)31a和32a朝向下方的中间体20。第一半导体晶粒31和第二半导体晶粒32可以分别通过在有源表面31a上的凸块310和在有源表面32a上的凸块320连接到中间体20。中间体20提供第一半导体晶粒31和第二半导体晶粒32与封装基板10之间的电连接,并且可能提供第一半导体晶粒31与第二半导体晶粒32之间的电连接。
根据一个实施例,第一半导体晶粒31可以包括专用集成芯片(ASIC,application-specific integrated chip)或微处理器(micro-processor),但是不限于这两种方式。第二半导体晶粒32可以包括由多个具有硅通孔(TSV,through silicon via)的存储器芯片(memory chip)堆叠的高带宽存储器(HBM,high bandwidth memory)芯片。
可以理解的是,第一半导体晶粒31和第二半导体晶粒32可以都是ASIC或都是系统级芯片(SoC,System-on-Chip)芯片。根据另一个实施例,第一半导体晶粒31和第二半导体晶粒32可以包括SoC芯片和DRAM(Dynamic Random Access Memory,动态随机存取存储器)芯片。根据另一个实施例,第一半导体晶粒31和第二半导体晶粒32可以包括ASIC芯片和HBM芯片。
应该理解的是,附图中的半导体晶粒的数量仅为了示例性说明。半导体晶粒的数量不限于两个,可以超过两个。
在中间体20的底表面20b上,提供了多个连接元件202。通过连接元件202,中间体20电连接到封装基板10。第一半导体晶粒31和第二半导体晶粒32通过中间体20电连接到封装基板10。在一些实施例中,第一半导体晶粒31和第二半导体晶粒32可以通过中间体20彼此电连接。
根据一个实施例,加强环(stiffener ring)40固定(secure)到封装基板10的上表面10a。加强环40可以沿封装基板10的一周设置,以形成例如矩形形状。加强环40环绕第一半导体晶粒31和第二半导体晶粒32。这样设置可以提高半导体封装的机械强度,保护半导体封装内的半导体晶粒等部件。
根据一个实施例,加强环40可以通过使用黏合层(adhesive layer)固定到封装基板10的上表面10a,但固定方式不限于此。加强环40可以由铜构成,但材质不限于此。采用金属材质例如铜的加强环可以帮助半导体晶粒散热,提高半导体封装的散热能力。
根据一个实施例,加强环40包括横跨(striding across)中间体20的加强筋(reinforcement rib)401。根据一个实施例,如图3所示,加强筋401通过下沉(downset)部分401b一体地连接到加强环40。如图2所示,加强筋401延伸穿过第一半导体晶粒31和第二半导体晶粒32之间的空间。加强筋401与中间体20的上表面20a直接接触。
根据一个实施例,无需使用模塑料(molding compound)来覆盖中间体20、第一半导体晶粒31和第二半导体晶粒32。采用这种方式,半导体晶粒产生的热量不会被模塑料等物体阻挡而影响半导体封装的散热,从而提高半导体封装的散热速度和散热能力。如图1所示,从本实施例的俯视图可知,加强筋401位于第一半导体晶粒31与第二半导体晶粒32之间。如图2所示,加强筋401与第一半导体晶粒31和第二半导体晶粒32共面。这样可以保证半导体封装的结构稳定性,提高半导体封装的机械强度。
根据一个实施例,如图2和图3所示,半导体封装1a可以进一步包括散热器(heatsink)50。散热器50可以通过热界面材料(TIM,thermal interface material)层510直接接合(bond)到第一半导体晶粒31的背面表面(rear surface)31b、第二半导体晶粒32的背面表面32b、和/或加强筋401的上表面401a。其中,热界面材料层可以是在膏状物中掺杂金属(例如铜、铝或其他金属合金等)材料形成的导热层。为了清楚起见,图1中未示出散热器50。
散热器50也可以接合到第一半导体晶粒31和第二半导体晶粒32之间的加强筋401,这有助于散热。根据另一个实施例,第一半导体晶粒31和/或第二半导体晶粒32可以与加强筋401热接触(thermal contact with),从而帮助半导体晶粒散热。散热器通过热界面材料层直接与半导体晶粒接触,散热器可以帮助更快的将半导体晶粒产生的热量散出。而且当加强筋与散热器接触时,可以进一步扩大散热通道,加速散热。
图4、图5和图6示出了本发明的另一个实施例,其中相同的数字表示相同的区域、层或元件。
图4是根据本发明另一实施例的半导体封装的俯视示意图。图5是沿着图4中的虚线I-I'截取的横截面示意图。图6是沿着图4中的虚线II-II'截取的横截面示意图。
如图4至图6所示,提供一种半导体封装1b。半导体封装1b可以是2.5D半导体封装。半导体封装1b包括具有上表面10a和底表面10b的封装基板10。中间体20安装在封装基板10的上表面10a上。根据一个实施例,中间体20可以包括硅中间体或RDL中间体,但是不限于这两种方式。
在底表面10b上,可以设置多个连接元件102。例如,多个连接元件102可以是焊球。通过多个连接元件102,半导体封装1b可以安装到印刷电路板或系统板,但是不限于这两种方式。
类似地,第一半导体晶粒31和第二半导体晶粒32以并排的方式安装在中间体20的上表面20a上。第一半导体晶粒31和第二半导体晶粒32可以是倒装芯片,第一半导体晶粒31和第二半导体晶粒32的有源表面31a和32a朝向下方的中间体20。第一半导体晶粒31和第二半导体晶粒32可以分别通过在有源表面31a上的凸块310和在有源表面32a上的凸块320连接到中间体20。
根据一个实施例,第一半导体晶粒31可以包括专用集成芯片(ASIC)或微处理器,但是不限于这两种方式。第二半导体晶粒32可以包括由多个具有硅通孔(TSV)的存储器芯片堆叠的高带宽存储器(HBM)芯片。根据一个实施例,第一半导体晶粒31设置为紧邻第二半导体晶粒32。例如典型地,第一半导体晶粒31和第二半导体晶粒32之间的间隙可以小于100微米。
在中间体20的底表面20b上设有多个连接元件202。通过连接元件202,中间体20电连接到封装基板10。第一半导体晶粒31和第二半导体晶粒32均通过中间体20电连接到封装基板10。在一些实施例中,第一半导体晶粒31和第二半导体晶粒32可以通过中间体20彼此电连接。
根据一个实施例,加强环40固定到封装基板10的上表面10a。加强环40可以沿着封装基板10的一周设置,以形成例如矩形形状。加强环40环绕第一半导体晶粒31和第二半导体晶粒32。
根据一个实施例,加强环40可以通过使用黏合层固定到封装基板10的上表面10a,但固定方式不限于此。加强环40可以由铜构成,但材质不限于此。
根据一个实施例,加强环40包括横跨中间体20的两个加强筋401。两个加强筋401绕开(circumvent)第一半导体晶粒31和第二半导体晶粒32。根据一个实施例,如图4和图6所示,加强筋401通过下沉部分401b一体地连接到加强环40。加强筋401沿中间体20的两个相对侧边缘延伸。加强筋401与中间体20的上表面20a直接接触。根据一个实施例,无需使用模塑料来覆盖中间体20、第一半导体晶粒31和第二半导体晶粒32。每个加强筋401均不与第一半导体晶粒31或第二半导体晶粒32重叠。采用这种方式,半导体晶粒产生的热量不会被模塑料或加强筋等物体阻挡而影响半导体封装的散热,从而提高半导体封装的散热速度和散热能力。
根据一个实施例,如图5和图6中可以看到,半导体封装1b可以进一步包括散热器50。散热器50可以通过热界面材料(TIM)层510直接接合到第一半导体晶粒31的背面表面31b和第二半导体晶粒32的背面表面32b。为了清楚起见,图4中未示出散热器50。
散热器50也可以接合到位于第一半导体晶粒31和第二半导体晶粒32外侧的加强筋401,这有助于散热。散热器50可以直接接合到加强筋401,例如通过TIM层接合到加强筋401,这样可以通过加强筋导热,有助于散热;或者散热器50与加强筋401之间设有间隙,这样可以便于热量从间隙散出。根据另一个实施例,第一半导体晶粒31和/或第二半导体晶粒32可以与加强筋401热接触,从而帮助半导体晶粒散热。
可以理解,两个加强筋401可以沿着与如图4所示的竖直方向不同的方向延伸。例如,如图18所示,两个加强筋401可以沿着第一半导体晶粒31和第二半导体晶粒32中的每一个的相对两侧的水平方向延伸。使用两个加强筋将进一步提高中间体安装的稳定性,提高半导体封装的结构稳定性。
图7和图8示出了本发明的另一个实施例,其中相同的数字表示相同的区域、层或元件。图7是根据本发明另一实施例的半导体封装的俯视示意图。图8是沿着图7中的虚线I-I'截取的横截面示意图。
如图7和图8所示,提供一种半导体封装1c。半导体封装1c可以是2.5D半导体封装。半导体封装1c包括具有上表面10a和底表面10b的封装基板10。中间体20安装在封装基板10的上表面10a上。根据一个实施例,中间体20可以包括硅中间体或RDL中间体,但是不限于这两种方式。
根据一个实施例,加强环40包括横跨中间体20的三个加强筋401。根据一个实施例,如图7中可见,加强筋401通过下沉部分401b一体地连接到加强环40。三个加强筋401中的两个沿中间体20的两个相对侧边缘延伸。三个加强筋401中的一个延伸穿过第一半导体晶粒31和第二半导体晶粒32之间的空间。加强筋401直接与中间体20的上表面20a接触。根据一个实施例,无需使用模塑料来覆盖中间体20、第一半导体晶粒31和第二半导体晶粒32。因此半导体晶粒产生的热量不会被模塑料或加强筋等物体阻挡而影响半导体封装的散热,从而提高半导体封装的散热速度和散热能力。
根据一个实施例,如图8中可见,半导体封装1c可以进一步包括散热器50。散热器50可以通过热界面材料(TIM)层510直接接合到第一半导体晶粒31的背面表面31b和第二半导体晶粒32的背面表面32b。为了清楚起见,图1中未示出散热器50。散热器通过热界面材料层直接与半导体晶粒接触,散热器可以帮助更快的将半导体晶粒产生的热量散出。散热器50可以直接接合到加强筋401,例如通过TIM层接合到加强筋401,这样可以通过加强筋导热,有助于散热。
在图9和图10示出了本发明的另一个实施例,其中相同的附图标记表示相同的区域、层或元件。图9是根据本发明另一实施例的半导体封装的俯视示意图。图10是沿着图9中的虚线I-I'截取的横截面示意图。
如图9和图10所示,提供一种半导体封装1d。半导体封装1d可以是2.5D半导体封装。半导体封装1d包括具有上表面10a和底表面10b的封装基板10。中间体20安装在封装基板10的上表面10a上。根据一个实施例,中间体20可以包括硅中间体或RDL中间体,但是不限于这两种方式。
根据一个实施例,加强环40包括横跨中间体20的多个加强筋401。多个加强筋401可以成形为包围第一半导体晶粒31和第二半导体晶粒32的框架(frame)。根据一个实施例,如在图9中可见的,加强筋401通过下沉部分401b一体地连接到加强环40。加强筋401与中间体20的上表面20a直接接触。采用这种方式将会加强对中间体的固定,并且加强筋环绕第一半导体晶粒和第二半导体晶粒,将会提高半导体晶粒的安装稳定性,提高半导体封装的机械强度,保护半导体晶粒。
根据一个实施例,无需使用模塑料来覆盖中间体20、第一半导体晶粒31和第二半导体晶粒32。因此半导体晶粒产生的热量不会被模塑料等物体阻挡而影响半导体封装的散热,从而提高半导体封装的散热速度和散热能力。
根据一个实施例,如图10中可见,半导体封装1d可以进一步包括散热器50。散热器50可以通过热界面材料(TIM)层510直接接合到第一半导体晶粒31的背面表面31b、第二半导体晶粒32的背面表面32b。为了清楚起见,图1中未示出散热器50。
图11,图12和图13示出了本发明的另一个实施例,其中相同的附图标记表示相同的区域、层或元件。图11是根据本发明另一实施例的半导体封装的俯视示意图。图12是沿着图11中的虚线I-I'截取的横截面示意图。图13是沿着图11中的虚线II-II'截取的横截面示意图。
如图11至图13所示,提供了一种半导体封装1f。半导体封装1f可以是2.5D半导体封装。半导体封装1f包括具有上表面10a和底表面10b的封装基板10。中间体20安装在封装基板10的上表面10a上。根据一个实施例,中间体20可以包括硅中间体或RDL中间体,但是不限于这两种方式。
在底表面10b上,可以提供多个连接元件102。例如,多个连接元件102可以是焊球。通过多个连接元件102,半导体封装件1f可以安装到印刷电路板或系统板,但是不限于这两种方式。
类似地,第一半导体晶粒31和第二半导体晶粒32以并排的方式安装在中间体20的上表面20a上。第一半导体晶粒31和第二半导体晶粒32可以是倒装芯片,第一半导体晶粒31和第二半导体晶粒32的有源表面31a和32a朝向下方的中间体20。第一半导体晶粒31和第二半导体晶粒32可以分别通过在有源表面31a上的凸块310和在有源表面32a上的凸块320连接到中间体20。
根据一个实施例,第一半导体晶粒31可以包括专用集成芯片(ASIC)或微处理器,但是不限于这两种方式。第二半导体晶粒32可以包括由多个具有硅通孔(TSV)的存储器芯片堆叠的高带宽存储器(HBM)芯片。
可以理解的是,第一半导体晶粒31和第二半导体晶粒32可以都是ASIC或者都是系统级芯片(SoC)芯片。根据另一个实施例,第一半导体晶粒31和第二半导体晶粒32可以包括SoC芯片和DRAM芯片。根据另一个实施例,第一半导体晶粒31和第二半导体晶粒32可以包括ASIC和HBM芯片。尽管在附图中仅示出了两个半导体晶粒,但是应该理解,在其他实施例中,半导体封装可以包括多于两个半导体晶粒。
在中间体20的底面20b上设有多个连接元件202。通过连接元件202,中间体20电连接到封装基板10。第一半导体晶粒31和第二半导体晶粒32通过中间体20电连接到封装基板10。在一些实施例中,第一半导体晶粒31和第二半导体晶粒32可以通过中间体20彼此电连接。
根据一个实施例,提供模塑料60以封装(encapsulate)第一半导体晶粒31和第二半导体晶粒32。第一半导体晶粒31的背面表面31b和第二半导体晶粒32的背面表面32b没有被模塑料60覆盖。采用这种方式,不仅可以让模塑料保护和固定半导体晶粒,并且还可以避免因模塑料覆盖背面表面而不利于散热,从而同时兼顾了半导体晶粒稳固性和散热。
根据一个实施例,加强环40固定到封装基板10的上表面10a。加强环40可以沿着封装基板10的一周设置,以形成矩形形状,例如。加强环40环绕第一半导体晶粒31和第二半导体晶粒32。
根据一个实施例,加强环40可以通过使用黏合层固定到封装基板10的上表面10a,但固定方式不限于此。加强环40可以由铜构成,但材质不限于此。
根据一个实施例,加强环40包括横跨模塑料60的两个加强筋401。根据一个实施例,如图11和图13所示,加强筋401通过下沉部分401b一体地连接到加强环40。加强筋401沿中间体20的两个相对侧边缘延伸。加强筋401与模塑料60的上表面20a直接接触。
根据一个实施例,半导体封装1f可以进一步包括散热器50。散热器50可以通过热界面材料(TIM)层510直接接合到第一半导体晶粒31的背面表面31b、第二半导体晶粒32的背面表面32b和加强筋401的上表面401a。如图11所示,加强筋401可以与第一半导体晶粒31或第二半导体晶粒32的背面表面部分重叠。具体的,其中的一个加强筋401与第一半导体晶粒31的背面表面31b部分地重叠;另一个加强筋401与第二半导体晶粒32的背面表面32b部分地重叠。这样可以加强对半导体晶粒和模塑料的固定,保证半导体晶粒和模塑料的稳固性。为了清楚起见,图11中未示出散热器50。根据一个实施例,加强筋401可以与第一半导体晶粒31或第二半导体晶粒32的背面表面直接接触。
根据一个实施例,当从上方观察时,加强筋401可以是跨过模塑料60的直线形状的筋条(rib)。直线形状的加强筋方便生产制造。然而,可以理解的是,加强筋401可以具有其他形状。例如,如图19所示,加强筋401为弯曲的以与周围的加强环40形成八边形(octagonal)结构。这种八边形结构可以为半导体封装提供更好的结构刚度(structuralrigidity)。当然加强筋401也可以与周围的加强环40形成五边形或六边形等。
图14和图15示出了本发明的另一个实施例,其中相同的数字表示相同的区域、层或元件。图14是根据本发明另一实施例的半导体封装的俯视示意图。图15是沿着图14中的虚线I-I'截取的横截面示意图。
如图14和图15所示,提供一种半导体封装1g。半导体封装1g可以是2.5D半导体封装。半导体封装1g包括具有上表面10a和底表面10b的封装基板10。中间体20安装在封装基板10的上表面10a上。根据一个实施例,中间体20可以包括硅中间体或RDL中间体,但是不限于这两种方式。
根据一个实施例,提供模塑料60以封装第一半导体晶粒31和第二半导体晶粒32。第一半导体晶粒31的背面表面31b和第二半导体晶粒32的背面表面32b是没有被模塑料60覆盖。
根据一个实施例,加强环40包括横跨模塑料60的两个加强筋401’和401”。根据一个实施例,如图14所示,加强筋401’和401”通过下沉部分401b一体地连接到加强环40。可以采用不对称的(asymmetric)加强筋结构。例如,加强筋401’具有比加强筋401”更大的宽度(或表面积)。
根据一个实施例,例如,加强筋401’可以与第一半导体晶粒31的背面表面31b完全重叠。例如,当从上方观察时,加强筋401”可以沿着中间体20的侧边缘延伸,并可以不与第二半导体晶粒32重叠。采用这种方式可以使用宽度(或表面积)较大的加强筋固定需要加强固定的半导体晶粒,从而保证半导体晶粒的稳固。同时,当加强筋采用金属材料如铜时,加强筋也可以帮助导热,从而减小对半导体晶粒散热的不利影响。
图16和图17示出了本发明的另一个实施例,其中相同的数字表示相同的区域、层或元件。图16是根据本发明另一实施例的半导体封装的俯视示意图。图17是沿着图16中的虚线I-I'截取的横截面示意图。
如图16和图17所示,提供一种半导体封装1h。半导体封装1h可以是2.5D半导体封装。半导体封装1h包括具有上表面10a和底表面10b的封装基板10。中间体20安装在封装基板10的上表面10a上。根据一个实施例,中间体20可以包括硅中间体或RDL中间体,但是不限于这两种方式。
根据一个实施例,提供模塑料60以封装第一半导体晶粒31和第二半导体晶粒32。第一半导体晶粒31的背面表面31b和第二半导体晶粒32的背面表面32b没有被模塑料60覆盖。
根据一个实施例,加强环40包括横跨中间体20的两个加强筋401。根据一个实施例,如图16所示,加强筋401通过下倾部分401b一体地连接到加强环40。如图17所示,加强筋401与中间体20的上表面20a和模塑料60的外围侧壁直接接触。采用这种设置可以通过加强筋将半导体晶粒和模塑料包围,从而进一步保护半导体晶粒,加强筋与中间体直接接触可保证中间体的稳固,提高封装的结构稳定性。加强筋401、第一半导体晶粒31和第二半导体晶粒32可以通过热界面材料(TIM)层510与散热器50热接触。
可以理解,两个加强筋401可以沿着与如图16所示的竖直方向不同的方向延伸。例如,如图20所示,两个加强筋401可以沿着第一半导体晶粒31和第二半导体晶粒32中的每一个的相对两侧的水平方向延伸。
图21和图22示出了本发明的另一个实施例,其中相同的数字表示相同的区域、层或元件。图21是根据本发明又一实施例的半导体封装的俯视示意图。图22是沿着图21中的虚线I-I'截取的横截面示意图。
如图21和图22所示,提供了一种半导体封装1i。半导体封装1i可以包括2.5D扇出(fan-out)半导体封装3。半导体封装1i包括具有上表面10a和底表面10b的封装基板10。2.5D扇出半导体封装3安装在上表面10a上。2.5D扇出半导体封装3包括:重分布层(RDL)结构21、第一半导体晶粒31、第二半导体晶粒32、模塑料60和连接元件202。第一半导体晶粒31和第二半导体晶粒32通过重分布层(RDL)结构21互连(interconnect)。RDL结构21形成在模塑料60和第一半导体晶粒31和第二半导体晶粒32的有源表面31a和32a上,以直接连接到第一半导体晶粒31和第二半导体晶粒32的接合焊盘。
根据一个实施例,第一半导体晶粒31可以包括专用集成芯片(ASIC)或微处理器,但是不限于这两种方式。第二半导体晶粒32可以包括其中堆叠有硅通孔(TSV)的多个存储器芯片的高带宽存储器(HBM)芯片。
在RDL结构21的底表面20b上设置有多个连接元件202。通过连接元件202,RDL结构21电连接到封装基板10。提供模塑料60以封装第一半导体晶粒31和第二半导体晶粒32。第一半导体晶粒31的背面表面31b和第二半导体晶粒32的背面表面32b没有被模塑料60覆盖。
根据本实施例,加强环40固定到封装基板10的上表面10a。加强环40可以沿着封装基板10的一周设置,以形成例如矩形形状。加强环40环绕第一半导体晶粒31和第二半导体晶粒32。根据本实施例,加强环40可以通过使用黏合层固定到封装基板10的上表面10a,但是固定方式不限于此。加强环40可以由铜构成,但材质不限于此。
加强环40可以包括横跨模塑料60的两个加强筋401。如图21所示,加强筋401通过下倾部分401b一体地连接到加强环40。加强筋401沿着2.5D扇出RDL结构的两个相对的侧边缘延伸。加强筋401与半导体晶粒31的背面表面31b部分重叠,与半导体晶粒32的背面表面32b部分重叠。加强筋401直接接触模塑料60的上表面60a。加强筋401也可以直接接触第一半导体晶粒31的背面表面31b和第二半导体晶粒32的背面表面32b。这样可以加强对半导体晶粒和模塑料的固定,保证半导体晶粒和模塑料的稳固性。
散热器50可以通过热界面材料层510直接接合到第一半导体晶粒31的背面表面31b、第二半导体晶粒32的背面表面32b和加强筋401的上表面401a。如图21所示,加强筋401可以与第一半导体晶粒31或第二半导体晶粒32的背面表面部分地重叠。为了清楚起见,图21中未示出散热器50。加强筋401可以与第一半导体晶粒31或第二半导体晶粒32的背面表面直接接触。当从上方观察时,加强筋401可以是横过模塑料60的直线形状的筋条。然而,可以理解的是,加强筋401可以具有其他形状。
本领域的技术人员将容易地观察到,在保持本发明教导的同时,可以做出许多该装置和方法的修改和改变。因此,上述公开内容应被解释为仅由所附权利要求书的界限和范围所限制。
Claims (12)
1.一种半导体封装,其特征在于,包括:
封装基板,具有上表面和底表面;
中间体,安装在所述封装基板的上表面上;
第一半导体晶粒和第二半导体晶粒,以并排的方式安装在所述中间体的上表面上;以及
加强环,安装在所述封装基板的上表面,其中所述加强环围绕所述第一半导体晶粒和第二半导体晶粒,所述加强环包括横跨所述中间体的加强筋,其中所述加强筋直接设置在所述中间体的上表面上,所述加强环的加强筋与所述加强环的其他部分不共面;所述加强筋延伸穿过所述第一半导体晶粒与所述第二半导体晶粒之间的空间。
2.根据权利要求1所述的半导体封装,其特征在于,进一步包括:
散热器,直接接合在所述第一半导体晶粒的背面表面和所述第二半导体晶粒的背面表面。
3.根据权利要求2所述的半导体封装,其特征在于,所述散热器通过热界面材料层直接接合到所述第一半导体晶粒的背面表面和所述第二半导体晶粒的背面表面。
4.根据权利要求1所述的半导体封装,其特征在于,所述加强筋通过下沉部分一体地连接到所述加强环。
5.根据权利要求1所述的半导体封装,其特征在于,所述加强筋与所述中间体的上表面直接接触。
6.根据权利要求1所述的半导体封装,其特征在于,所述加强筋沿着所述中间体的侧边缘延伸。
7.根据权利要求1所述的半导体封装,其特征在于,所述加强筋未与所述第一半导体晶粒或所述第二半导体晶粒重叠。
8.根据权利要求1所述的半导体封装,其特征在于,所述加强筋围绕所述第一半导体晶粒和所述第二半导体晶粒。
9.一种半导体封装,其特征在于,包括:
封装基板,具有上表面和底表面;
中间体,安装在所述封装基板的上表面上;
第一半导体晶粒和第二半导体晶粒,以并排的方式安装在所述中间体的上表面上;
模塑料,封装所述第一半导体晶粒和所述第二半导体晶粒;以及
加强环,固定到所述封装基板的上表面,其中所述加强环包括横跨所述模塑料的加强筋,其中所述加强筋直接设置在所述中间体的上表面上,所述加强环的加强筋与所述加强环的其他部分不共面;所述加强筋延伸穿过所述第一半导体晶粒与所述第二半导体晶粒之间的空间。
10.根据权利要求9所述的半导体封装,其特征在于,所述第一半导体晶粒的背面表面和所述第二半导体晶粒的背面表面未被所述模塑料覆盖。
11.根据权利要求9所述的半导体封装,其特征在于,所述加强筋部分地或完全地与所述第一半导体晶粒的背面表面重叠。
12.一种半导体封装,其特征在于,包括:
封装基板,具有上表面和底表面;
重分布层结构,安装在所述封装基板的上表面上;
第一半导体晶粒和第二半导体晶粒,以并排的方式安装在所述重分布层结构的上表面上;
模塑料,封装所述第一半导体晶粒和所述第二半导体晶粒;以及
加强环,固定到所述封装基板的上表面,其中所述加强环包括横跨所述模塑料的加强筋,其中所述加强筋直接设置在所述重分布层结构的上表面上,所述加强环的加强筋与所述加强环的其他部分不共面;所述加强筋延伸穿过所述第一半导体晶粒与所述第二半导体晶粒之间的空间。
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