CN114582851A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN114582851A
CN114582851A CN202111053547.4A CN202111053547A CN114582851A CN 114582851 A CN114582851 A CN 114582851A CN 202111053547 A CN202111053547 A CN 202111053547A CN 114582851 A CN114582851 A CN 114582851A
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China
Prior art keywords
interposer substrate
substrate
package
semiconductor chip
heat radiation
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Pending
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CN202111053547.4A
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English (en)
Inventor
金东暤
金知晃
朴桓必
沈钟辅
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN114582851A publication Critical patent/CN114582851A/zh
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Abstract

提供了一种半导体封装，包括：下封装，所述下封装包括下基板和下半导体芯片；中介层基板，在所述下封装上并且具有穿透所述中介层基板的多个孔；热辐射结构，所述热辐射结构包括所述中介层基板的顶表面上的支撑部和所述中介层基板的孔中的多个突出部；以及导热层，在所述下半导体芯片和所述热辐射结构的突出部之间。

Description

半导体封装
相关申请的交叉引用
本申请要求于2020年11月30日在韩国知识产权局递交的韩国专利申请No.10-2020-0164363的优先权，其公开内容由此通过引用全部并入。
技术领域
本发明构思涉及一种半导体封装，更具体地涉及一种包括中介层基板的半导体封装。
背景技术
提供半导体封装以实现用以有资格用于电子产品中的集成电路芯片。通常，在半导体封装中，半导体芯片安装在印刷电路板(PCB)上，并且使用接合线或焊块将半导体芯片电连接到印刷电路板。半导体封装的速度和容量越高，半导体封装的功耗增加得越多。因此，半导体封装的热特性和可靠性变得越来越重要。
发明内容
本发明构思的一些示例实施例提供了具有更好的热辐射性质的半导体封装。
本发明构思的一些示例实施例提供了具有更高的可靠性的半导体封装及其制造方法。
根据本发明构思的一些示例实施例，一种半导体封装可以包括：下封装，所述下封装包括下基板和至少一个下半导体芯片；中介层基板，在所述下封装上，所述中介层基板具有穿透所述中介层基板的多个孔；热辐射结构，所述热辐射结构包括所述中介层基板的顶表面上的支撑部和所述中介层基板的孔中的多个突出部；以及导热层，在所述下半导体芯片和所述热辐射结构的突出部之间。
根据本发明构思的一些示例实施例，一种半导体封装可以包括：下封装，所述下封装包括下基板和至少一个下半导体芯片；中介层基板，在所述下封装上，所述中介层基板具有穿透所述中介层基板的多个孔；以及热辐射结构，在所述中介层基板上。所述热辐射结构可以包括：多个第一部分，在所述中介层基板的孔中并且与所述下半导体芯片竖直地重叠；以及多个第二部分，在所述中介层基板的顶表面上并且连接到所述第一部分。所述热辐射结构可以与所述中介层基板的孔的侧壁间隔开并且与所述下半导体芯片的顶表面间隔开。
根据本发明构思的一些示例实施例，一种半导体封装可以包括：下封装，所述下封装包括下基板、至少一个下半导体芯片、下模塑层和多个下连接结构；中介层基板，在所述下封装上，所述中介层基板具有穿透所述中介层基板的多个孔，在平面图中所述多个孔与所述下半导体芯片重叠；上封装，在所述中介层基板上，所述上封装包括上基板和至少一个上半导体芯片；多个上连接结构，在所述上基板和所述中介层基板之间并且耦合到所述上基板和所述中介层基板；热辐射结构，所述热辐射结构包括所述中介层基板的顶表面上的支撑部和所述多个孔中的突出部；以及导热层，在所述热辐射结构和所述下半导体芯片之间，所述导热层包括与所述热辐射结构的材料不同的材料。所述上连接结构可以与所述热辐射结构的所述支撑部横向间隔开。
附图说明
图1A示出了图示根据本发明构思的一些示例实施例的半导体封装的平面图。
图1B示出了沿着图1A的线I-II截取的截面图。
图1C示出了图示图1B的部分III的放大视图。
图2示出了图示根据一些示例实施例的热辐射结构的透视图。
图3A示出了图示根据一些示例实施例的下封装、中介层基板、导热层和热辐射结构的截面图。
图3B示出了图示根据一些示例实施例的下封装、中介层基板、导热层和热辐射结构的截面图。
图3C示出了图示根据一些示例实施例的下封装、中介层基板、导热层和热辐射结构的截面图。
图3D示出了图示根据一些示例实施例的下封装、中介层基板、导热层和热辐射结构的截面图。
图4A示出了图示根据一些示例实施例的半导体封装的截面图。
图4B示出了图示根据一些示例实施例的半导体封装的截面图。
图4C示出了图示根据一些示例实施例的半导体封装的截面图。
图5A至图5D示出了图示根据一些示例实施例的制造半导体封装的方法的截面图。
具体实施方式
在本说明书中，虽然可以在本文中使用术语“第一”、“第二”、“第三”等来描述各种元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分不应受这些术语限制。这些术语仅用于将一个元件、组件、区域、层和/或部分与另一个区域、层和/或部分加以区分。因此，在不脱离本公开的范围的情况下，下面讨论的第一元件、组件、区域、层和/或部分可以被称为第二元件、组件、区域、层和/或部分。
在本文中可以使用空间相对术语如“横向地”、“下”、“底”、“上”、“顶”等，以便于描述一个元件或特征相对于另一元件或特征在附图中示出的关系。将理解的是，空间相对术语除了包括附图中示出的定向之外，还意在包含设备在使用或操作中的不同定向。例如，设备可以以其他方式定向(旋转90度和/或在其他方向)，且可以相应地解释本文中使用的空间相对描述符。
当在本说明书中与数值相结合地使用术语“约”或“基本上”时，相关联的数值意在包括在所述数值附近的制造公差(例如，±10％)。此外，当词语“一般地”和“基本上”与几何形状结合使用时，意在不要求几何形状的精度，但是该形状的宽容度在本公开的范围内。此外，无论数值或形状是否被“约”或“基本上”修饰，都将理解的是，这些值和形状应该被解释为，包括所述数值或形状附近的制造或操作公差(例如，±10％)。
除非另外指出，否则相同的附图标记可以表示相同的组件。现在将描述根据本发明构思的半导体封装及其制造方法。
图1A示出了图示根据一些示例实施例的半导体封装的平面图。图1B示出了沿着图1A的线I-II截取的截面图。图1C示出了图示图1B的部分III的放大视图。图2示出了图示根据一些示例实施例的热辐射结构的透视图。
参考图1A、图1B、图1C和图2，半导体封装可以包括下封装100、上封装500、上连接结构400、中介层基板200、热辐射结构310和导热层350。下封装100可以包括下基板110、下半导体芯片120、下模塑层130和下连接结构140。在一些实施例中，印刷电路板(PCB)和/或再分布层可以用作下基板110。下基板110可以包括介电基层、第一基板焊盘111、第二基板焊盘112和内部接线113。当在平面图中观察时，第一基板焊盘111可以设置在下基板110的中心区的顶表面上。第二基板焊盘112可以设置在下基板110的边缘区的顶表面上。例如，下基板110的边缘区可以设置在下基板110的中心区和侧表面之间。第一基板焊盘111和/或第二基板焊盘112可以包括与金属相似的导电材料，例如，铝(A1)、铜(Cu)、钨(W)、钛(Ti)和/或其合金中的一种或多种。
内部接线113可以设置在下基板110中。内部接线113可以耦合到第一基板焊盘111和/或第二基板焊盘112。例如，至少一个第一基板焊盘111可以通过其对应的内部接线113耦合到对应的第二基板焊盘112。短语“两个组件彼此电连接/耦合”可以包括两个组件彼此直接地或通过其他导电组件彼此间接地连接/耦合的意思。例如，短语“电连接到下基板110”可以意指“电连接到内部接线113”。内部接线113可以包括与金属相似的导电材料，例如，铝(A1)、铜(Cu)、钨(W)、钛(Ti)和/或其合金中的一种或多种。在以下附图中，下基板110中的实线示意性地表示内部接线113。
半导体封装还可以包括焊接端子150。焊接端子150可以设置在下基板110的底表面上并且电耦合到内部接线113。外部电信号可以通过焊接端子150传输到内部接线113。焊接端子150可以电耦合到第一基板焊盘111和/或第二基板焊盘112。例如，焊接端子150可以通过内部接线113电耦合到第一基板焊盘111或第二基板焊盘112。焊接端子150可以包括导电焊盘和/或焊球，并且可以包括与金属相似的导电材料，例如，焊接材料。焊接材料可以包括锡(Sn)、银(Ag)、锌(Zn)和/或其合金。
在一些实施例中，下半导体芯片120可以是接合到下基板110的倒装芯片。下半导体芯片120可以用作逻辑芯片。例如，下半导体芯片120可以充当非存储器芯片，例如，应用处理器。又例如，下半导体芯片120可以是片上系统。下半导体芯片120中可以具有集成电路，并且可以包括逻辑电路、存储器电路和/或其组合。下半导体芯片120可以包括设置在下半导体芯片120的底表面上的芯片焊盘121。下半导体芯片120的底表面可以对着下基板110。芯片焊盘121可以电连接到下半导体芯片120的集成电路。因此，下半导体芯片120的底表面可以充当有源表面。下半导体芯片120可以具有与底表面相对的顶表面120a；顶表面120a可以是例如无源表面。在本说明书中，短语“电连接到半导体芯片的芯片焊盘”也可以意指“电连接到半导体芯片”。表述“电连接到半导体芯片”可以意指“电连接到半导体芯片的集成电路”。
焊块125可以设置在下基板110和下半导体芯片120之间。例如，焊块125可以电连接到第一基板焊盘111和/或芯片焊盘121。例如，焊块125可以电连接第一基板焊盘111和芯片焊盘121。焊块125可以包括焊料和/或柱中的一个或多个。焊块125可以包括导电材料，例如焊接材料。
在一些示例实施例中，可以使用热压缩接合法将下半导体芯片120安装在下基板110上。在这种情况下，下半导体芯片120可以与下基板110直接物理接触，并且芯片焊盘121可以直接耦合到对应的第一基板焊盘111。
下基板110上可以设置有与下半导体芯片120横向间隔开的下连接结构140。短语“横向设置”可以意指“在第一方向D1上、在第二方向D2上、在与第一方向D1相对的方向上、和/或在与第二方向D2相对的方向上设置”。第一方向D1可以与下基板110的顶表面平行。第二方向D2可以与下基板110的顶表面平行，同时与第一方向D1相交。第三方向D3可以与下基板110的顶表面基本上垂直。当在平面图中观察时，下连接结构140可以设置在下基板110的边缘区上。例如，当在平面图中观察时，下连接结构140可以插入在下半导体芯片120和下基板110的侧表面之间。下连接结构140可以设置在对应的第二基板焊盘112上和/或电耦合到对应的第二基板焊盘112。因此，下连接结构140可以(例如，通过内部接线113)电耦合到下半导体芯片120和/或焊接端子150。下连接结构140可以包括金属柱、焊接球、导电柱和/或其组合。下连接结构140可以包括导电材料，例如金属和/或焊接材料。
中介层基板200可以设置在下封装100上。例如，中介层基板200可以设置在下半导体芯片120和下连接结构140上。中介层基板200可以具有彼此相对的顶表面200a和底表面200b。中介层基板200可以包括和/或可以是绝缘体，例如，绝缘树脂和/或聚合物。绝缘树脂可以包括阻焊材料，例如，光敏聚酰亚胺，但是本发明构思不限于此。绝缘聚合物可以是环氧树脂基模塑料，但是本发明构思不限于此。中介层基板200可以具有穿透中介层基板200的孔290。例如，孔290可以穿透中介层基板200的顶表面200a和底表面200b。当在如图1A所示的平面图中观察时，孔290可以与下半导体芯片120重叠。当在平面图中观察时，孔290自身可以具有圆形形状。备选地，当在平面图中观察时，每个孔290可以具有四边形形状、六边形形状、八边形形状和/或任意合适的多边形形状。
中介层基板200可以包括下焊盘210、金属接线230和上焊盘220。下焊盘210和上焊盘220可以分别设置在中介层基板200的底表面200b和顶表面200a上。下焊盘210和上焊盘220可以与孔290横向间隔开。例如，在一些实施例中，下焊盘210和/或上焊盘220可以在下基板100的边缘区上方。下焊盘210可以对应地电耦合到下连接结构140。金属接线230可以设置在中介层基板200中。上焊盘220可以通过金属接线230电连接到下焊盘210。至少一个上焊盘220可以不与下焊盘210竖直重叠且不连接到下焊盘210。在本说明书中，术语“竖直的”或“竖直地”可以意指“与第三方向D3平行”。上焊盘220的数量和布置可以自由地设计而不受下连接结构140的数量和布置的限制。下焊盘210、金属接线230和上焊盘220可以包括诸如金属的导电材料。
上封装500可以设置在中介层基板200上。上封装500可以包括上衬底510和上半导体芯片520。上基板510可以包括第一导电焊盘511、第二导电焊盘512和/或导电接线513。第一导电焊盘511和第二导电焊盘512可以分别设置在基板510的底表面和顶表面上。导电接线513可以设置在上基板510中。第二导电焊盘512可以通过导电接线513电耦合到第一导电焊盘511。
上半导体芯片520可以安装在上基板510的顶表面上。例如，上半导体芯片520可以通过接合线540电连接到上基板510。短语“电连接到上基板510”可以意指“电连接到至少一条导电接线513”。又例如，上半导体芯片520可以以倒装方式安装在上基板510上。上半导体芯片520可以具有与下半导体芯片120的功能不同的功能。例如，上半导体芯片520可以充当存储器芯片。上半导体芯片520可以设置为单个芯片和/或设置为多个芯片的部分。例如，多个上半导体芯片520可以彼此横向间隔开和/或多个上半导体芯片520可以彼此堆叠。为了描述的简洁，以下将集中描述单个上半导体芯片520，但是本发明构思不限于此。
上封装500还可以包括上模塑层530。上基板510上可以设置有上模塑层530，上模塑层530密封接合线540、上半导体芯片520的顶表面和/或上半导体芯片520的至少一个侧壁。上模塑层530可以包括例如与绝缘聚合物相似的绝缘体，例如，环氧树脂基模塑料和/或阻焊材料。
上连接结构400可以插入在上基板510和中介层基板200之间。例如，上连接结构400可以对应地插入在中介层基板200的上焊盘220和上基板510的第一导电焊盘511之间并且电耦合到两者。上半导体芯片520可以通过上基板510、上连接结构400和下连接结构140电连接到下半导体芯片120和/或焊接端子150。
热辐射结构310可以设置在孔290中以及中介层基板200的顶表面200a上。热辐射结构310可以与上连接结构400横向间隔开。例如，在一些实施例中，热辐射结构310可以设置在下基板110的中心区上方。热辐射结构310可以包括与金属相似的导热材料，例如，铜(Cu)、铝(Al)和/或其合金。例如，可以处理金属板以制造热辐射结构310。
热辐射结构310可以包括支撑部311和突出部313。热辐射结构310的突出部313可以设置在中介层基板200的对应的孔290中。因此，突出部313的底表面的高度可以比中介层基板200的顶表面200a的高度低。在本说明书中，术语“高度”可以表示“竖直高度”，并且表述“高度上的差异”可以是在与第三方向D3平行的方向上测量得到的。因为热辐射结构310的突出部313设置在中介层基板200的孔290中，所以即使设置了热辐射结构310，半导体封装在尺寸上也可以减小。突出部313可以与对应的孔290的侧壁间隔开。孔290的侧壁可以对应于中介层基板200的内壁(图1C的200c)。突出部313可以与下半导体芯片120的顶表面120a间隔开。因此，突出部313的底表面可以位于比下半导体芯片120的顶表面120a的高度高的高度。每个突出部313可以具有例如圆柱形状，但不限于此。例如，突出部313可以具有无需限制为图1A和图2所示的形状的各种形状。在一些实施例中，当在平面图中观察时，每个突出部313可以具有与对应的孔290相匹配的形状。例如，突出部313可以具有四边形形状、六边形形状、八边形形状和/或任意合适的多边形形状。当在平面图中观察时，突出部313可以沿第一方向D1和第二方向D2布置。突出部313的平面布置不限于所示的平面布置，而是可以进行不同地改变。例如，突出部313可以以蜂窝或Z字形状布置。突出部313可以是热辐射结构310的第一部分。
热辐射结构310的支撑部311可以设置在中介层基板200的顶表面200a上。支撑部311可以与上连接结构400横向间隔开。当在如图1A所示的平面图中观察时，支撑部311可以设置在中介层基板200的中心区上，并且上连接结构400可以设置在中介层基板200的边缘区上。例如，上连接结构400可以设置在支撑部311和中介层基板200的侧壁之间。当在平面图中观察时，上连接结构400可以设置为包围支撑部311。
如图1B和图1C所示，支撑部311可以设置在突出部313上并且连接到突出部313。例如，支撑部311和突出部313可以包括相同的材料和/或可以在它们之间没有边界地连接。支撑部311的宽度W1可以比每个突出部313的宽度宽。支撑部311的宽度W1可以对应于热辐射结构310的顶表面的宽度。在一些实施例中，支撑部311的宽度W1的范围可以例如从约30μm到约500μm。因为支撑部311的宽度W1等于或小于约500μm，所以热辐射结构310不会对上连接结构400的布置施加限制。支撑部311可以与中介层基板200的顶表面200a和上基板510的底表面间隔开。支撑部311的顶表面的高度可以比中介层基板200的顶表面200a的高度高。支撑部311的顶表面的高度可以比上基板510的底表面的高度低。支撑部311可以是热辐射结构310的第二部分。虽然被示出为四边形块，但是支撑部311不限于此，并且可以是不同的形状和/或可以包括不同的形状。在一些实施例中，支撑部311的至少一个表面可以形成纹理以增大支撑部311的表面面积，由此增加来自热辐射结构310的热耗散。
当半导体封装操作时，可能从下半导体芯片120产生比较多的热量。例如，从下半导体芯片120产生的热量的量可以大于从上半导体芯片520产生的热量的量。下半导体芯片120的热辐射特性越好，半导体封装的热性质的改善越大。当上封装500在其顶表面上具有热沉和/或散热片时，热沉或散热片在接收从下半导体芯片120产生的热量时可能具有困难。根据一些示例实施例，因为热辐射结构310设置在下半导体芯片120上，从下半导体芯片120产生的热量可以不到达上封装500，而是传送到热辐射结构310。因此，从下半导体芯片120产生的热量可以迅速地释放以改善半导体封装的热性质。根据一些示例实施例，因为支撑部311的宽度W1等于或大于约30μm，所以下半导体芯片120可以有效地改善热辐射特性。根据一些实施例，上封装500可以包括一个或多个上半导体芯片520的堆叠。在这种情况下，例如，在半导体芯片520包括存储器芯片、逻辑芯片、缓冲器芯片、控制器芯片、应用处理器芯片、中介层芯片和/或其组合的情况下，热辐射结构310和/或导热层350可以设置在一些和/或所有的半导体芯片520之间，从而半导体芯片520的堆叠中产生的热量可以耗散而不到达上封装500的上边缘和/或侧边缘。
可以在上封装500的安装工艺中利用压力和热量来设置上连接结构400。在这种情况下，压力可以迫使至少两个上连接结构400彼此接触以引起至少两个上连接结构400之间的电短路。根据一些示例实施例，因为对热辐射结构310设置支撑部311，所以可以防止上连接结构400在上封装500的安装工艺中接收过量的压力。因此，可以防止上连接结构400之间出现电短路，并且可以提高半导体封装的可靠性。支撑部311的上表面和上基板510的下表面之间可以存在气隙或可以不存在气隙。
如图1C所示，支撑部311的高度H1可以为每个上连接结构400的高度H2的约0.7倍到约0.9倍。因为支撑部311的高度H1等于或大于每个上连接结构400的高度H2的约0.7倍，所以下连接结构140可以有效地防止在上封装500的安装工艺中接收过量的压力。因为支撑部311的高度H1等于或小于每个上连接结构400的高度H2的约0.9倍，所以半导体封装可以变得尺寸紧凑。
当单个孔290设置在中介层基板200中时，可能需要孔290具有较大的宽度以充分释放来自下半导体芯片120的热量。在这种情况下，可能在半导体封装制造中难以处理中介层基板200。根据一些示例实施例，中介层基板200可以具有多个孔290，并且可以调整孔290的宽度和两个相邻的孔290之前的间隔D。因此，可以容易地处理中介层基板200。中介层基板200的相邻的孔290之间的间隔D的范围可以从约30μm到约50μm。因为中介层基板200的相邻的孔290之间的间隔D等于或大于约30μm，所以可以更容易地处理中介层基板200。
因为多个突出部313设置在中介层基板200的对应的孔290中，所以从下半导体芯片120产生的热量可以通过多个突出部313迅速地释放。因为中介层基板200的相邻的孔290之间的间隔D等于或小于约50μm，所以下半导体芯片120可以设置有足够数量的突出部313。因此，下半导体芯片120可以有效地改善热辐射性质。
突出部313的间距P可以大于每个突出部313的宽度W2。例如，突出部313的间距P和宽度W2之间的差可以被赋予约20μm到约50μm的值。突出部313的间距P和宽度W2之间的差可以大于中介层基板200的两个相邻的孔290之间的间隔D。
导热层350可以设置在热辐射结构310和下半导体芯片120之间和/或热辐射结构310和中介层基板200之间。例如，导热层350可以设置在下半导体芯片120的顶表面120a和热辐射结构310的每个突出部313的底表面之间的第一间隔中，由此填充第一间隔。导热层350的导热率可以大于空气的导热率。因为导热层350设置在第一间隔中，所以当半导体封装操作时，热辐射结构310可以通过导热层350迅速地接收从下半导体芯片120产生的热量。导热层350可以设置在突出部313和中介层基板200的孔290的侧壁(例如，中介层基板200的内壁200c)之间的第二间隔中和/或设置在支撑部311和中介层基板200之间的第三间隔中，由此填充第二间隔和第三间隔。在每个孔290中，导热层350可以具有与中介层基板200和下模塑层130物理接触的外壁350c。
导热层350可以包括与导电热辐射结构310的材料不同的材料。例如，可以使用焊膏材料形成导热层350。在这种情况下，导热层350可以包括导电材料，例如，锡、铅、银和/或其任意合金。备选地，导热层350可以包括热界面材料(TIM)。热界面材料可以包括，例如，聚合物和导热粒子。导热粒子可以分布在聚合物中。导热粒子可以包括金属。导热层350可以处于固态。
下模塑层130可以设置在下基板110和中介层基板200之间的间隔中。下模塑层130可以密封下基板110、下半导体芯片120的顶表面120a和侧壁和/或下连接结构140的侧壁。例如，下模塑层130的可以与中介层基板200的底表面物理接触。例如，在下模塑层130的顶表面和中介层基板200的底表面之间可以不设置空的空间。当设置空的空间时，空气和/或湿气可以占据空的空间。相反，根据一些示例实施例，下模塑层130可以保护下连接结构140免于暴露到外部空气。因此可以防止下连接结构140由于外部湿气或杂质而被破坏，因此，半导体封装的可靠性可以提高。下模塑层130可以包括与绝缘聚合物相似的绝缘体，例如，环氧树脂模塑料(EMC)和/或绝缘树脂，例如，光敏聚酰亚胺。
下模塑层130可以包括延伸部130Z。延伸部130Z可以在下半导体芯片120的顶表面120a和中介层基板200的底表面之间延伸。延伸部130Z可以与下半导体芯片120的顶表面120a和中介层基板200的底表面接触。下模塑层130的延伸部130Z可以与导热层350的外壁350c物理接触。延伸部130Z可以具有与中介层基板200的对应的孔290竖直对准的侧壁。
下模塑层130还可以设置在下基板110和下半导体芯片120之间的间隔中，由此密封焊块125。备选地，下填充层(未示出)可以设置在下基板110和下半导体芯片120之间的间隔中，由此密封焊块125。下填充层可以包括绝缘聚合物和/或树脂。
中介层基板200可以具有与下封装100的宽度和上封装500的宽度基本上相同的宽度。与所示出的不同，中介层基板200的宽度可以与下封装100的宽度基本上相同且小于上封装500的宽度。例如，中介层基板200、下封装100和上封装500的宽度之间的关系可以进行不同的改变。
图3A至图3D示出了图示根据一些示例实施例的下封装、中介层基板、导热层和热辐射结构的放大截面图。下面将省略重复的描述。
参考图3A至图3D，热辐射结构310的支撑部311可以设置在上中介层基板200的顶表面200a上，并且热辐射结构310的突出部313可以设置在中介层基板200的对应的孔290中。热辐射结构310的突出部313可以连接到热辐射结构310的支撑部311。突出部313可以从支撑部311朝着下半导体芯片120突出。突出部313的底表面可以对应于热辐射结构310的底表面。导热层350可以设置在下半导体芯片120的顶表面120a和突出部313的底表面之间的第一间隔中，由此覆盖下半导体芯片120的顶表面120a。导热层350可以以许多方式设置。下面将详细描述根据一些示例实施例的导热层350的布置。
如图3A所示，导热层350可以不延伸到中介层基板200的孔290的侧壁和/或突出部313的侧壁上。例如，如图所示，导热层350可以接触和/或湿润中介层基板200的孔290的侧壁但是可以不延伸到孔290的侧壁上。
如图3B所示，导热层350可以填充第一间隔并且还可以在对应的突出部313和孔290的侧壁之间延伸。导热层350最上面的表面350a的高度可以比中介层基板200的顶表面200a的高度低。
如图3C所示，导热层350可以设置在第一间隔中并且设置在孔290的侧壁和突出部313之间的第二间隔中，并且还可以延伸到中介层基板200的顶表面200a和支撑部311的底表面之间的第三间隔中。导热层350的端部350Z可以设置在中介层基板200的顶表面200a和支撑部311的底表面之间。底切区390可以设置在中介层基板200的顶表面200a和支撑部311的底表面之间。底切区390可以例如显露导热层350的端部350Z。底切区390可以在空间上连接到外部，并且在底切区390中可以提供空气。
如图3D所示，导热层350可以设置在突出部313和下半导体芯片120之间、突出部313和中介层基板200之间、以及支撑部311和中介层基板200之间。导热层350的端部350Z可以设置在支撑部311的外壁311c外部。例如，导热层350还可以覆盖支撑部311的外壁311c的至少一部分。
图4A示出了图示根据一些示例实施例的半导体封装的沿着图1A的线I-II截取的截面图。
参考图4A，半导体封装可以包括：下封装100、上封装500、中介层基板200、上连接结构400、热辐射结构310和导热层350。
下封装100可以包括下基板110、多个下半导体芯片120、下模塑层130和下连接结构140。多个下半导体芯片120可以包括彼此横向间隔开的第一下半导体芯片120X和第二下半导体芯片120Y。第一下半导体芯片120X和第二下半导体芯片120Y中的每一个可以与图1A至图1C的示例中所讨论的下半导体芯片120基本上相同。例如，第一下半导体芯片120X和第二下半导体芯片120Y可以通过焊块125电连接到下基板110。
孔290可以穿过中介层基板200。当在平面图中观察时，中介层基板200的一些孔290可以与第一下半导体芯片120X重叠和/或另一些孔290可以与第二下半导体芯片120Y重叠。
热辐射结构310可以具有包括第一突出部313X和第二突出部313Y的突出部313。第一突出部313X可以设置在第一下半导体芯片120X的上顶表面上，并且第二突出部313Y可以设置在第二下半导体芯片120Y的上顶表面上。热辐射结构310可以具有支撑部311，支撑部311设置在中介层基板200的顶表面200a、第一突出部313X和第二突出部313Y上并且连接到第一突出部313X和第二突出部313Y。
导热层350可以插入在第一下半导体芯片120X和第一突出部313X之间以及第二下半导体芯片120Y和第二突出部313Y之间。导热层350还可以在热辐射结构310和中介层基板200的孔290的内壁之间延伸。导热层350还可以设置在热辐射结构310和中介层基板200的顶表面200a之间。虽然被示出为如上所述地填充第一间隔、第二间隔和第三间隔，但是导热层350不限于此，并且可以例如是和/或包括图3A至图3D的导热层350中的至少一种。
导热层350和热辐射结构310可以用于向外部释放从第一下半导体芯片120X和第二下半导体芯片120Y产生的热量。
图4B示出了图示根据一些示例实施例的半导体封装的沿着图1A的线I-II截取的截面图。
参考图4B，半导体封装可以包括：下封装100、上封装500、中介层基板200、上连接结构400、第一热辐射结构310X、第二热辐射结构310Y、第一导热层350X和第二导热层350Y。下封装100可以包括下基板110、多个下半导体芯片120(例如，第一下半导体芯片120X和第二下半导体芯片120Y)、下模塑层130和下连接结构140。多个下半导体芯片120(例如，第一下半导体芯片120X和第二下半导体芯片120Y)中的每一个可以与对应的孔290竖直地重叠。
第一热辐射结构310X可以设置在第一下半导体芯片120X上，并且第二热辐射结构310Y可以设置在第二下半导体芯片120Y上。第二热辐射结构310Y可以与第一热辐射结构310X横向间隔开。第一热辐射结构310X和第二热辐射结构310Y中的每一个可以与图1A至图1C的示例中所讨论的热辐射结构310基本上相同。例如，第一热辐射结构310X和第二热辐射结构310Y中的每一个可以包括支撑部311和突出部313。
第一导热层350X可以插入在第一热辐射结构310X和第一下半导体芯片120X之间。第一导热层350X还可以在第一热辐射结构310X和中介层基板200之间延伸。第二导热层350Y可以插入在第二热辐射结构310Y和第二下半导体芯片120Y之间。第二导热层350Y还可以在第二热辐射结构310Y和中介层基板200之间延伸。第一导热层350X和第二导热层350Y中的每一个可以与图1A至图1C和/或图3A至图3D的示例中讨论的导热层350基本上相同的。
图4C示出了图示根据一些示例实施例的半导体封装的沿着图1A的线I-II截取的截面图。
参考图4C，半导体封装可以包括：下封装100、上封装500、中介层基板200、上连接结构400、热辐射结构310和导热层350。下封装100可以包括下基板110、多个下半导体芯片120(例如，第一下半导体芯片120X和第二下半导体芯片120Y)、下模塑层130和下连接结构140。第一下半导体芯片120X和第二下半导体芯片120Y可以与图4A和/或4B中所讨论的那些基本上相同。相反，第一下半导体芯片120X的类型可以与第二下半导体芯片120Y的类型不同。例如，第一下半导体芯片120X可以是逻辑芯片、应用处理器芯片或片上系统，和/或第二下半导体芯片120Y可以包括电源管理集成电路(PMIC)并且可以充当电源管理芯片。当半导体封装操作时，可以从第一下半导体芯片120X产生大量的热量。例如，在这种情况下，第一下半导体芯片120X可以产生比第二下半导体芯片120Y更多的热量。
中介层基板200可以具有孔290，并且当在平面图中观察时，孔290可以与第一下半导体芯片120X重叠而可以不与第二下半导体芯片120Y重叠。
热辐射结构310可以设置在中介层基板200上以及设置在孔290中。热辐射结构310可以包括设置在第一下半导体芯片120X的顶表面上的突出部313。导热层350可以插入在热辐射结构310和第一下半导体芯片120X之间以及热辐射结构310和中介层基板200之间。热辐射结构310和导热层350均可以不设置在第二下半导体芯片120Y的顶表面上。
半导体封装的实施例可以彼此组合。例如，可以存在从图1A至图1C的实施例、图3A的实施例、图3B的实施例、图3C的实施例、图4A的实施例、图4B的实施例和图4C的实施例选择的至少两个的组合。
图5A至图5D示出了图示根据一些示例实施例的制造半导体封装的方法的沿图1A的线I-II截取的截面图。
参考图5A，可以制备下封装100。下封装100可以包括在图1A至图1C中讨论的下基板110、至少一个下半导体芯片120、下模塑层130和下连接结构140。
中介层基板200可以设置在下封装100上。中介层基板200可以包括下焊盘210、金属接线230和上焊盘220。下焊盘210可以耦合到对应的下连接结构140。中介层基板200的底表面可以与下模塑层130的顶表面物理接触。可以不在中介层基板200的底表面和下模塑层130的顶表面之间单独设置空的空间。
参考图5B，可以在中介层基板200和/或下模塑层130中形成孔290。形成孔290可以包括执行铣削、钻孔和/或蚀刻工艺以去除中介层基板200的一部分。在这个步骤中，孔290还可以延伸到下模塑层130以显露下半导体芯片120的顶表面120a。例如，孔290的形成可以持续到显露下半导体芯片120的顶表面120a为止。
备选地，在制备在其中形成孔290的中介层基板200以后，中介层基板200可以设置在下模塑层130和下连接结构140上。可以去除下模塑层130的显露孔290的部分，以使得孔290显露下半导体芯片120的顶表面120a。
参考图5C，可以在中介层基板200的孔290中形成初步导热层350P。初步导热层350P可以覆盖下半导体芯片120的顶表面120a。在一些实施例中，初步导热层350P还可以延伸到孔290的侧壁和/或中介层基板200的顶表面200a上。初步导热层350P可以具有流动性(例如，是可延展的、半液体和/或液体)。例如，形成初步导热层350P可以包括向孔290提供焊膏材料。又例如，可以向孔290提供热界面材料以形成初步导热层350P。
参考图5D，热辐射结构310可以设置在中介层基板200上。例如，可以制备包括图2所示的支撑部311和突出部313的热辐射结构310。热辐射结构310可以设置在中介层基板200上，并且热辐射结构310的突出部313可以与中介层基板200的孔290对准。热辐射结构310可以下降，以向孔290设置突出部313。在这个步骤中，因为初步导热层350P具有流动性，所以初步导热层350P可以令人满意地填充热辐射结构310和下半导体芯片120之间的第一间隔。初步导热层350P还可以填充热辐射结构310和中介层基板200之间的间隔。然后，初步导热层350P可以固化，以形成导热层350。形成导热层350可以包括固化初步导热层350P中包括的聚合物，但是本发明构思不限于此。
返回参考图1B，上封装500可以安装在中介层基板200上。安装上封装500可以包括：将上封装500设置在中介层基板200上，以及在上封装500和中介层基板200之间形成上连接结构400。回流工艺可以导致上连接结构400对应地耦合到中介层基板200的上焊盘220。上连接结构400可以将上封装500物理和/或电连接到中介层基板200。与图5D的讨论不同，固化初步导热层350P可以在上连接结构400的回流工艺期间执行，因此可以形成导热层350。
上述过程可以制造半导体封装。
根据本发明构思，因为在下半导体芯片上设置了热辐射结构，所以半导体封装的热特性可以改善。热辐射结构可以包括支撑部和突出部。热辐射结构的突出部设置在中介层基板的对应的孔中，因此半导体封装的尺寸可以减小。热辐射结构的支撑部可以设置在中介层基板的顶表面上，因此在安装上封装的过程中，可以防止上连接结构彼此物理接触。因此，半导体封装的可靠性可以提高。
本发明构思的详细描述不应被解释为限于本文阐述的实施例，本发明构思意在覆盖本发明的各种组合、修改和变化而不脱离本发明构思的精神和范围。所附权利要求应被解释为包括其他实施例。

Claims (20)

1.一种半导体封装，包括：
下封装，包括下基板和至少一个下半导体芯片；
中介层基板，在所述下封装上，所述中介层基板包括穿透所述中介层基板的多个孔；
热辐射结构，包括所述中介层基板的顶表面上的支撑部和所述中介层基板的孔中的多个突出部；以及
导热层，在所述下半导体芯片和所述热辐射结构的突出部之间。
2.根据权利要求1所述的半导体封装，其中，所述导热层包括与所述热辐射结构的材料不同的材料。
3.根据权利要求2所述的半导体封装，其中，所述导热层包括焊膏材料或热界面材料中的至少一种。
4.根据权利要求1所述的半导体封装，其中：
所述下封装还包括所述下基板和所述中介层基板之间的下模塑层，
所述下模塑层包括延伸部，并且
所述延伸部在所述下半导体芯片的顶表面和所述中介层基板的底表面之间。
5.根据权利要求4所述的半导体封装，其中，所述下模塑层的所述延伸部与所述导热层物理接触。
6.根据权利要求4所述的半导体封装，其中，所述中介层基板的孔的侧壁与所述下模塑层的所述延伸部的侧壁对准。
7.根据权利要求4所述的半导体封装，其中，所述下模塑层与所述中介层基板的底表面物理接触。
8.根据权利要求1所述的半导体封装，其中，所述导热层还在所述热辐射结构和所述中介层基板之间。
9.根据权利要求1所述的半导体封装，还包括：
上封装，在所述中介层基板和所述热辐射结构上；以及
上连接结构，在所述中介层基板和所述上封装之间，
其中，所述上连接结构与所述热辐射结构横向间隔开。
10.根据权利要求9所述的半导体封装，其中，所述支撑部的高度是所述上连接结构的高度的0.7倍到0.9倍。
11.根据权利要求1所述的半导体封装，其中，相邻的两个孔之间在横向方向上的间隔在20μm到50μm的范围中。
12.根据权利要求1所述的半导体封装，其中，所述支撑部在横向方向上的宽度在30μm到500μm的范围中。
13.根据权利要求1所述的半导体封装，其中，当在平面图中观察时，所述中介层基板的孔与所述至少一个下半导体芯片重叠。
14.一种半导体封装，包括：
下封装，包括下基板和至少一个下半导体芯片；
中介层基板，在所述下封装上，所述中介层基板包括穿透所述中介层基板的多个孔；以及
热辐射结构，在所述中介层基板上，所述热辐射结构包括：
多个第一部分，在所述中介层基板的孔中并且与所述下半导体芯片竖直地重叠，以及
多个第二部分，在所述中介层基板的顶表面上并且连接到所述第一部分，
其中，所述热辐射结构与所述中介层基板的孔的侧壁间隔开并且与所述下半导体芯片的顶表面间隔开。
15.根据权利要求14所述的半导体封装，还包括：
导热层，在所述下半导体芯片和所述热辐射结构的第一部分之间，
其中，所述导热层包括与所述热辐射结构的材料不同的材料。
16.根据权利要求15所述的半导体封装，其中：
所述下封装还包括所述下基板和所述中介层基板之间的下模塑层，
所述下模塑层包括所述下半导体芯片和所述中介层基板之间的延伸部，并且
所述下模塑层的所述延伸部与所述导热层的外壁物理接触。
17.根据权利要求14所述的半导体封装，还包括：
上基板，在所述中介层基板和所述热辐射结构上；以及
上连接结构，在所述中介层基板和所述上基板之间，
其中，第二部分的高度是所述上连接结构的高度的0.7倍到0.9倍。
18.一种半导体封装，包括：
下封装，包括下基板、至少一个下半导体芯片、下模塑层和多个下连接结构；
中介层基板，在所述下封装上，所述中介层基板包括穿透所述中介层基板的多个孔，在平面图中所述多个孔与所述下半导体芯片重叠；
上封装，在所述中介层基板上，所述上封装包括上基板和至少一个上半导体芯片；
多个上连接结构，在所述上基板和所述中介层基板之间并且耦合到所述上基板和所述中介层基板；
热辐射结构，包括所述中介层基板的顶表面上的支撑部和所述多个孔中的突出部；以及
导热层，在所述热辐射结构和所述下半导体芯片之间，所述导热层包括与所述热辐射结构的材料不同的材料，
其中，所述上连接结构与所述热辐射结构的所述支撑部横向间隔开。
19.根据权利要求18所述的半导体封装，其中：
所述突出部的底表面的高度比所述中介层基板的顶表面的高度低，并且
所述突出部的底表面的高度比所述至少一个下半导体芯片的顶表面的高度高。
20.根据权利要求18所述的半导体封装，其中：
所述下模塑层在所述下基板和所述中介层基板之间，
所述下模塑层在所述至少一个下半导体芯片的顶表面和所述中介层基板的底表面之间延伸，并且
所述下模塑层与所述导热层物理接触。
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