CN107767894B - 半导体存储装置 - Google Patents
半导体存储装置 Download PDFInfo
- Publication number
- CN107767894B CN107767894B CN201710134239.1A CN201710134239A CN107767894B CN 107767894 B CN107767894 B CN 107767894B CN 201710134239 A CN201710134239 A CN 201710134239A CN 107767894 B CN107767894 B CN 107767894B
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- Prior art keywords
- circuit
- calibration
- voltage
- semiconductor memory
- command
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- Dram (AREA)
- Read Only Memory (AREA)
- Memory System (AREA)
Abstract
Description
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016161061A JP6640677B2 (ja) | 2016-08-19 | 2016-08-19 | 半導体記憶装置 |
JP2016-161061 | 2016-08-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107767894A CN107767894A (zh) | 2018-03-06 |
CN107767894B true CN107767894B (zh) | 2021-05-28 |
Family
ID=61192091
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710134239.1A Active CN107767894B (zh) | 2016-08-19 | 2017-03-08 | 半导体存储装置 |
Country Status (4)
Country | Link |
---|---|
US (2) | US10121549B2 (zh) |
JP (1) | JP6640677B2 (zh) |
CN (1) | CN107767894B (zh) |
TW (1) | TWI653641B (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6640677B2 (ja) * | 2016-08-19 | 2020-02-05 | キオクシア株式会社 | 半導体記憶装置 |
JP2018045743A (ja) | 2016-09-13 | 2018-03-22 | 東芝メモリ株式会社 | 半導体装置及びメモリシステム |
JP2020027674A (ja) * | 2018-08-10 | 2020-02-20 | キオクシア株式会社 | 半導体メモリ |
CN111933205B (zh) * | 2020-08-04 | 2023-02-24 | 西安紫光国芯半导体有限公司 | Zq校准器、zq校准方法以及多通道存储器 |
JP2023043011A (ja) | 2021-09-15 | 2023-03-28 | キオクシア株式会社 | 半導体記憶装置 |
JP2023127385A (ja) * | 2022-03-01 | 2023-09-13 | キオクシア株式会社 | メモリシステム |
CN115938424B (zh) * | 2023-03-03 | 2023-06-23 | 长鑫存储技术有限公司 | 一种电阻校准电路、电阻校准方法和存储器 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103811059A (zh) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | 一种非挥发存储器参考校准电路与方法 |
CN104916315A (zh) * | 2014-03-14 | 2015-09-16 | 株式会社东芝 | 半导体存储装置 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4199789B2 (ja) * | 2006-08-29 | 2008-12-17 | エルピーダメモリ株式会社 | 半導体装置の出力回路調整方法 |
KR100862316B1 (ko) * | 2007-03-08 | 2008-10-13 | 주식회사 하이닉스반도체 | 반도체 메모리장치, 반도체 메모리장치의 zq캘리브래이션동작 제어회로 및 반도체 메모리장치의 zq캘리브래이션방법 |
KR100902104B1 (ko) | 2007-06-08 | 2009-06-09 | 주식회사 하이닉스반도체 | 반도체 메모리장치 |
JP2010117987A (ja) * | 2008-11-14 | 2010-05-27 | Denso Corp | メモリ制御装置、およびメモリ制御プログラム |
KR101045086B1 (ko) | 2009-06-08 | 2011-06-29 | 주식회사 하이닉스반도체 | 터미네이션 회로 및 이를 포함하는 임피던스 매칭 장치 |
JP2011081893A (ja) * | 2009-09-11 | 2011-04-21 | Elpida Memory Inc | 半導体装置及びこれを備えるデータ処理システム |
JP2011101143A (ja) * | 2009-11-05 | 2011-05-19 | Elpida Memory Inc | 半導体装置及びそのシステムとキャリブレーション方法 |
CN103455077B (zh) * | 2012-05-31 | 2016-08-03 | 华为技术有限公司 | 一种自适应调整电压的方法、装置及系统 |
KR20140008745A (ko) * | 2012-07-11 | 2014-01-22 | 삼성전자주식회사 | 자기 메모리 장치 |
KR102089613B1 (ko) * | 2013-01-02 | 2020-03-16 | 삼성전자주식회사 | 불 휘발성 메모리 장치 및 그것을 포함한 메모리 시스템 |
KR20140107890A (ko) * | 2013-02-28 | 2014-09-05 | 에스케이하이닉스 주식회사 | 메모리, 이를 포함하는 메모리 시스템 및 메모리 콘트롤러의 동작 방법 |
US9779039B2 (en) | 2013-08-29 | 2017-10-03 | Micron Technology, Inc. | Impedance adjustment in a memory device |
KR102185284B1 (ko) | 2013-12-12 | 2020-12-01 | 삼성전자 주식회사 | 온 다이 터미네이션 저항들의 부정합을 보상하는 버퍼 회로, 반도체 장치 반도체 장치의 동작방법 |
KR102251810B1 (ko) * | 2014-09-30 | 2021-05-13 | 삼성전자주식회사 | 메모리 장치, 메모리 시스템 및 메모리 장치에 대한 제어 방법 |
US10025685B2 (en) * | 2015-03-27 | 2018-07-17 | Intel Corporation | Impedance compensation based on detecting sensor data |
US10261697B2 (en) * | 2015-06-08 | 2019-04-16 | Samsung Electronics Co., Ltd. | Storage device and operating method of storage device |
KR20170061418A (ko) * | 2015-11-26 | 2017-06-05 | 삼성전자주식회사 | 스트레스 인가 모드를 갖는 캘리브레이션 회로 및 이를 포함하는 메모리 장치 |
JP6640677B2 (ja) * | 2016-08-19 | 2020-02-05 | キオクシア株式会社 | 半導体記憶装置 |
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2016
- 2016-08-19 JP JP2016161061A patent/JP6640677B2/ja active Active
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2017
- 2017-02-14 TW TW106104801A patent/TWI653641B/zh active
- 2017-02-26 US US15/442,684 patent/US10121549B2/en active Active
- 2017-03-08 CN CN201710134239.1A patent/CN107767894B/zh active Active
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2018
- 2018-09-27 US US16/144,597 patent/US10418112B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103811059A (zh) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | 一种非挥发存储器参考校准电路与方法 |
CN104916315A (zh) * | 2014-03-14 | 2015-09-16 | 株式会社东芝 | 半导体存储装置 |
Non-Patent Citations (1)
Title |
---|
A Heterogeneous Dual DLL and Quantization error minimized ZQ calibration for 30nm 1.2V 4Gb 3.2Gb/s/pin DDR4 SDRAM;Taesik Na;《2013 Symposium on VLSI Circuits》;20130816;全文 * |
Also Published As
Publication number | Publication date |
---|---|
JP2018028957A (ja) | 2018-02-22 |
US10418112B2 (en) | 2019-09-17 |
TWI653641B (zh) | 2019-03-11 |
JP6640677B2 (ja) | 2020-02-05 |
US20190027223A1 (en) | 2019-01-24 |
US20180053556A1 (en) | 2018-02-22 |
US10121549B2 (en) | 2018-11-06 |
CN107767894A (zh) | 2018-03-06 |
TW201807705A (zh) | 2018-03-01 |
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Address after: Tokyo Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo Patentee before: Pangea Co.,Ltd. Address after: Tokyo Patentee after: Kaixia Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |
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Effective date of registration: 20220127 Address after: Tokyo Patentee after: Pangea Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |