CN107431085B - 具有沟槽栅的iii族氮化物晶体管 - Google Patents

具有沟槽栅的iii族氮化物晶体管 Download PDF

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CN107431085B
CN107431085B CN201680011424.5A CN201680011424A CN107431085B CN 107431085 B CN107431085 B CN 107431085B CN 201680011424 A CN201680011424 A CN 201680011424A CN 107431085 B CN107431085 B CN 107431085B
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储荣明
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Abstract

一种晶体管，包括III族氮化物半导体层的叠层，所述叠层具有正面和背面，源极与所述叠层的正面接触，漏极与所述叠层的背面接触，沟槽贯穿所述叠层的一部分，所述沟槽具有侧壁，栅极结构在所述沟槽中形成，包括在所述沟槽的侧壁上形成的AlN层，绝缘覆盖层在所述AlN层上形成，以及栅电极在所述绝缘覆盖层上形成并且覆盖所述沟槽的侧壁。

Description

具有沟槽栅的III族氮化物晶体管
相关申请的交叉引用
本申请与2015年4月14日提交的美国临时专利申请No.62/147,325相关并要求其优先权，在此将该临时申请的全文并入作为参考。
技术领域
现有技术涉及用于高效率电源开关的晶体管以及常关操作。
相关技术的讨论
高性能电源开关装置对于高能效电源转换是至关重要的。这种装置使得电源开关产品可以在飞机和汽车的电子系统中使用。
高性能电源开关要求低导通电阻和常关操作。对于III族氮化物晶体管，其具有低导通电阻和常关操作之间的折衷。低沟道电阻通常通过制造其中的电子以高迁移率传输的AlGaN/GaN异质结实现。然而，在AlGaN/GaN异质结中发生的电子积累导致常开操作。
这种晶体管的先前示例使用具有在侧壁上再生长的AlGaN层的沟槽栅结构以产生高迁移率沟道。这样的设计以低导通电阻工作；然而，它也工作在常开模式，其会导致在一些应用中的不安全操作。
具有在侧壁上再生长的AlGaN层的沟槽栅以产生高迁移率沟道被Okada等发表在2010年应用物理快报上的“Novel Vertical Heterojunction Field-Effect Transistorwith Re-grown AlGaN/GaN Two-Dimensional Electron Gas Channels on GaNSubstrates”描述。虽然这种方法具有低导通电阻的优点，但具有在常开模式工作的缺点。
能够提供低导通电阻和在常关模式工作的改进的高性能电源开关是令人期望的。
发明内容
本公开描述一种III族氮化物晶体管，用于具有高电流密度、低导通电阻以及与表现出低沟道电阻的高电子迁移率沟道兼容的常关栅极的高效率电源开关晶体管。
在本文公开的第一个实施例中，晶体管包括III族氮化物半导体层的叠层，叠层具有正面和背面，源极与叠层的正面接触，漏极与叠层的背面接触，沟槽贯穿叠层的一部分，沟槽具有侧壁，在沟槽中形成栅极结构，包含在沟槽的侧壁上形成AlN(氮化铝)层，绝缘覆盖层在AlN层上形成，以及栅电极在绝缘覆盖层上形成并且覆盖沟槽的侧壁。
在本文公开的另一个实施例中，一种制造晶体管的方法，其包括形成III族氮化物半导体层的叠层，叠层具有正面和背面，在叠层的正面形成源极，在叠层的背面形成漏极，形成贯穿叠层的一部分的沟槽，沟槽具有侧壁，在沟槽中形成栅极结构，包含在沟槽的侧壁上形成AlN层，在AlN层上形成绝缘覆盖层，以及在绝缘覆盖层上形成栅电极并且覆盖沟槽的侧壁。
在本文公开的另一个实施例中，晶体管包括源极、漏极、包含n+GaN(氮化镓)的漏极接触层(漏极接触层与漏极接触)、在漏极接触层上的n-GaN的沟道层、在沟道层上的AlGaN(铝镓氮)或GaN的p-层；以及在p-层上的n+GaN的源极接触层(源极接触层与源极接触)、贯穿源极接触层和p-层的沟槽；以及在沟槽中形成的栅极结构，包括在沟槽的侧壁上形成的AlN层、在AlN层上形成的绝缘覆盖层以及在绝缘覆盖层上形成的栅电极并且覆盖沟槽的侧壁。
本发明的目的、优势和新颖特征部分地通过下面的描述得到阐述。在附图和说明书中，附图标记表示各种特征，其中相同附图标记表示相同特征。
附图说明
图1是根据本技术原理的GaN垂直晶体管的横截面视图；
图2是根据本技术原理的GaN垂直晶体管的更详细的横截面视图；
图3A、3B、3C、3D、3E、3F以及3G示出与本技术原理一致的制造如图2中所示的GaN垂直晶体管的制造图。
具体实施方式
下面将详细说明本发明的多个具体实施方式。但是本领域普通技术人员可以理解，本发明的实施并不需要全部具体细节。在其他情况下，出于简洁的目的，说明书对已知特征并未描述。
图1是根据本技术原理的GaN垂直晶体管的横截面视图。如图1中所示的晶体管100，至少具有在装置150的上表面上的一个源极102和栅电极130。漏极112在装置150的底面上。III族氮化物半导体层在源极102与漏极112之间制造。III族氮化物半导体层包括(从图1的底部到顶部)：重掺杂n+型GaN漏极接触层110、轻掺杂n-型GaN漂移或沟道层108、高掺杂p-型GaN或者AlGaN基极层106以及高掺杂n+型GaN源极接触层104。
栅极结构包括在沟槽的侧壁上制造的具有以下层的沟槽：AlN层127和绝缘覆盖层128。在一个实施例中，绝缘覆盖层在AlN层之上形成，AlN层本身在沟槽的侧壁上形成。栅电极130在绝缘覆盖层128上形成，并且至少覆盖在沟槽的侧壁上的绝缘覆盖层128。
图2是根据本技术原理的GaN垂直晶体管200的替代实施例。在图2中，与图1中相同的构件用相同的附图标记表示，并且在下面不会详细描述。如图2中所示的晶体管200，包括在装置150的上表面上的源极102和栅电极130、在装置150的底面上的漏极112以及如上参考图1的层104、106、108以及110。
在图2中，栅极结构包含在沟槽的侧壁上制备的具有以下层的沟槽：GaN沟道层224、单晶AlN层225、多晶AlN层226以及绝缘覆盖层128。栅电极130在绝缘覆盖层128之上形成，并且至少覆盖沟槽的侧壁。GaN沟道层224与沟道层108连续，层224在沟槽的侧壁上形成并且可以与源极102接触。单晶AlN层225在层224之上，并且多晶AlN层226在层225之上。绝缘覆盖层128在多晶AlN层226之上。栅电极130在绝缘覆盖层128上形成并且至少覆盖在沟槽的侧壁上的绝缘覆盖层128。
下面描述制造图1或图2的装置的方法。与图1和图2中相同的构件用相同的附图标记表示，并且在下面不会详细描述。轻掺杂n-GaN漂移层108首先通过金属有机物化学气相沉淀(MOCVD)或分子束外延(MBE)在高掺杂n+GaN漏极接触层110上生长。n-型GaN漂移或者沟道层108的掺杂物通常可以是Si、O、Ge或者它们的组合。高掺杂n+GaN漏极接触层110通常具有大于1017cm-3并且小于1021cm-3的掺杂浓度。漂移层108具有通常在1015cm-3到1017cm-3范围内的掺杂浓度。漂移层108具有通常在0.5μm到50μm范围内的厚度。p-型GaN基极层106通过MOCVD或者MBE在漂移层108之上生长。p-型GaN 106层的掺杂物可以是Mg，并且掺杂浓度可以在1017cm-3到1020cm-3之间。p-型GaN基极层106的厚度通常在0.1μm到10μm的范围内。高掺杂n+源极层104通过MOCVD或者MBE在p-型GaN基极层106之上生长。n+GaN源极层104的掺杂物通常可以是Si、O、Ge或者它们的组合，并且通常具有大于1017cm-3并且小于1021cm-3的掺杂浓度。n+GaN源极层104的厚度通常在0.01μm到1μm的范围内。
栅极沟槽302在源极102之间的GaN层的叠层中形成，沟槽的底部贯穿p-型GaN基极层106并且停在n-GaN漂移层108的里面。栅极沟槽302通常通过电感耦合的等离子体刻蚀形成，具有基于Cl的化学物质。栅极沟槽的宽度通常在0.5μm到5μm的范围内。
为了形成图1的装置，栅极介质叠层然后在栅极沟槽的侧壁上形成。如图1中所示，栅极介质叠层的一个示例是AlN 127的双层和SiN的绝缘覆盖层128。AlN层127可以通常通过MOCVD生长，其厚度范围从1nm到100nm。SiN覆盖层128通常通过MOCVD或者低压化学气相沉淀(LPCVD)生长，其厚度范围从1nm到100nm。源极开口然后可以通过图案化和刻蚀或者其他已知方法穿过栅极介质叠层形成，停在n+GaN源极层104之上或者里面。源极102然后可以在源极开口上形成。栅电极130可以在沟槽的侧壁上的SiN覆盖层128上的栅极沟槽内形成。漏极112在装置的背面上的高掺杂n+GaN层110上形成。
图3A到3G是图2中示出的GaN垂直晶体管200的制造图。在图3A中，使用如上所述的III族氮化物半导体层104、106、108和110制造基底150，并且源极102和漏极112分别在装置150的正面和背面上形成。在图3B中，沟槽302通过刻蚀从源极接触层104的表面、穿过基极层106并停止在漂移或沟道层108中形成。在图3C中，薄GaN沟道层224(通常具有大约1到10nm的厚度)通过金属有机物化学气相沉淀(MOCVD)或分子束外延(MBE)在沟槽302的侧壁上再生长。GaN沟道层224也与漂移或沟道层108接触。在图3D中，在GaN沟道层224的再生长之后，非常薄的单晶AlN层225(通常具有大约0.5到2nm的厚度)通过MOCVD或MBE在GaN沟道层224之上再生长，其在沟道层108和单晶AlN层225之间的界面形成高迁移率(低阻抗)沟道。在图3E中，在单晶AlN层225的再生长之后，多晶AlN层226(通常为大约5到50nm厚)通过MOCVD或者MBE在单晶AlN层225之上生长，以将表面/界面形态与沟道分开。单晶AlN层和多晶AlN层可以在600°到1000°之间的温度通过MOCVD生长。在图3F中，在多晶AlN层226的再生长之后，例如为SiN或Al2O3的绝缘覆盖层128在多晶AlN层226之上形成，以防止泄露电流。在图3G中，栅电极130在绝缘覆盖层128上形成，通常填满沟槽。
在操作中，当足够大的正偏压施加在栅电极和源极之间时，高迁移率(低阻抗)电子沟道在栅极介质叠层和刻蚀的半导体沟槽的侧壁之间的界面上形成。沟道提供源极和漏极之间的电流通路。因为绝缘覆盖层放置在栅极介质层里，所以可以施加大的栅极-源极偏压而不会导致过量的栅极泄漏电流。大的栅极-源极偏压是期望的，因为可以减小开关时间并且可以容纳更高的阈值电压。AlN层提供与半导体的高质量界面，其需要高电子迁移率和最小的俘获效应。
当栅极-源极偏压为0或者为负时，在沟道108中不存在迁移的电子。高阻率沟道切断电流通路，在源极和漏极之间支持一定的压降。
根据本技术原理的晶体管展示高效率电源开关，并且尤其是高电流密度、低导通电阻、与表现出低沟道电阻的高电子迁移率沟道兼容的常关栅极。
更具体来说，根据本技术原理的III族氮化物晶体管在高效率电源开关应用中是有用的。在附图和以上描述中示出的垂直装置结构提供高电流密度和低导通电阻。该晶体管提供的常关栅极用于安全操作。进一步地，常关栅极结构与高电子迁移率沟道兼容，用于实现低沟道电阻。
已经根据专利法律的要求描述了本发明，本领域技术人员将理解如何对本发明做出修改和改动来满足他们的具体要求或条件。此类的修改和改动可以在不偏离如这里所公开的本发明的范围和精神的情况下做出。
已经提供示例性和优选的实施方式的上述具体描述，以便根据法律的要求来说明和公开。其意图并不是穷举性的，并且也不将本发明限于所描述的精确形式，而是仅仅使得本领域的技术人员能够理解本发明如何能够适于特定的使用或实现。修改和变动的可能性对于本领域的从业者来说是明显的。示例性实施方式的描述并不打算进行任何限制，该限制可以包括容差、特征尺寸、具体操作条件、工程规范或类似等，并且也可以在实现之间变化或具有对于现有技术的变化，并且没有从其暗示任何的限制。申请人已经关于当前的现有技术做出公开，并且也设想演进并且未来中的适配可以考虑那些演进，即根据那时的现有技术。意图在于本发明的范围由书面的权利要求和适用的等同方案来定义。对单数的权利要求元素的引用并不旨在指“一个并且仅一个”除非如此明确地陈述。另外，本公开中没有元素、组件、方法或处理步骤旨在是专用于公共，无论元素、组件、或步骤是否明确地在权利要求书中描述。这里也没有权利要求元素将在35U.S.C.Sec。112，第6款下被解释，除非元件明确使用措词“用于…的装置”来描述，并且这里也没有方法或处理步骤将被在那些条款下解释，除非步骤或多个步骤使用措词“包括以下步骤…”来明确地描述。
概念
至少已经公开了下面的概念。
概念1.一种晶体管，包括：
III族氮化物半导体层的叠层，所述叠层具有正面和背面；
源极，其与所述叠层的正面接触；
漏极，其与所述叠层的背面接触；
沟槽，其贯穿所述叠层的一部分，所述沟槽具有侧壁；以及
栅极结构，其在所述沟槽中形成，包括：
AlN层，其在所述沟槽的侧壁上形成；
绝缘覆盖层，其在所述AlN层上形成；以及
栅极，其在所述绝缘覆盖层上形成并且覆盖所述沟槽的侧壁。
概念2.根据概念1所述的晶体管，其中III族氮化物半导体层的所述叠层包括：
漏极接触层，其在所述背面包括n+GaN，所述漏极接触层与所述漏极接触；
n-GaN的沟道层，其在所述漏极接触层上；
AlGaN或GaN的p-层，其在所述沟道层上；以及
n+GaN的源极接触层，其在所述p-层上，所述源极接触层与所述源极接触；
其中所述沟槽贯穿所述源极接触层和所述p-层。
概念3.根据概念1或2所述的晶体管，其中所述AlN层包括：
单晶AlN层，其在所述沟槽的侧壁上形成；以及
多晶AlN层，其在所述单晶AlN层上形成。
概念4.根据概念3所述的晶体管，其中所述单晶AlN层的厚度范围大约从0.5nm到2nm；以及
其中所述多晶AlN层的厚度范围大约从5nm到50nm。
概念5.根据概念3所述的晶体管，其中所述单晶AlN层通过MOCVD或者MBE生长。
概念6.根据概念3所述的晶体管，其中所述多晶AlN层通过MOCVD或者MBE生长。
概念7.根据概念3所述的晶体管，
其中所述单晶AlN层在600°到1000°之间的温度通过MOCVD生长；
其中所述多晶AlN层在600°到1000°之间的温度通过MOCVD生长。
概念8.根据概念1或2所述的晶体管，进一步包括：
第二GaN沟道层，其在所述AlN层和所述沟槽的侧壁之间；
其中所述第二GaN沟道层与所述沟道层接触。
概念9.根据概念8所述的晶体管，其中所述第二GaN沟道层的厚度范围大约从1nm到10nm。
概念10.根据概念8所述的晶体管，其中所述第二GaN沟道层通过MOCVD或者MBE生长。
概念11.一种制造晶体管的方法，包括：
形成III族氮化物半导体层的叠层，所述叠层具有正面和背面；
在所述叠层的正面形成源极；
在所述叠层的背面形成漏极；
形成贯穿所述叠层的一部分的沟槽，所述沟槽具有侧壁；以及
在所述沟槽中形成栅极结构，包括：
在所述沟槽的侧壁上形成AlN层；
在所述AlN层上形成绝缘覆盖层；以及
在所述绝缘覆盖层上形成栅极并且覆盖所述沟槽的侧壁。
概念12.根据概念11所述的方法，其中形成III族氮化物半导体层的所述叠层包括：
在所述背面上形成包括n+GaN的漏极接触层；
在所述漏极接触层上形成n-GaN的沟道层；
在所述沟道层上形成AlGaN或GaN的p-层；以及
在p-层上形成n+GaN的源极接触层，所述源极接触层与所述源极接触；
其中形成所述沟槽，其贯穿所述叠层的一部分，包括形成贯穿所述源极接触层和所述p-层的所述沟槽。
概念13.根据概念11或12所述的方法，其中形成所述AlN层包括：
在所述沟槽的侧壁上形成单晶AlN层；以及
在所述单晶AlN层上形成多晶AlN层。
概念14.根据概念13所述的方法，
其中所述单晶AlN层的厚度范围大约从0.5nm到2nm；以及
其中所述多晶AlN层的厚度范围大约从5nm到50nm。
概念15.根据概念13所述的方法，其中所述单晶AlN层通过MOCVD或者MBE生长。
概念16.根据概念13所述的方法，其中所述多晶AlN层通过MOCVD或者MBE生长。
概念17.根据概念13所述的方法，
其中所述单晶AlN层在600°到1000°之间的温度通过MOCVD生长；
其中所述多晶AlN层在600°到1000°之间的温度通过MOCVD生长。
概念18.根据概念11或12所述的方法，进一步包括：
在所述AlN层和所述沟道的侧壁之间形成第二GaN沟道层；
其中所述第二GaN沟道层与所述沟道层接触。
概念19.根据概念18所述的方法，其中所述第二GaN沟道层的厚度范围大约从1nm到10nm。
概念20.根据概念18所述的方法，其中所述第二GaN沟道层通过MOCVD或者MBE生长。
概念21.一种晶体管，包括：
源极；
漏极；
漏极接触层，其包括n+GaN，所述漏极接触层与所述漏极接触；
n-GaN的沟道层，其在所述漏极接触层上；
AlGaN或GaN的p-层，其在沟道层上；以及
n+GaN的源极接触层，其在p-层上，所述源极接触层与所述源极接触；
沟槽，其贯穿所述源极接触层和所述p-层；以及
栅极结构，其在所述沟槽中形成，包括：
AlN层，其在所述沟槽的侧壁上形成；
绝缘覆盖层，其在所述AlN层上形成；以及
栅极，其在所述绝缘覆盖层上形成并且覆盖所述沟槽的侧壁。
概念22.根据概念21所述的晶体管，其中所述AlN层包括：
单晶AlN层，其在所述沟槽的侧壁上形成；以及
多晶AlN层，其在所述单晶AlN层上形成。
概念23.根据概念22所述的晶体管，进一步包括：
第二GaN沟道层，其在所述AlN层和所述沟槽的侧壁之间；
其中所述第二GaN沟道层与所述沟道层接触。
概念24.根据概念23所述的晶体管，
其中所述单晶AlN层的厚度范围大约从0.5nm到2nm；
其中所述多晶AlN层的厚度范围大约从5nm到50nm；以及
其中所述第二GaN沟道层的厚度范围大约从1nm到10nm。
概念25.根据概念21所述的晶体管，
其中所述n+GaN漏极接触层具有大于1017cm-3并且小于1021cm-3的掺杂浓度；
其中所述沟道层具有通常在1015cm-3到1017cm-3范围内的掺杂浓度；
其中所述p-型GaN层具有在1017cm-3到1020cm-3之间的掺杂浓度；以及
其中所述n+GaN源极层具有大于1017cm-3并且小于1021cm-3的掺杂浓度。
概念26.根据概念21或25所述的晶体管，
其中所述沟道层具有在0.5μm到50μm范围内的厚度；
其中所述p-型GaN层具有在0.1μm到10μm范围内的厚度；
其中所述n+GaN源极层具有在0.01μm到1μm范围内的厚度。

Claims (26)

1.一种晶体管，包括：
漏极；
漏极接触层，其与所述漏极接触；
在所述漏极接触层上的沟道层；
AlGaN或GaN的p-层，其在所述沟道层上；
n+GaN的源极接触层，所述源极接触层与所述p-层接触；
源极，其与所述源极接触层接触，其中仅n+GaN的源极接触层在所述源极和p-层之间；
沟槽，其贯穿所述源极接触层和p-层，其中所述沟槽具有垂直的侧壁；以及
栅极结构，其在所述沟槽中形成，包括：
AlN层，其在所述沟槽的侧壁上形成；
绝缘覆盖层，其在所述AlN层上形成；以及
栅极，其在所述绝缘覆盖层上形成；
其中所述AlN层的底部并不延伸到所述p-层的底部下方。
2.根据权利要求1所述的晶体管，其中漏极接触层包括n+GaN并且所述沟道层包括n-GaN。
3.根据权利要求1所述的晶体管，其中所述AlN层包括：
单晶AlN层，其在所述沟槽的侧壁上形成；以及
多晶AlN层，其在所述单晶AlN层上形成。
4.根据权利要求3所述的晶体管，其中所述单晶AlN层的厚度范围从0.5nm到2nm；以及
其中所述多晶AlN层的厚度范围从5nm到50nm。
5.根据权利要求3所述的晶体管，其中所述单晶AlN层通过MOCVD或者MBE生长。
6.根据权利要求3所述的晶体管，其中所述多晶AlN层通过MOCVD或者MBE生长。
7.根据权利要求3所述的晶体管，
其中所述单晶AlN层在600°到1000°之间的温度通过MOCVD生长；
其中所述多晶AlN层在600°到1000°之间的温度通过MOCVD生长。
8.根据权利要求1所述的晶体管，进一步包括：
第二GaN沟道层，其在所述AlN层和所述沟槽的侧壁之间；
其中所述第二GaN沟道层与所述沟道层接触。
9.根据权利要求8所述的晶体管，其中所述第二GaN沟道层的厚度范围从1nm到10nm。
10.根据权利要求8所述的晶体管，其中所述第二GaN沟道层通过MOCVD或者MBE生长。
11.一种制造晶体管的方法，包括：
形成漏极接触层；
在所述漏极接触层上形成沟道层；
在所述沟道层上形成AlGaN或GaN的p-层；
形成与所述p-层接触的源极接触层；
形成与所述源极接触层接触的源极，其中仅n+GaN的源极接触层在所述源极和p-层之间；
在所述漏极接触层上形成漏极；
形成贯穿所述源极接触层和所述p-层的沟槽，其中所述沟槽具有垂直的侧壁；以及
在所述沟槽中形成栅极结构，包括：
在所述沟槽的侧壁上形成AlN层；
在所述AlN层上形成绝缘覆盖层；以及
在所述绝缘覆盖层上形成栅极；
其中所述AlN层的底部并不延伸到所述p-层的底部下方。
12.根据权利要求11所述的方法，其中所述漏极接触层包括n+GaN并且所述沟道层包括n-GaN。
13.根据权利要求11所述的方法，其中形成所述AlN层包括：
在所述沟槽的侧壁上形成单晶AlN层；以及
在所述单晶AlN层上形成多晶AlN层。
14.根据权利要求13所述的方法，
其中所述单晶AlN层的厚度范围从0.5nm到2nm；以及
其中所述多晶AlN层的厚度范围从5nm到50nm。
15.根据权利要求13所述的方法，其中所述单晶AlN层通过MOCVD或者MBE生长。
16.根据权利要求13所述的方法，其中所述多晶AlN层通过MOCVD或者MBE生长。
17.根据权利要求13所述的方法，
其中所述单晶AlN层在600°到1000°之间的温度通过MOCVD生长；
其中所述多晶AlN层在600°到1000°之间的温度通过MOCVD生长。
18.根据权利要求11所述的方法，进一步包括：
在所述AlN层和所述沟道的侧壁之间形成第二GaN沟道层；
其中所述第二GaN沟道层与所述沟道层接触。
19.根据权利要求18所述的方法，其中所述第二GaN沟道层的厚度范围从1nm到10nm。
20.根据权利要求18所述的方法，其中所述第二GaN沟道层通过MOCVD或者MBE生长。
21.一种晶体管，包括：
源极；
漏极；
漏极接触层，其包括n+GaN，所述漏极接触层与所述漏极接触；
n-GaN的沟道层，其在所述漏极接触层上；
AlGaN或GaN的p-层，其在沟道层上；以及
n+GaN的源极接触层，其在p-层上并且与p-层接触，并且所述源极接触层与所述源极接触，其中仅n+GaN的源极接触层在所述源极和p-层之间；
沟槽，其贯穿所述源极接触层和所述p-层，其中所述沟槽具有垂直的侧壁；以及
栅极结构，其在所述沟槽中形成，包括：
AlN层，其在所述沟槽的侧壁上形成；
绝缘覆盖层，其在所述AlN层上形成；以及
栅极，其在所述绝缘覆盖层上形成；
其中所述AlN层的底部并不延伸到所述p-层的底部下方。
22.根据权利要求21所述的晶体管，其中所述AlN层包括：
单晶AlN层，其在所述沟槽的侧壁上形成；以及
多晶AlN层，其在所述单晶AlN层上形成。
23.根据权利要求22所述的晶体管，进一步包括：
第二GaN沟道层，其在所述AlN层和所述沟槽的侧壁之间；
其中所述第二GaN沟道层与所述沟道层接触。
24.根据权利要求23所述的晶体管，
其中所述单晶AlN层的厚度范围从0.5nm到2nm；
其中所述多晶AlN层的厚度范围从5nm到50nm；以及
其中所述第二GaN沟道层的厚度范围从1nm到10nm。
25.根据权利要求22所述的晶体管，
其中所述n+GaN漏极接触层具有大于1017cm-3并且小于1021cm-3的掺杂浓度；
其中所述沟道层具有通常在1015cm-3到1017cm-3范围内的掺杂浓度；
其中所述p-型GaN层具有在1017cm-3到1020cm-3之间的掺杂浓度；以及
其中所述n+GaN的源极接触层具有大于1017cm-3并且小于1021cm-3的掺杂浓度。
26.根据权利要求25所述的晶体管，
其中所述沟道层具有在0.5μm到50μm范围内的厚度；
其中所述p-型GaN层具有在0.1μm到10μm范围内的厚度；
其中所述n+GaN的源极接触层具有在0.01μm到1μm范围内的厚度。
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