WO2012169019A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2012169019A1 WO2012169019A1 PCT/JP2011/063095 JP2011063095W WO2012169019A1 WO 2012169019 A1 WO2012169019 A1 WO 2012169019A1 JP 2011063095 W JP2011063095 W JP 2011063095W WO 2012169019 A1 WO2012169019 A1 WO 2012169019A1
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Definitions
- the present invention relates to a vertical semiconductor device that is used for high-power switching and has a low on-resistance and excellent withstand voltage performance, and a method for manufacturing the same.
- a high current switching element is required to have a high reverse breakdown voltage and a low on-resistance.
- a field effect transistor (FET: Field Effect Transistor) using a group III nitride semiconductor is excellent in terms of high breakdown voltage, high temperature operation and the like because of its large band gap.
- FET Field Effect Transistor
- vertical transistors using GaN-based semiconductors are attracting attention as high-power control transistors.
- mobility is provided by providing an opening in a GaN-based semiconductor and providing a regrowth layer including a channel of a two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) on a side surface of the opening.
- 2DEG 2 Dimensional Electron Gas
- a p-type GaN layer that acts as a guard ring is inserted around the opening where the regrowth layer is provided. For this reason, since it becomes an npn structure, obtaining the high mobility by the two-dimensional electron gas which forms a channel, it can ensure the pressure
- the semiconductor device of the present invention is formed in a GaN-based stack including an n-type drift layer, a p-type layer located on the n-type drift layer, and an n-type surface layer located on the p-type layer. .
- an opening that reaches the n-type drift layer from the n-type surface layer through the p-type layer is provided in the GaN-based stack, and a channel that is positioned so as to cover the GaN-based stack exposed in the opening is provided.
- Including a regrowth layer is a two-dimensional electron gas that includes an electron transit layer and an electron supply layer, and a channel is formed at the interface between the electron transit layer and the electron supply layer.
- the thickness of the p-type layer is in the range of d to 10d, where d is the thickness of the electron transit layer, and the p-type layer enters the n-type surface layer from the (p-type layer / n-type surface layer) interface.
- a p-type impurity gradient layer having a concentration reduced from the p-type impurity concentration in the layer is provided.
- the p-type layer is in the range of the thickness d to 10d, the length of the channel can be suppressed and the on-resistance can be suppressed while ensuring sufficient breakdown voltage performance.
- the p-type impurity gradient layer can contribute to the improvement of the breakdown voltage performance. For this reason, the pressure resistance can be secured even with the p-type layer alone, but a margin or safety margin can be obtained for the pressure resistance.
- the p-type impurity gradient layer is formed so as to enter the n-type surface layer, it does not directly increase the on-resistance or hardly affects the on-resistance.
- the p-type layer when the p-type layer is set thin in order to reduce the on-resistance, leakage tends to occur from the n-type surface layer to the n-type drift layer via the electron transit layer (usually the i-type GaN layer).
- the electron transit layer usually the i-type GaN layer.
- the p-type impurity gradient layer enters the n-type surface layer, the n-type surface layer substantially occupies a position retracted from the p-type layer, or the p-type layer substantially increases, and the electron Leakage while detouring to the traveling layer can be suppressed.
- the thickness of the p-type layer if the thickness of the p-type layer is less than d, the withstand voltage performance cannot be ensured, and the leakage current increases.
- the thickness of the p-type layer exceeds 10d, the length of the channel along the slope of the opening exceeds 10d, and an increase in on-resistance cannot be ignored.
- the side effects caused by it can be eliminated by the arrangement of the p-type impurity gradient layer.
- there are almost no side effects and both performance improvement by thinning the p-type layer and performance improvement by the p-type impurity gradient layer can be obtained.
- the n-type surface layer it is assumed that there is no penetration of the p-type impurity gradient layer at least in the thickness portion close to the surface. That is, in the p-type impurity gradient layer, the p-type impurity concentration is lowered to the background level at least at a portion near the surface of the n-type surface layer.
- the above GaN-based laminate is epitaxially grown on a predetermined crystal plane of GaN.
- the underlying GaN may be a GaN substrate or a GaN film on a support substrate. Furthermore, it is formed on a GaN substrate or the like during the growth of the GaN-based laminate, and in the subsequent process, except for a predetermined thickness portion such as the GaN substrate, only a thin GaN layer base remains in the product state. There may be.
- the thin underlying GaN layer may be conductive or non-conductive, and the drain electrode can be provided on the front or back surface of the thin GaN layer, depending on the manufacturing process and the structure of the product.
- the supporting base or the substrate may be conductive or non-conductive.
- the drain electrode can be directly provided on the back surface (lower) or front surface (upper) of the supporting base or substrate.
- a drain electrode can be provided on the non-conductive substrate and on the conductive layer located on the lower layer side in the semiconductor layer.
- the p-type impurity gradient layer can be formed in the thickness range of 0.5d to 3.5d from the (p-type layer / n-type surface layer) interface into the n-type surface layer. As a result, it is possible to contribute to improvement of withstand voltage performance and suppression of the leakage current. In addition, the on-resistance can be hardly affected. When the thickness of the p-type impurity gradient layer is less than 0.5d, the improvement of the breakdown voltage performance and the leakage current is limited, and many cannot be expected. On the other hand, if it exceeds 3.5d, the on-resistance is affected.
- the p-type impurity concentration gradient in the p-type impurity gradient layer can be in the range of 30 nm / decade to 300 nm / decade.
- concentration gradient of the p-type impurity is less than 30 nm / decade, it becomes close to a steep interface, and it is difficult to obtain the above-described improvement of the withstand voltage performance and the suppression of leakage current only by locally affecting a very thin range.
- the gradient exceeds 300 nm / decade, there is no great difference from the increase in the thickness of the p-type layer, and the risk of increasing the on-resistance increases.
- nm / decade which is a unit of concentration gradient, is a film thickness necessary for reducing the impurity concentration by one digit.
- the thickness d of the electron transit layer can be in the range of 20 nm to 400 nm. As a result, it becomes easy to obtain an effect such as suppression of leakage current by the arrangement of the p-type layer and the p-type impurity gradient layer. If the thickness is less than 20 nm, the on-resistance increases due to the influence of Mg diffusion from the p-type layer to the electron transit layer, and if the thickness exceeds 400 nm, the n-type surface layer passes through the electron transit layer to the n-type drift layer. Leakage is likely to occur.
- the n-type impurity concentration of the n-type surface layer can be in the range of ⁇ 25% to + 25% based on the p-type impurity concentration of the p-type layer.
- the n-type impurity concentration in the n-type surface layer and the p-type impurity concentration in the p-type layer are substantially the same, and the p-type impurity gradient layer has almost no impurities offset on the n-type surface layer side from the interface.
- a layer portion without carrier is formed. As a result, it is possible to improve both the breakdown voltage performance and the suppression of leakage current.
- the semiconductor device manufacturing method of the present invention uses a GaN-based laminate.
- an n-type drift layer, a p-type layer positioned on the n-type drift layer, an n-type surface layer on the p-type layer, and an n-type surface layer through a p-type layer a step of providing an opening reaching the n-type drift layer; and a step of forming an electron transit layer and an electron supply layer in the opening.
- the thickness of the electron transit layer is d and the thickness of the p-type layer is any of d to 10d.
- a p-type impurity gradient layer whose concentration decreases from the p-type impurity concentration in the p-type layer is formed from the (p-type layer / n-type surface layer) interface into the n-type surface layer.
- the p-type impurity in the p-type layer is guided to the n-type surface layer, thereby forming the p-type impurity.
- the inclined layer can be easily formed in the n-type surface layer. As a result, it is possible to easily obtain a semiconductor device having low on-resistance, excellent withstand voltage performance and low leakage current characteristics.
- the n-type impurity concentration of the n-type surface layer is within a range of ⁇ 25% to + 25% based on the p-type impurity concentration of the p-type layer.
- the p-type impurity gradient layer can be formed in the thickness range of 0.5d to 3.5d from the (p-type layer / n-type surface layer) interface into the n-type surface layer. As a result, it is possible to obtain a semiconductor device excellent in breakdown voltage performance and low leakage current.
- n-type surface layer In the step of forming the n-type surface layer, doping is performed so as to form a p-type impurity gradient layer, or the growth temperature is set to 1030 ° C. to 1100 so that the p-type impurity in the p-type layer diffuses into the n-type surface layer.
- the n-type surface layer can be grown in the range of ° C.
- the present invention it is possible to obtain a semiconductor device capable of stably securing a low on-resistance while obtaining an excellent longitudinal breakdown voltage.
- FIG. 4 is a cross-sectional view taken along the line II of FIG. 3, showing the vertical GaN-based FET according to the first embodiment of the present invention. It is an enlarged view in the opening part side surface of the semiconductor device of FIG. It is a figure which shows the thickness direction distribution of the p-type impurity in a p-type impurity gradient layer.
- FIG. 2 is a plan view of a chip on which the semiconductor device of FIG. 1 is formed.
- FIG. 2 is a diagram showing a method for manufacturing the vertical GaN-based FET of FIG. 1 and showing a state in which an epitaxial multilayer including a p-type impurity gradient layer is formed on a GaN substrate.
- FIG. 1 is a cross-sectional view showing a semiconductor device 10 according to an embodiment of the present invention.
- - n from (GaN-based substrate 1 / buffer layer 2 / n type drift layer 4 / p-type barrier layer 6 / n + -type contact layer 8) surface of the formed GaN-based semiconductor layer by - -type An opening 28 reaching the drift layer 4 is provided.
- the n + -type contact layer 8 is another name for the n-type surface layer 8 when placing importance on the arrangement of electrodes, and is also referred to as an n + -type cap layer with emphasis on the surface layer of the laminate.
- the p-type barrier layer 6 is another name for the p-type layer 6 when importance is attached to the barrier layer against electrons. Further, the n ⁇ type drift layer 4 becomes an n type drift layer.
- a regrowth layer 27 including an electron transit layer 22 and an electron supply layer 26 is formed so as to cover the GaN-based semiconductor layer exposed in the opening 28.
- a gate electrode G is formed on the regrowth layer 27 with the insulating film 9 interposed.
- a source electrode S is formed on the GaN-based semiconductor layer in contact with the electron transit layer 22 and the electron supply layer 26.
- the source electrode S, the n ⁇ -type drift layer 4 and the like are disposed so as to face the source electrode S.
- a drain electrode D is provided on both sides.
- a two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) is formed at the interface between the electron transit layer 22 and the electron supply layer 26, and this 2DEG constitutes a longitudinal current channel between the source electrode and the drain electrode.
- the point of the semiconductor device 10 of the present embodiment is that (1) the thickness of the p-type barrier layer 6 is in the range of d to 10d, where d is the thickness of the electron transit layer 22, and (2) (p-type barrier Layer 6 / n + -type contact layer 8) A p-type impurity gradient layer 7 whose concentration decreases from the p-type impurity concentration in the p-type barrier layer 6 is formed from the interface into the n + -type contact layer 8. In the point.
- FIG. 2A is an enlarged view of the regrowth layer 27 and (n ⁇ type drift layer / p type barrier layer 6 / n + type contact layer 8) on the side surface of the opening 28 in the semiconductor device 10 shown in FIG. 2A is a cross-sectional view
- FIG. 2B is a diagram showing a p-type impurity concentration distribution in the thickness direction.
- the thickness of the electron transit layer 22 is d.
- the thickness of the p-type barrier layer 6 is preferably in the range of d to 10d with reference to the thickness d of the electron transit layer 22.
- the thickness of the p-type impurity gradient layer 7 is preferably in the range of 0.5d to 3.5d. Referring to FIG.
- the thickness of the p-type impurity gradient layer 7 is determined by paying attention to the type of main p-type impurities that make the p-type barrier layer 6 p-type, for example, Mg (p-type barrier layer 6 / The thickness between the n + -type contact layer 8) boundary and the Mg background concentration in the n + -type contact layer 8 is defined.
- Mg concentration at the boundary of (p-type barrier layer 6 / n + -type contact layer 8) is about 5 ⁇ 10 18 (5E + 18) (cm ⁇ 3 ), which matches the Mg concentration in p-type barrier layer 6. is there.
- the background concentration of Mg in the n + -type contact layer 8 is, for example, about 1 ⁇ 10 16 (1E + 16) (cm ⁇ 3 ). between the surface of the Mg concentration of the p-type impurity gradient layer 7 intersects the background concentration of Mg in the n + -type contact layer 8 (point), and (p-type barrier layer 6 / n + -type contact layer 8) interface Is the thickness of the p-type impurity gradient layer 7.
- the thin p-type barrier layer 6 and the p-type impurity gradient layer 7 By disposing the thin p-type barrier layer 6 and the p-type impurity gradient layer 7, the following action can be obtained.
- the p-type barrier layer 6 Since the p-type barrier layer 6 is in the range of the thickness d to 10d, the channel length can be suppressed to 10d or less and sufficient on-resistance can be suppressed while ensuring sufficient withstand voltage performance.
- the p-type impurity gradient layer 7 can improve the withstand voltage performance as compared with the case where the p-type barrier layer 6 is disposed alone. For this reason, the pressure resistance can be secured even with the p-type layer alone, but a margin or safety margin can be obtained for the pressure resistance.
- the p-type impurity gradient layer is formed so as to enter the n-type surface layer, it does not directly increase the on-resistance or hardly affects the on-resistance.
- the n ⁇ -type drift layer passes from the n + -type contact layer 8 via the electron transit layer (usually the i-type GaN layer) 22. 4 is likely to leak.
- the p-type impurity gradient layer 7 enters into the n + -type contact layer 8
- the n + -type contact layer 8 is virtually the thinned retreated to a position retracted from the p-type barrier layer 6 (the surface side Shape) or the p-type barrier layer 6 substantially increases, and leakage while detouring to the electron transit layer 22 can be suppressed.
- the p-type impurity gradient layer 7 acts resistively on such a leakage current path.
- the p-type impurity gradient layer 7 has the effect of (E1) improving the withstand voltage performance and (E3) suppressing the leakage current while obtaining a decrease in on-resistance by making the p-type layer thinner. To improve.
- the p-type impurity gradient layer 7 has a p-type impurity concentration lowered to a background level (for example, 1 ⁇ 10 16 cm ⁇ 3 ) at least at a portion near the surface of the n + -type contact layer 8. To do.
- a background level for example, 1 ⁇ 10 16 cm ⁇ 3
- FIG. 3 is a plan view of a chip on which the semiconductor device is formed, and shows where the cross-sectional view of FIG. 1 is located in the whole.
- the opening 28 and the gate electrode G are hexagonal, and the periphery is covered with the source electrode S while avoiding the gate wiring 12 and is densely packed (honeycomb structure).
- the gate electrode can have a long peripheral length, that is, the on-resistance can be lowered.
- the current flows through the path of the source electrode S ⁇ the channel in the regrown layer 27 ⁇ the n ⁇ type drift layer 4 ⁇ the drain electrode D.
- the gate electrode G, the gate wiring 12 and the gate pad 13 constitute a gate structure.
- the source wiring is provided on an interlayer insulating film (not shown).
- a via hole is provided in the interlayer insulating film, and the source electrode S including the plug conductive portion is conductively connected to a source conductive layer (not shown) on the interlayer insulating film.
- the source structure including the source electrode S can have a low electric resistance and a high mobility suitable for a high-power element.
- the above hexagonal honeycomb structure can be formed in a bowl shape, and even by arranging the bowl-shaped openings densely, the opening perimeter per area can be increased, and as a result, the current density can be improved. it can.
- a GaN-based stacked body of an n ⁇ -type GaN drift layer 4 / p-type GaN layer 6 / n + -type GaN contact layer 8 is epitaxially grown on the GaN substrate 1 having the above meaning.
- a GaN-based buffer layer may be inserted between the GaN substrate 1 and the n ⁇ -type GaN drift layer 4.
- MOCVD metal organic chemical vapor deposition
- MBE molecular beam epitaxial
- GaN-based semiconductor layer with good crystallinity can be formed.
- trimethylgallium is used as a gallium source.
- High purity ammonia is used as the nitrogen raw material.
- Purified hydrogen is used as the carrier gas.
- the purity of high purity ammonia is 99.999% or more, and the purity of purified hydrogen is 99.999995% or more.
- Hydrogen-based silane is used as the n-type dopant Si raw material, and cyclopentadienyl magnesium is used as the p-type dopant Mg raw material.
- a conductive GaN substrate having a diameter of 2 inches is used as the substrate.
- the n ⁇ -type GaN layer 4 / p-type GaN layer 6 / n + -type GaN layer 8 are grown in this order.
- a method of forming the p-type impurity gradient layer 7 from the (p-type GaN layer 6 / n + -type GaN layer 8) interface into the n + -type GaN layer 8 is as follows. (S1) when switching from the growth of the p-type GaN layer 6 to grow to n + -type GaN layer 8, raising the initial temperature in the growth of the n + -type GaN layer 8, the p-type GaN layer 6 n + The diffusion of p-type impurities such as Mg into the type GaN layer 8 is promoted.
- a p-type dopant for example, cyclopentadienyl magnesium, which is a raw material of Mg, is changed to a p-type in the initial short period of growth of the n + -type GaN layer 8.
- the concentration gradient of the p-type impurity in the p-type impurity gradient layer 7 is preferably 30 nm / decade to 300 nm / decade.
- the concentration gradient of the p-type impurity exceeds 300 nm / decade, there is no great difference from the increase in the thickness of the p-type layer, and the risk of increasing the on-resistance increases. Further, if the concentration gradient is less than 30 nm / decade, it is difficult to obtain the above-described effects of improving the withstand voltage performance and suppressing the leakage current only by locally affecting a very thin range.
- the opening 28 is formed by etching.
- the opening 28 is etched by forming a resist pattern M1 on the surfaces of the epitaxial layers 4, 6 and 8, and then etching the resist pattern M1 by RIE (Reactive Ion Etching). The opening 28 is provided while being retracted.
- the wafer is introduced into an MOCVD apparatus, and as shown in FIG. 4C, an electron transit layer 22 made of undoped GaN and an electron supply layer 26 made of undoped AlGaN. A regrowth layer 27 containing GaN is grown.
- the wafer is taken out of the MOCVD apparatus, and an insulating film 9 is grown as shown in FIG. 7A.
- the source electrode S is formed on the epitaxial layer surface and the drain electrode D is formed on the back surface of the GaN-based substrate 1. Further, the gate electrode G is formed on the side surface of the opening 28.
- the semiconductor device 10 shown in FIG. 7B is manufactured based on the manufacturing method described in the above embodiment, and the p-type impurity gradient layer 7 formed from the p-type barrier layer 6 into the n + -type contact layer 8 is manufactured. Presence (thickness and concentration gradient) was verified.
- Each part of the semiconductor device 10 other than the p-type impurity gradient layer 7 is as follows. Mg was used for the p-type impurity of the p-type GaN barrier layer 6.
- the initial temperature of the formation of the n + -type cap layer 8 is raised to 1050 ° C. based on the method of (M1) described above, and then the Mg + n-type cap layer 8 is formed.
- n ⁇ -type GaN drift layer 4 thickness 5 ⁇ m, Si concentration 1 ⁇ 10 16 (1E16) cm ⁇ 3 p-type GaN barrier layer 6: thickness 0.5 ⁇ m, Mg concentration 1 ⁇ 10 18 (1E18) cm ⁇ 3 n + -type GaN contact layer 8: thickness 0.2 ⁇ m, Si concentration 1 ⁇ 10 18 (1E18) cm ⁇ 3
- Electron traveling layer (undoped GaN) 22 thickness 0.1 ⁇ m
- the undoped AlGaN layer 26 was grown, the supply of the organometallic raw material was stopped and the temperature was lowered in a nitrogen atmosphere. Thereafter, the concentration distribution of Mg in the depth direction was measured by SIMS (Secondary Ion-microprobe Mass Spectrometry) while etching the semiconductor device 10 as a test body in the depth direction from the surface of the n + -type cap layer 8.
- FIG. 8 is a diagram showing the concentration distribution of Mg in the depth direction measured by SIMS.
- the p-type barrier layer 6 has a thickness of 0.5 ⁇ m and a thickness of 5d.
- the thinned p-type layer 6 and p-type impurity graded layer (Mg graded layer) 7 obtain (E1) improved on-resistance and (E2) improved breakdown voltage performance and (E3). It is possible to improve the effect of suppressing leakage current.
- the present invention it is possible to obtain a semiconductor device capable of stably securing a low on-resistance while obtaining an excellent longitudinal breakdown voltage. For this reason, a large current can be controlled with almost no loss.
- GaN substrate 1 GaN substrate, 2 buffer layer, 4 n ⁇ type GaN drift layer, 6 p type GaN layer, 7 p type impurity gradient layer, 8 n + type GaN surface layer, 9 insulating film, 10 vertical type GaNFET, 12 gate wiring, 13 Gate pad, 22 GaN electron transit layer, 26 AlGaN electron supply layer, 27 regrowth layer, 28 opening, M1 resist pattern, D drain electrode, G gate electrode, S source electrode.
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Abstract
Description
p型層の厚みについていえば、p型層の厚みがd未満では、耐圧性能を確保できないし、また上記のリーク電流が増大する。しかし、p型層の厚みが10dを超えると、開口部斜面に沿うチャネルの長さが10dを超えて大きくなり、オン抵抗の増大が無視できなくなる。本発明では、上記のように、p型層の厚みを薄くしながら、それに起因する副作用を、p型不純物傾斜層の配置によって解消することができる。所定の場合には、副作用はほとんどなく、p型層の薄肉化による性能向上と、p型不純物傾斜層による性能向上とをともに得ることができる。
なお、n型表層において、少なくとも表面に近い厚み部分では、p型不純物傾斜層の侵入がないことを前提とする。すなわち、p型不純物傾斜層は、n型表層の少なくとも表面に近い部分では、p型不純物濃度はバックグラウンドレベルに低下しているものとする。
GaN基板または支持基体等が製品に残る場合、当該支持基体または基板は、導電性でも、非導電性でもよい。導電性の場合は、ドレイン電極は、その支持基体または基板の裏面(下)またはおもて面(上)に直接設けることができる。また、非導電性の場合は、非導電性基板の上であって、上記半導体層中の下層側に位置する導電層の上に、ドレイン電極を設けることができる。
なお、濃度勾配の単位であるnm/decadeは、不純物濃度が1桁低減するのに必要な膜厚、である。
開口部28に露出する上記GaN系半導体層を覆うように、電子走行層22および電子供給層26を含む再成長層27が形成されている。再成長層27上には絶縁膜9を介在させてゲート電極Gが形成される。GaN系半導体層上に、電子走行層22および電子供給層26に接してソース電極Sが形成され、このソース電極Sと対面するように、当該ソース電極Sと、n-型ドリフト層4等を挟んで、ドレイン電極Dが設けられている。電子走行層22と電子供給層26との界面に、二次元電子ガス(2DEG:2 Dimensional Electron Gas)が形成され、この2DEGが、ソース電極とドレイン電極との間の縦方向電流のチャネルを構成する。
本実施の形態の半導体装置10のポイントは、(1)p型バリア層6の厚みが、電子走行層22の厚みをdとしてd~10dの範囲にあり、かつ、(2)(p型バリア層6/n+型コンタクト層8)界面から該n+型コンタクト層8内へと、該p型バリア層6におけるp型不純物濃度から濃度が減少するp型不純物傾斜層7が形成されている点にある。
図2Bを参照して、p型不純物傾斜層7の厚みは、p型バリア層6をp型化している主要なp型不純物の種類、たとえばMgに着目して、(p型バリア層6/n+型コンタクト層8)境界から、n+型コンタクト層8におけるMgのバックグランド濃度に至る間の厚みと定義される。たとえば、(p型バリア層6/n+型コンタクト層8)境界における上記Mg濃度は、p型バリア層6におけるMg濃度に一致して、5×1018(5E+18)(cm-3)程度である。また、n+型コンタクト層8におけるMgのバックグランド濃度は、たとえば1×1016(1E+16)(cm-3)程度である。p型不純物傾斜層7のMg濃度がn+型コンタクト層8におけるMgのバックグランド濃度と交差する面(点)と、(p型バリア層6/n+型コンタクト層8)境界面との間の厚みが、当該p型不純物傾斜層7の厚みである。
(E1)p型バリア層6が厚みd~10dの範囲にあるので、十分な耐圧性能を確保しながら、チャネルの長さを10d以下に抑えることができ、オン抵抗を低く抑えることができる。
(E2)上記のp型不純物傾斜層7は、p型バリア層6を単独配置するよりも、耐圧性能を向上させることができる。このため、p型層単独でも耐圧性能を確保することができるが、耐圧性能について余裕代または安全代を得ることができる。また、p型不純物傾斜層は、n型表層内に入り込む形で形成されているので、オン抵抗の増大には直結しないか、またはオン抵抗にほとんど影響しない。
(E3)とくにオン抵抗を減少させるためにp型バリア層6を薄く設定した場合、n+型コンタクト層8から電子走行層(通常、i型GaN層)22を経由してn-型ドリフト層4へとリークが生じやすくなる。しかし、n+型コンタクト層8にp型不純物傾斜層7が入り込むため、n+型コンタクト層8は、実質上、p型バリア層6から後退した位置(表面側へと後退して薄くされた形状)を占めることになり、またはp型バリア層6が実質上増大することになり、電子走行層22へと迂回しながらのリークを抑制することができる。p型不純物傾斜層7がそのようなリーク電流経路に対して抵抗的に作用する。
要は、上記のp型不純物傾斜層7は、p型層を薄くすることで(E1)オン抵抗の減少を得ながら、(E2)耐圧性能の向上および(E3)リーク電流の抑制、する作用を向上させる。
なお、n+型コンタクト層8において、少なくとも表面に近い厚み部分では、p型不純物傾斜層7の侵入がないことを前提とする。すなわち、p型不純物傾斜層7は、n+型コンタクト層8の少なくとも表面に近い部分では、p型不純物濃度はバックグラウンドレベル(たとえば、1×1016cm-3)に低下しているものとする。
上記の六角形のハニカム構造は、畝状にして、畝状の開口部を密に配置することでも、上記の面積当たりの開口部周囲長を大きくでき、この結果、電流密度を向上させることができる。
上記の層の形成は、例えば、MOCVD(有機金属化学気相成長)法を用いる。またはMOCVD法でなくMBE(分子線エピタキシャル)法を用いてもよい。これにより結晶性の良好なGaN系半導体層を形成できる。GaN基板1の形成において、導電性基板上に窒化ガリウム膜をMOCVD法によって成長させる場合、ガリウム原料として、トリメチルガリウムを用いる。窒素原料としては高純度アンモニアを用いる。キャリアガスとしては純化した水素を用いる。高純度アンモニアの純度は99.999%以上、純化水素の純度は99.999995%以上である。n型ドーパントのSi原料には水素ベースのシランを用い、p型ドーパントのMg原料にはシクロペンタジエニルマグネシウムを用いる。基板には直径2インチの導電性GaN基板を用いる。まず、温度1030℃、圧力100Torrで、アンモニアおよび水素の雰囲気中で、基板クリーニングを実施する。その後、基板を1050℃に昇温して、圧力200Torr、窒素原料とガリウム原料の比率であるV/III比=1500で窒化ガリウム層を成長させる。
(S1)p型GaN層6の成長からn+型GaN層8への成長へと切り替える際に、n+型GaN層8の成長における初期の温度を上昇させ、p型GaN層6からn+型GaN層8へのp型不純物たとえばMgの拡散を促進させる。
(S2)n+型GaN層8の成長途中、p型ドーパント、たとえばMgの原料であるシクロペンタジエニルマグネシウムの導入量を、n+型GaN層8の成長の初期の短期間は、p型バリア層6と同等にして、そのあと傾斜的に減少させる。
p型不純物傾斜層7のp型不純物の濃度勾配は、30nm/decade~300nm/decade、とするのがよい。p型不純物の濃度勾配が300nm/decadeを超えると、p型層の厚みが増大するのと大差なくなり、オン抵抗の増大をもたらすリスクが増大する。また濃度勾配が、30nm/decade未満であれば、ごく薄い範囲に局所的な影響を及ぼすだけで、上記の耐圧性能の向上やリーク電流の抑制の作用は得にくい。
次いで、上記ウエハをMOCVD装置から取り出し、図7Aに示すように、絶縁膜9を成長させる。その後、再びフォトリソグラフィとイオンビーム蒸着法を用いて、図7Bに示すように、ソース電極Sをエピタキシャル層表面に、ドレイン電極DをGaN系基板1の裏面に形成する。さらにゲート電極Gを開口部28の側面に形成する。
n-型GaNドリフト層4:厚み5μm、Si濃度1×1016(1E16)cm-3
p型GaNバリア層6:厚み0.5μm、Mg濃度1×1018(1E18)cm-3
n+型GaNコンタクト層8:厚み0.2μm、Si濃度1×1018(1E18)cm-3
電子走行層(アンドープGaN)22:厚み0.1μm
電子供給層(アンドープAlGaN層)26:厚み0.02μm、Al組成25%
図6を参照して、アンドープGaN層22の成長では、950℃において240秒ほどの成長時間をとって厚み0.1μmとした。また、アンドープAlGaN層26の成長では、1080℃にて100秒間ほど成長時間をとって厚み0.02μとした。アンドープAlGaN層26を成長させた後、有機金属原料の供給を停止して、窒素雰囲気で降温した。
その後、試験体である半導体装置10について、n+型キャップ層8の表面から深さ方向にエッチングしながら、SIMS (Secondary Ion-microprobe Mass Spectrometry)によって、Mgの深さ方向濃度分布を測定した。
Claims (8)
- n型ドリフト層、該n型ドリフト層上に位置するp型層、および該p型層上に位置するn型表層、を含むGaN系積層体、に形成された半導体装置であって、
前記GaN系積層体に、前記n型表層から前記p型層を経て前記n型ドリフト層に届く開口部が設けられ、
前記開口部に露出する前記GaN系積層体を覆うように位置する、チャネルを含む再成長層とを備え、
前記再成長層は電子走行層および電子供給層を含み、前記チャネルが前記電子走行層の前記電子供給層との界面に形成される二次元電子ガスであり、
前記p型層の厚みが、前記電子走行層の厚みをdとして、d~10dの範囲にあり、かつ、前記(p型層/n型表層)界面から該n型表層内へと、該p型層におけるp型不純物濃度から濃度が減少するp型不純物傾斜層が設けられていることを特徴とする、半導体装置。 - 前記p型不純物傾斜層は、前記(p型層/n型表層)界面から前記n型表層内へと厚み0.5d~3.5dの範囲に形成されていることを特徴とする、請求項1または2に記載の半導体装置。
- 前記p型不純物傾斜層におけるp型不純物濃度勾配が、30nm/decade~300nm/decadeの範囲にあることを特徴とする、請求項1または2に記載の半導体装置。
- 前記電子走行層の厚みdが、20nm~400nmの範囲にあることを特徴とする、請求項1~3のいずれか1項に記載の半導体装置。
- 前記n型表層におけるn型不純物濃度は、前記p型層のp型不純物濃度を基準に、-25%~+25%の範囲内にあることを特徴とする、請求項1~4のいずれか1項に記載の半導体装置。
- GaN系積層体を用いた半導体装置の製造方法であって、
n型ドリフト層と、該n型ドリフト層上に位置するp型層と、該p型層上にn型表層とを形成する工程と、
前記n型表層から前記p型層を経て前記n型ドリフト層に届く開口部を設ける工程と、
前記開口部に電子走行層および電子供給層を形成する工程とを備え、
前記p型層の形成工程において、前記電子走行層の厚みをdとして、該p型層の厚みをd~10dの範囲内のいずれかとし、
前記n型表層の形成工程において、前記(p型層/n型表層)界面から該n型表層内へと、該p型層におけるp型不純物濃度から濃度が減少するp型不純物傾斜層を形成することを特徴とする、半導体装置の製造方法。 - 前記n型表層の形成工程では、前記n型表層のn型不純物濃度を、前記p型層のp型不純物濃度を基準に、-25%~+25%の範囲内にするようにドーピングして、前記p型不純物傾斜層を、前記(p型層/n型表層)界面から前記n型表層内へと厚み0.5d~3.5dの範囲に形成することを特徴とする、請求項6に記載の半導体装置の製造方法。
- 前記n型表層の形成工程では、前記p型不純物傾斜層を形成するようにドーピングするか、または、前記p型層内のp型不純物が該n型表層に拡散するように、成長温度を1030℃~1100℃の範囲にして該n型表層を成長することを特徴とする、請求項6または7に記載の半導体装置の製造方法。
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