CN110534558B - 一种栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管 - Google Patents
一种栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管 Download PDFInfo
- Publication number
- CN110534558B CN110534558B CN201910750433.1A CN201910750433A CN110534558B CN 110534558 B CN110534558 B CN 110534558B CN 201910750433 A CN201910750433 A CN 201910750433A CN 110534558 B CN110534558 B CN 110534558B
- Authority
- CN
- China
- Prior art keywords
- gallium nitride
- electrode
- base
- grid
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 51
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000002131 composite material Substances 0.000 title claims abstract description 17
- 230000000694 effects Effects 0.000 title claims abstract description 17
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 17
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 17
- 238000009792 diffusion process Methods 0.000 title abstract description 5
- 230000003071 parasitic effect Effects 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 239000011777 magnesium Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 229910052593 corundum Inorganic materials 0.000 description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明公开一种栅控双极‑场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管。该器件通过采用基区与栅极相连的电极连接方式,代替传统的氮化镓VDMOS中基区与源极短接的电极连接方式。该器件工作在关态时,器件的耐压特性与传统的氮化镓VDMOS的一致。该器件工作在开态时,由于栅极与基区相连,当在栅极接入栅压时,基区也接入一定电压,使得器件寄生的双极型晶体管开启,提供了一个新的导电通道;与此同时,器件的沟道同样能正常开启进行导电。该器件与传统的氮化镓VDMOS器件相比,在保证器件具有相同击穿电压的同时,大幅度提高了器件的导通电流,极大改善了氮化镓晶体管的导通性能。
Description
技术领域
本发明涉及半导体功率器件技术领域,具体涉及一种垂直双扩散晶体管。
背景技术
垂直双扩散金属氧化物半导体器件(VDMOS)是一种重要的功率半导体器件,具有独特的垂直导电双扩散结构。该器件具有普通MOS器件与双极晶体管共同的优点,与常规的双极晶体管相比,它的开关速度与开关损耗小,频率特性好,输入阻抗高,驱动功率小,跨导高度线性。无论是开关应用还是线性应用,VDMOS都是较为理想的功率器件,并且它是一种更为标准化的产品,所需的设计因素不多,更突出其制造能力。而如何解决功率MOSFET的击穿电压与导通电阻的冲突一直是研究热点。传统的VDMOS采用的基区与源区之间短接的电极连接方式。在开启状态下,由于基区与源区短接,寄生的双极型晶体管不会开启,器件只能在正常开启的沟道中导电。
相对于传统的硅材料,氮化镓材料具有禁带宽度大、电子漂移饱和速度高、介电常数小、导电性能好、击穿电压高、热导率大等特点,适用于制作抗辐射、高频、大功率和高密度集成的电子器件,在军事和民工等发面都有着广泛的前景,在制备宽波谱、高功率、高效率的微电子、电力电子、光电子等器件方面处于领先地位。
传统的VDMOS没有对寄生的双极型晶体管给予足够的重视,采用基区与源区之间短接的电极连接方式。在开启状态下,由于基区与源区短接,寄生的双极型晶体管不会开启,器件只能在正常开启的沟道中导电。
发明内容
本发明提出了一种栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管,旨在满足耐压要求的前提下进一步有效增加器件导通电流(降低器件导通电阻)。
本发明的技术方案如下:
一种栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管,包括:
氮化镓衬底;
在所述氮化镓衬底上外延生成的漂移区;
在所述漂移区上部两侧分别形成的两处基区;
在两处基区之间刻蚀形成的槽型栅窗口;
在所述槽型栅窗口依次淀积形成的非故意掺杂氮化镓层、氧化铝氧化层;
在所述氧化铝氧化层的凹槽内加入的多晶硅栅极;
所述非故意掺杂氮化镓层的上部向两侧分别延伸覆盖部分基区;在对应于所述部分基区的非故意掺杂氮化镓层表面形成源区;两处源区分别与所述Al2O3氧化层的上部两侧外壁邻接;
所述源区上生成源极;
所述氮化镓衬底底部生成漏极;
所述基区上生成基极;基极与栅极电连接,满足:栅极接入电压时,基区获得的电压使得器件寄生的双极型晶体管开启。
基于以上方案,本发明还进一步作了如下优化:
基极与栅极之间的连接材料可以是导体材料,使得栅极接入电压时基极与栅极电位一致。导体材料优选铜或铝。
基极与栅极之间的连接材料也可以是半导体材料,使得基极接入电压时基极电位大于栅极电位,栅极接入电压时栅极电位大于基极电位。半导体材料优选半绝缘多晶硅。
氮化镓衬底的硅掺杂浓度为1×1018cm-3~2×1018cm-3。
基区的镁掺杂浓度为1×1018cm-3~2×1018cm-3;源区的硅掺杂浓度为1×1018cm-3~2×1018cm-3;漂移区的硅掺杂浓度为1×1016cm-3~2×1016cm-3。
非故意掺杂氮化镓层的厚度为40~60nm。
基区和基极、源区和源极、漏区和漏极接触方式为欧姆接触。
槽型栅窗口纵向刻蚀深入漂移区1~4μm。
本发明技术方案的有益效果如下:
本发明应用氮化镓材料,将传统的VDMOS采用基区与源区之间短接的电极连接方式,改为采用基极与栅极相连接的电极连接方式。该器件工作在关态时,器件的耐压特性与传统的氮化镓VDMOS的一致,器件的栅极,基区和源极接地,漏极接高电位。所以器件关态工作时源区,基区和漂移区之间寄生的双极型晶体管不会开启,防止二次击穿,器件的击穿特性与传统器件击穿特性相同。该器件工作在开态时,由于栅极与基区相连。当在栅极接入栅压时,基区也接入一定电压,使得器件寄生的双极型晶体管开启,提供了一个新的导电通道;与此同时,器件的沟道同样能正常开启进行导电。
本发明与传统的氮化镓VDMOS器件相比,在保证器件具有相同击穿电压的同时,大幅度提高了器件的导通电流,极大地改善了氮化镓晶体管的导通性能。
附图说明
图1为本发明的一种栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管结构示意图。
图2基于图1所示结构示意了导电通道。其中,A为沟道形成的导电通道,B为寄生的双极型晶体管开启形成的导电通道。
附图标号说明:
1-氮化镓衬底;2-漂移区;3-非故意掺杂氮化镓层;4-Al2O3氧化层;5-基区;6-源区;7-源极,8-栅极;9-漏极;10-基极。
具体实施方式
如图1为一种栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管:
氮化镓衬底1,硅掺杂浓度为1×1018cm-3~2×1018cm-3;
在衬底上外延生成出漂移区2;漂移区2的硅掺杂浓度为1×1016cm-3~2×1016cm-3。
在漂移区上形成基区5,基区5的镁掺杂浓度为1×1018cm-3~2×1018cm-3;
在基区与漂移区部分刻蚀,深入漂移区1~4μm,形成槽型栅窗口;
在槽型栅窗口上淀积一层氮化镓,形成非故意掺杂氮化镓层3,厚度为40~60nm;
在非故意掺杂氮化镓层3上淀积一层Al2O3氧化层4;
在Al2O3氧化层4上加入多晶硅栅电极(栅极8);
在非故意掺杂氮化镓层3上形成源区6;源区6的硅掺杂浓度为1×1018cm-3~2×1018cm-3;
在源区6、基区5和衬底1底部上分别生成源极7、基极10和漏极9,均为欧姆接触;基极10与栅极8相连接。
由于非故意掺杂氮化镓层3具有更少的杂质散射和更平滑的沟道表面,相比传统Si VDMOS可以使器件获得更高的沟道迁移率。
基区5与栅极8之间的连接材料可为导体材料(如铜和铝等),栅极8接入电压时,基区5与栅极8电位一致。
基区5与栅极8之间的连接材料可为电阻材料(如半绝缘多晶硅等)。基区5接入电压时,则基区5电位大于栅极8电位;栅极8接入电压时,则栅极8电位大于基区5电位。
需要说明的是,附图中所示栅极与基极共接引出接线端子为拓扑示意,实际产品中基极和栅极相连后引出的电极,它可以从基极处直接引出或是从栅极处直接引出。所以会因基极和栅极间的电阻以及引出电极位置的不同导致栅极与基极的电位存在差异。
该器件采用基区与栅极相连的电极连接方式。该器件工作在关态时,器件的耐压特性与传统的氮化镓VDMOS的一致。器件的栅极,基区和源极接地,漏极接高电位。所以器件关态工作时源区,基区和漂移区之间寄生的双极型晶体管不工作,防止二次击穿,器件的击穿特性与传统器件击穿特性相同。该器件工作在开态时,由于栅极与基区相连。当在栅极接入栅压时,基区也接入一定电压,使得器件寄生的双极型晶体管开启,提供了一个新的导电通道B。同时,器件的沟道同样能正常开启进行导电。器件导通电流得到大幅度增加,大大降低器件的导通电阻。
本发明较之于传统氮化镓器件的导通电流密度大幅度提升,两种器件的在漂移区相同、相同击穿电压的情况下,器件的导通电流密度提升了1到3个数量级。
当然,本发明中的VDMOS也可以为P沟道,其结构与N沟道VDMOS相同,在此不再赘述。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明技术原理的前提下,还可以做出若干改进和替换,这些改进和替换的方案也落入本发明的保护范围。
Claims (10)
1.一种栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管,其特征在于,包括:
氮化镓衬底;
在所述氮化镓衬底上外延生成的漂移区;
在所述漂移区上部两侧分别形成的两处基区;
在两处基区之间刻蚀形成的槽型栅窗口;
在所述槽型栅窗口依次淀积形成的非故意掺杂氮化镓层、氧化铝氧化层;
在所述氧化铝氧化层的凹槽内加入的多晶硅栅极;
所述非故意掺杂氮化镓层的上部向两侧分别延伸覆盖部分基区;在对应于所述部分基区的非故意掺杂氮化镓层表面形成源区;两处源区分别与所述氧化铝氧化层的上部两侧外壁邻接;
所述源区上生成源极;
所述氮化镓衬底底部生成漏极;
所述基区上生成基极;基极与栅极电连接,满足:栅极接入电压时,基区获得的电压使得器件寄生的双极型晶体管开启。
2.根据权利要求1所述的栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管,其特征在于:基极与栅极之间的连接材料为导体材料,使得栅极接入电压时基极与栅极电位一致。
3.根据权利要求2所述的栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管,其特征在于:所述导体材料为铜或铝。
4.根据权利要求1所述的栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管,其特征在于:基极与栅极之间的连接材料为半导体材料,使得基极接入电压时基极电位大于栅极电位,栅极接入电压时栅极电位大于基极电位。
5.根据权利要求4所述的栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管,其特征在于:连接基极与栅极的半导体材料为半绝缘多晶硅。
6.根据权利要求1所述的栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管,其特征在于:氮化镓衬底的硅掺杂浓度为1×1018cm-3~2×1018cm-3。
7.根据权利要求1所述的栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管,其特征在于:基区的镁掺杂浓度为1×1018cm-3~2×1018cm-3;源区的硅掺杂浓度为1×1018cm-3~2×1018cm-3;漂移区的硅掺杂浓度为1×1016cm-3~2×1016cm-3。
8.根据权利要求1所述的栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管,其特征在于:所述非故意掺杂氮化镓层的厚度为40~60nm。
9.根据权利要求1所述的栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管,其特征在于:基区和基极、源区和源极、漏区和漏极接触方式为欧姆接触。
10.根据权利要求1所述的栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管,其特征在于:所述槽型栅窗口纵向刻蚀深入漂移区1~4μm。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910750433.1A CN110534558B (zh) | 2019-08-14 | 2019-08-14 | 一种栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910750433.1A CN110534558B (zh) | 2019-08-14 | 2019-08-14 | 一种栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110534558A CN110534558A (zh) | 2019-12-03 |
CN110534558B true CN110534558B (zh) | 2021-06-18 |
Family
ID=68663253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910750433.1A Active CN110534558B (zh) | 2019-08-14 | 2019-08-14 | 一种栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN110534558B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114068675A (zh) * | 2021-11-16 | 2022-02-18 | 大连海事大学 | 一种双极分裂栅增强型功率晶体管 |
CN117476631B (zh) * | 2023-12-26 | 2024-03-22 | 广东仁懋电子有限公司 | 一种氮化镓微波功率器件 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3666280B2 (ja) * | 1999-01-20 | 2005-06-29 | 富士電機ホールディングス株式会社 | 炭化けい素縦形fetおよびその製造方法 |
JP2005011846A (ja) * | 2003-06-16 | 2005-01-13 | Nissan Motor Co Ltd | 半導体装置 |
CN103151373A (zh) * | 2013-03-13 | 2013-06-12 | 胡勇海 | 扩展安全工作区的半导体器件 |
EP3284107B1 (en) * | 2015-04-14 | 2023-06-14 | Hrl Laboratories, Llc | Iii-nitride transistor with trench gate |
-
2019
- 2019-08-14 CN CN201910750433.1A patent/CN110534558B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CN110534558A (zh) | 2019-12-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN207664048U (zh) | 半导体器件 | |
JP4417677B2 (ja) | 電力用半導体装置 | |
KR100474214B1 (ko) | 실리콘 카바이드 수평 채널이 버퍼된 게이트 반도체 소자 | |
KR20110063532A (ko) | 금속 기판 상의 반도체 이종구조체 내에 스트레인드 채널을 가지는 전력 모스펫 | |
US8264015B2 (en) | Semiconductor device wherein a first insulated gate field effect transistor is connected in series with a second field effect transistor | |
CN110649096B (zh) | 一种高压n沟道HEMT器件 | |
CN102231390B (zh) | 一种超结结构的纵向双扩散金属氧化物半导体功率器件 | |
CN107251233A (zh) | 半导体装置 | |
US8653606B2 (en) | Semiconductor device and power conversion device using same | |
CN111969047B (zh) | 一种具有复合背势垒层的氮化镓异质结场效应晶体管 | |
CN110534558B (zh) | 一种栅控双极-场效应复合氮化镓垂直双扩散金属氧化物半导体晶体管 | |
CN113629135A (zh) | 一种集成沟槽和体平面栅的SiC MOSFET器件 | |
CN108538909A (zh) | 具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管及其制作方法 | |
CN114899219A (zh) | 一种具有屏蔽效应的超结P柱和N-沟道的4H-SiC基VDMOS器件 | |
WO2019085850A1 (zh) | Igbt功率器件 | |
CN113257887A (zh) | 一种具有三种区域的4H-SiC金属半导体场效应晶体管 | |
CN110544722A (zh) | 一种栅控双极-场效应复合氮化镓横向双扩散金属氧化物半导体晶体管 | |
CN109216461B (zh) | 集成肖特基二极管的u型源槽vdmosfet器件 | |
US10355132B2 (en) | Power MOSFETs with superior high frequency figure-of-merit | |
CN110190114B (zh) | 一种栅控双极-场效应复合碳化硅垂直双扩散金属氧化物半导体晶体管 | |
CN110649097A (zh) | 一种高压p沟道HEMT器件 | |
US8823098B2 (en) | Structures for power transistor and methods of manufacture | |
Loechelt et al. | A high-speed silicon FET for efficient DC-DC power conversion | |
CN110212032B (zh) | 一种栅控双极-场效应复合元素半导体基横向双扩散金属氧化物半导体晶体管 | |
CN114843332A (zh) | 低功耗高可靠性半包沟槽栅mosfet器件及制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |