CN114068675A - 一种双极分裂栅增强型功率晶体管 - Google Patents

一种双极分裂栅增强型功率晶体管 Download PDF

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CN114068675A
CN114068675A CN202111356834.2A CN202111356834A CN114068675A CN 114068675 A CN114068675 A CN 114068675A CN 202111356834 A CN202111356834 A CN 202111356834A CN 114068675 A CN114068675 A CN 114068675A
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王颖
黄昊
李兴冀
杨剑群
曹菲
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Dalian Maritime University
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/772—Field effect transistors
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Abstract

本发明公开一种双极分裂栅增强型功率晶体管，包括衬底层、漂移区、有源层、槽栅以及器件顶层；所述衬底层位于双极分裂栅增强型功率晶体管底部，所述衬底层上表面一部分与漂移区连接，所述衬底层上表面另一部分与槽栅连接；所述漂移区上表面与有源层连接；所述有源层上表面与器件顶层连接。本发明通过在ATLAS模拟器中执行二维数值模拟，证明了BiSGE结构降低了导通电阻、IDS‑VDS和品质因数特性，与SGE相比，不会影响断态击穿电压。UIS测试结果表明，BiSGE晶体管的耐用性可与SGEUMOS相媲美。

Description

一种双极分裂栅增强型功率晶体管
技术领域
本发明涉及功率半导体器件领域，特别是涉及一种双极分裂栅增强型功率晶体管。
背景技术
如今，大多数主要功率MOSFET供应商都采用了沟槽MOS结构，沟槽MOSFET导通损耗的主要贡献是沟道和漂移区电阻。沟道电阻可以通过增加栅极密度来降低。传统高栅极密度沟槽MOSFET的总电阻通常会受到漂移区电阻的限制。Resurf Stepped Oxide(RSO)结构需要将漂移区电阻降低到超过该1D硅极限。因为栅电极沿漂移区延伸并通过厚氧化物与其隔离，具有场板并增强了漂移区中的电场。由于侧壁的多晶硅场板耗尽漂移区并均匀调制电场扩散，梯度氧化物旁路(GOB)结构在中低压区具有超越超结结构的性能，并克服了超结结构中的电荷平衡。然而，与横向DMOS器件相比，RSO MOSFET表现出相对较大的开关损耗，因为更高的栅漏电容或米勒电容(CGD)，并且GOB MOSFET限制了场板和栅电极的缩放比例。因此提出了分栅RSO MOSFET、栅增强型MOSFET和分栅增强(SGE)MOSFET以改善通态电阻率和击穿电压，同时不增加CGD，有必要依此思路对传统沟槽MOS结构进行改进，以提高其性能。
发明内容
本发明的目的是提供一种双极分裂栅增强型功率晶体管，以优化器件的整体性能。
为实现上述目的，本发明提供了如下方案：本发明提供一种双极分裂栅增强型功率晶体管，包括：
衬底层、漂移区、有源层、槽栅和器件顶层；
所述衬底层位于双极分裂栅增强型功率晶体管底部，所述衬底层上表面一部分与所述漂移区连接，所述衬底层上表面另一部分与所述槽栅连接；
所述漂移区上表面与所述有源层连接；
所述有源层上表面与所述器件顶层连接。
可选地，所述衬底层由下到上设置有依次连接的漏极和衬底。
可选地，所述漏极的材料为硅；所述衬底的材料为金属。
可选地，所述漂移区为N型漂移区；所述漂移区的材料为硅。
可选地，所述有源层包括：体区、基区和源区；
所述体区下表面与所述N型漂移区上表面连接，所述体区上表面分别与所述基区和所述源区的下表面连接，且与所述槽栅邻接；
所述基区位于所述有源层的左侧，所述基区的上表面与所述器件顶层的下表面连接，且与所述体区、所述源区邻接；
所述源区下表面与所述体区的上表面连接，所述源区上表面与所述器件顶层的下表面连接，所述源区左侧与所述基区邻接，所述源区右侧与所述槽栅邻接。
可选地，所述体区与所述基区为P型，所述源区的掺杂类型为N型；所述体区、所述基区和所述源区的材料为硅。
可选地，所述器件顶层包括：基极和源极；
所述基极与所述基区的上表面连接；所述源极与所述源区的上表面连接。
可选地，所述基极与所述源极的材料为金属。
可选地，所述槽栅包括：栅氧化物层、栅极、浮体层；
所述栅极位于所述槽栅的顶层，所述栅极与所述栅氧化物层连接；
所述浮体层位于所述栅极的下方，所述浮体层与所述栅氧化物层连接；
所述栅氧化物层贯穿于所述栅极与所述浮体层之间。
可选地，所述栅极与所述浮体层的材料是多晶硅。
本发明公开了以下技术效果：
本发明提供了一种双极分裂栅增强型功率晶体管，是一种新颖的UMOSFET晶体管结构，与传统沟槽MOS结构相比，降低了通态电阻率、IDS-VDS和品质因数特性，改善了击穿电压，同时不增加栅漏电容(CGD)，优化了器件的整体性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例中一种双极分裂栅增强型功率晶体管(BiSGE)结构示意图；
图2为本发明实施例中现有的分裂栅增强型功率场效应管(SGE UMOS)结构示意图；
图3为本发明实施例中BiSGE晶体管的等效电路示意图；
图4为本发明实施例中在不同漏极偏压下BiSGE晶体管与SGE UMOS的正向导通特性示意图；
图5为本发明实施例中BiSGE晶体管与SGE UMOS的关态击穿电压特性示意图；
图6为发明实施例中(a)为UIS特性模拟测试电路；(b)为SGE UMOS和BiSGE晶体管的模拟UIS特性示意图。
附图中：1、漏极；2、衬底；3、N型漂移区；4、栅氧化层；5、浮体多晶硅层；6、多晶硅栅极；7、P-体区；8、P+基区；9、N+源区；10、基极；11、源极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
本发明提供一种双极分裂栅增强型功率晶体管，其中，结构如图1所示，包括：衬底层、漂移区、有源层、槽栅和器件顶层。
衬底层位于双极分裂栅增强型功率晶体管底部，衬底层上表面一部分与漂移区连接，衬底层上表面另一部分与槽栅连接；
漂移区上表面与有源层连接；
有源层上表面与器件顶层连接。
具体地，衬底层包括：衬底2和漏极1；漏极1位于衬底2的下表面。漏极1的材料为硅；衬底2的材料为金属。
具体地，漂移区为N型漂移区3；漂移区的材料为硅，也可以使用SiC和GaN等其它宽禁带半导体材料。
具体地，有源层包括：P-体区7、P+基区8和N+源区9；
P-体区7下表面与N型漂移区3上表面连接，P-体区7上表面分别与P+基区8和N+源区9的下表面连接，且与槽栅邻接；
P+基区8位于有源层的左侧，P+基区8的上表面与器件顶层的下表面连接，且与P-体区7、N+源区9邻接；
N+源区9下表面与P-体区7的上表面连接，N+源区9上表面与器件顶层的下表面连接，N+源区9左侧与P+基区8邻接，N+源区9右侧与槽栅邻接。
P-体区7、P+基区8、N+源区9的材料为硅，也可以使用SiC和GaN等其它宽禁带半导体材料。
具体地，器件顶层包括：基极10和源极(发射极)11；P+基区8上方是基极10、N+源区9上方是源极(发射极)11；基极10与源极(发射极)11的材料为金属。
具体地，所述槽栅包括：栅氧化物层4、多晶硅栅极6、浮体多晶硅层5；
多晶硅栅极6位于槽栅的顶层，多晶硅栅极6与栅氧化物层4连接；
浮体多晶硅层5位于多晶硅栅极6的下方，浮体多晶硅层5与栅氧化物层4连接；
栅氧化物层4贯穿于多晶硅栅极6与浮体多晶硅层5之间。
多晶硅栅极6与浮体多晶硅层5的长度、厚度可调。
如图2所示，现有的分裂栅增强型功率场效应管包括：漏极1、衬底2、N型漂移区3、栅氧化层4、浮体多晶硅层5、多晶硅栅极6、P-体区7、P+基区8、N+源区9、源极11。
在现有的分裂栅增强型功率场效应管器件顶层只有单个的源极；而本发明的器件顶层是双极的，设置有基极和源极。
使用设备模拟器对双极分裂栅增强型晶体管(BiSGE)进行数值研究，以比较SGEUMOS。根据图3至图6所示仿真结果可以得出，BiSGE结构降低了通态电阻率、IDS-VDS和品质因数特性，与SGE结构相比，由于双极并联SGE，基极与SGE结构相比，不影响断态击穿电压。栅极由导通状态下的支路电压比(ξ)决定,寄生双极结型晶体管的基极从P+插头区引出，并通过自偏置方法将其与栅极连接分支电压比(ξ)，因为ξ为0.08，当栅极电压为10V时，基极偏置为0.8V。此外，UIS测试结果表明，BiSGE晶体管的耐用性可与SGE UMOS相媲美。
以上所述的实施例仅是对本发明的优选方式进行描述，并非对本发明的范围进行限定，在不脱离本发明设计精神的前提下，本领域普通技术人员对本发明的技术方案做出的各种变形和改进，均应落入本发明权利要求书确定的保护范围内。

Claims (10)

1.一种双极分裂栅增强型功率晶体管，其特征在于，包括：
衬底层、漂移区、有源层、槽栅和器件顶层；
所述衬底层位于双极分裂栅增强型功率晶体管底部，所述衬底层上表面一部分与所述漂移区连接，所述衬底层上表面另一部分与所述槽栅连接；
所述漂移区上表面与所述有源层连接；
所述有源层上表面与所述器件顶层连接。
2.根据权利要求1所述的双极分裂栅增强型功率晶体管，其特征在于，所述衬底层由下到上设置有依次连接的漏极和衬底。
3.根据权利要求2所述的双极分裂栅增强型功率晶体管，其特征在于，所述漏极的材料为硅；所述衬底的材料为金属。
4.根据权利要求1所述的双极分裂栅增强型功率晶体管，其特征在于，所述漂移区为N型漂移区；所述漂移区的材料为硅。
5.根据权利要求4所述的双极分裂栅增强型功率晶体管，其特征在于，所述有源层包括：体区、基区和源区；
所述体区下表面与所述N型漂移区上表面连接，所述体区上表面分别与所述基区和所述源区的下表面连接，且与所述槽栅邻接；
所述基区位于所述有源层的左侧，所述基区的上表面与所述器件顶层的下表面连接，且与所述体区、所述源区邻接；
所述源区下表面与所述体区的上表面连接，所述源区上表面与所述器件顶层的下表面连接，所述源区左侧与所述基区邻接，所述源区右侧与所述槽栅邻接。
6.根据权利要求5所述的双极分裂栅增强型功率晶体管，其特征在于，所述体区与所述基区为P型，所述源区的掺杂类型为N型；所述体区、所述基区和所述源区的材料为硅。
7.根据权利要求5所述的双极分裂栅增强型功率晶体管，其特征在于，所述器件顶层包括：基极和源极；
所述基极与所述基区的上表面连接；所述源极与所述源区的上表面连接。
8.根据权利要求7所述的双极分裂栅增强型功率晶体管，其特征在于，所述基极与所述源极的材料为金属。
9.根据权利要求1所述的双极分裂栅增强型功率晶体管，其特征在于，所述槽栅包括：栅氧化物层、栅极、浮体层；
所述栅极位于所述槽栅的顶层，所述栅极与所述栅氧化物层连接；
所述浮体层位于所述栅极的下方，所述浮体层与所述栅氧化物层连接；
所述栅氧化物层贯穿于所述栅极与所述浮体层之间。
10.根据权利要求9所述的双极分裂栅增强型功率晶体管，其特征在于，所述栅极与所述浮体层的材料是多晶硅。
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